NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 856 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
eMMC Control Register (FMI_EMMCCTL)
Register
Offset
R/W
Description
Reset Value
FMI_EMMCCTL
0x820
R/W
eMMC Control Register
0x0101_0000
31
30
29
28
27
26
25
24
Reserved
NWR
23
22
21
20
19
18
17
16
BLK_CNT
15
14
13
12
11
10
9
8
DBW
SW_RST
CMD_CODE
7
6
5
4
3
2
1
0
Reserved
CLK8_OE
CLK74_OE
R2_EN
DO_EN
DI_EN
RI_EN
CO_EN
Bits
Description
[31]
Reserved
Reserved.
[30:29]
Reserved
Reserved.
[28]
Reserved
Reserved.
[27:24]
NWR
NWR Parameter for Block Write Operation
This value indicates the NWR parameter for data block write operation in eMMC clock
counts. The actual clock cycle will beNWR+1.
[23:16]
BLK_CNT
Block Counts to Be Transferred or Received
This field contains the block counts for data-in and data-out transfer. For
READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, using this
function to accelerate data transfer and improve performance. Don't fill 0x0 to this field.
Note:
For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the
actual total length is BLK_CNT * (BLK_LENGTH (FMI_EMMCBLEN[10:0]) +1).
[15]
DBW
eMMC Data Bus Width (for 1-bit / 4-bit Selection)
0 = Data bus width is 1-bit.
1 = Data bus width is 4-bit.
[14]
SW_RST
Software Engine Reset
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the internal state machine and counters. The contents of
control register will not be cleared (but RI_EN, DI_EN, DO_EN and R2_EN will be
cleared). This bit will be auto cleared after few clock cycles.
[13:8]
CMD_CODE
eMMC Command Code
This register contains the eMMC command code (0x00
– 0x3F).
[7]
Reserved
Reserved.
