NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 1124 -
Revision V1.30
NUC97
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CHNIC
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Interrupt Control/Status Register (INT_CS)
Interrupts are the communication method for Display Controller-initiated communication with the
Display Controller Driver. There are several events that may trigger an interrupt from the Display
Controller. Each specific event sets a specific bit in the INT_CS register. The Display Controller
requests an interrupt when all three of the following conditions are met:
The
DISP_INT_EN
bit in
DCCS
is set to ‘1’.
A status bit in
INT_CS
is set to ‘1’.
The corresponding enable bit in
INT_CS
for the
Status
bit is set to ‘1’.
Register
Offset
R/W
Description
Reset Value
INT_CS
0x0C
R/W
Interrupt Control/Status Register
0x0000_0000
31
30
29
28
27
26
25
24
DISP_F_INT DISP_F_STATUS
UNDERRUN_INT BUS_ERROR_INT
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
UNDERRUN_EN DISP_F_EN
Bits
Description
[31]
DISP_F_INT
Frame Display Complete Interrupt Status (Write-clear)
When write “1” value on the bit, the interrupt will be cleared.
(This status bit can be internally written no matter DISP_F_EN is enable or not)
[30]
DISP_F_STATUS
Frame Display Complete Internal Status (2), (Write-clear)
When write “1” value on the bit, it will be cleared.
(This status bit can be internally written only if DISP_F_EN is enable)
Note:
The interrupt status can be programmed for indicating frame displayed complete or
field displayed complete by FIELD_INTR (DCCS[6]).
[29]
UNDERRUN_INT
FIFO Under-run Interrupt Status (Write-clear)
When write “1” value on the bit, the interrupt will be cleared.
[28]
BUS_ERROR_INT
Bus Error Interrupt (Write-clear)
When DMA bus master receive an error response from slaves, this bit will be set.
When write “1” value on the bit, the interrupt will be cleared.
Note:
This interrupt is always enabled.
[27:2]
Reserved
Reserved.
[1]
UNDERRUN_EN
FIFO Under-run Interrupt Enable