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NUC970 Technical Reference Manual

Publication Release Date: Dec. 15, 2015

- 241 -

Revision V1.30

NUC97

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[12:8]

DQS1_ODS DQS1 Output Delay Selection

This field controls the DQS1 output delay value and source selection circuit for DQS1 output generation.
The brief circuit for this function is listed below.

DQS1_ODS

DQS1 Output

5’b0_0000

The DQS1 is generated from DRAM_CLK.

5’b0_0001

~

5’b0_1111

The DQS1 is generated from DRAM_CLK with a delay value. This delay value is
controlled by the following equation:

DQS1 delay = DQS1_ODS[11:8] * DelayCLKMUX.

DelayCLKMUX:

It’s the gate delay of a CLKMUX gate.

5’b1_0000

The DQS1 is generated from DDR_CLK/2.

5’b1_0001

~

5’b1_1111

The DQS1 is generated from DDR_CLK/2 with a delay value. This delay value is
controlled by the following equation:

DQS1 delay = DQS1_ODS[11:8] * DelayCLKMUX.

DelayCLKMUX: It’s the gate delay of a CLKMUX gate.

[7:5]

Reserved

Reserved.

[4:0]

DQS0_ODS DQS0 Output Delay Selection

This field controls the DQS0 output delay value and source selection circuit for DQS0 output generation.
The brief circuit for this function is listed below.

DQS0_ODS

DQS0 Output

5’b0_0000

The DQS0 is generated from DRAM_CLK.

5’b0_0001

~

5’b0_1111

The DQS0 is generated from DRAM_CLK with a delay value. This delay value
is controlled by the following equation:

DQS1 delay = DQS0_ODS[3:0] * DelayCLKMUX.

DelayCLKMUX: It’s the gate delay of a CLKMUX gate.

5’b1_0000

The DQS0 is generated from DDR_CLK/2.

5’b1_0001

~

5’b1_1111

The DQS1 is generated from DDR_CLK/2 with a delay value. This delay value
is controlled by the following equation:

DQS1 delay = DQS0_ODS[3:0] * DelayCLKMUX.

DelayCLKMUX: It’s the gate delay of a CLKMUX gate.

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Summary of Contents for NUC970 series

Page 1: ...usive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NuMicro micr...

Page 2: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 2 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL...

Page 3: ...2DFxxY Pin Diagram 29 3 3 2 NUC976DKxxY Pin Diagram 30 3 3 3 NUC977DKxxY Pin Diagram 31 Pin Description 32 3 4 4 BLOCK DIAGRAM 58 NUC970 Series Block Diagram 58 4 1 5 FUNCTIONAL DESCRIPTION 59 ARM ARM...

Page 4: ...ster Description 194 SDRAM Interface Controller SDIC 217 5 5 5 5 1 Overview 217 5 5 2 Features 217 5 5 3 Block Diagram 218 5 5 4 Basic Configuration 219 5 5 5 Functional Description 219 5 5 6 Register...

Page 5: ...eatures 299 5 9 3 Block Diagram 299 5 9 4 Basic Configuration 300 5 9 5 Functional Description 300 5 9 6 Register Map 304 5 9 7 Register Description 305 Timer Controller TMR 322 5 10 5 10 1 Overview 3...

Page 6: ...egister Map 367 5 13 7 Register Description 368 Windowed Watchdog Timer WWDT 372 5 14 5 14 1 Overview 372 5 14 2 Features 372 5 14 3 Block Diagram 372 5 14 4 Basic Configuration 372 5 14 5 Function De...

Page 7: ...view 516 5 18 2 Features 516 5 18 3 Block Diagram 517 5 18 4 Basic Configuration 517 5 18 5 Functional Description 518 5 18 6 Register Map 526 5 18 7 Register Description 527 SPI Interface Controller...

Page 8: ...57 5 22 5 Functional Description 657 5 22 6 Registers Map 660 5 22 7 Register Description 665 USB Host Controller USBH 717 5 23 5 23 1 Overview 717 5 23 2 Features 717 5 23 3 Block Diagram 718 5 23 4...

Page 9: ...26 7 Register Description 910 Cryptographic Accelerator CRYPTO 933 5 27 5 27 1 Overview 933 5 27 2 Features 933 5 27 3 Block Diagram 934 5 27 4 Basic Configuration 934 5 27 5 Functional description 93...

Page 10: ...1162 5 31 4 Basic Configuration 1162 5 31 5 Functional Description 1163 5 31 6 Register Map 1166 5 31 7 Register Description 1167 Analog to Digital Converter ADC 1198 5 32 5 32 1 Overview 1198 5 32 2...

Page 11: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 11 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 7 REVISION HISTORY 1250...

Page 12: ...lock Divider Block Diagram 144 Figure 5 3 9 LCD Display Controller Clock Divider Block Diagram 144 Figure 5 3 10 Reference Clock Output Divider Block Diagram 144 Figure 5 3 11 SD Card Host Controller...

Page 13: ...e 5 14 3 WWDT Reset and Reload Behavior 375 Figure 5 15 1 RTC Functional Block Diagram 385 Figure 5 16 1 UART Block Diagram 413 Figure 5 16 2 Auto Flow Control Block Diagram 414 Figure 5 16 3 UART Lin...

Page 14: ...5 19 1 SPI Block Diagram 536 Figure 5 19 2 Normal SPI Timing 538 Figure 5 19 3 Alternate Phase SCLK Clock Timing 539 Figure 5 19 4 Dual IO output Sequence 539 Figure 5 19 5 Dual IO Input Sequence 540...

Page 15: ...l Address Descriptor Table Format 848 Figure 5 25 6 PAD Physical Address Descriptor Table Fetch Modes 849 Figure 5 26 1 PAD Physical Address Descriptor Table Format 912 Figure 5 26 2 PAD Physical Addr...

Page 16: ...32 1 ADC Functional Block Diagram 1199 Figure 5 32 2 ADC Transfer Function 1200 Figure 5 32 3 Simplified Sampling Diagram 1201 Figure 5 32 4 ADC Battery Voltage Detection Diagram 1202 Figure 5 32 5 K...

Page 17: ...ist in Software Mode 442 Table 5 17 1 SC Host Controller Pin Description 476 Table 5 17 2 UART Pin Description 476 Table 5 21 1 Arbiter Arbitration Results 583 Table 5 21 2 Different CAMCMR Setting an...

Page 18: ...ates two 10 100 Mb Ethernet MAC controllers USB 2 0 HS HOST Device controller with HS transceiver embedded TFT type LCD controller CMOS sensor I F controller 2D graphics engine DES 3DES AES crypto eng...

Page 19: ...up to four booting modes Boot from USB Boot from eMMC Boot from NAND Flash Boot from SPI Flash Clock Control Support two PLLs up to 500 MHz for high performance system operation External 12 MHz high...

Page 20: ...vice Support ECC4 ECC8 ECC12 ECC15 and ECC24 BCH algorithm for ECC code generation error detection and error correction Support eMMC flash interface Support DMA function to accelerate the data transfe...

Page 21: ...lor Font Expanding BLT Support Transparent BLT Support Tile BLT Support Block Move BLT Support Copy File BLT Support Color Font Expansion Support Rectangle Fill Support RGB332 RGB565 RGB888 data forma...

Page 22: ...ble for decode Support arbitrarily 1X 8X image up scaling function for encode mode Support down scaling function 1X 16X for Y422 and Y420 1X 8X for Y444 for decode mode Support specified window decode...

Page 23: ...mmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection 11 ETU 266 ETU One 24 bit and two 8 bit time out counters for Answer to Request ATR and...

Page 24: ...rial data transfer Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Support burst mode operation that transmission and reception can be executed up to four times in a...

Page 25: ...programmable memory for key of Crypto functionality Support up to 15 times of programming and erase Low Voltage Detect LVD and Low Voltage Reset LVR Support two 2 6V and 2 8V voltage detection levels...

Page 26: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 26 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL All Green package RoHS LQFP 216 pin LQFP 128 pin...

Page 27: ...RATION NUC970 Series Part Number Naming Guide 3 1 UC 9 7 X X X X ARM Microcontroller Related Product Product Number X X Package Type N Nuvoton Standard Product 972 977 976 D LQFP Pin Count K 128pin 14...

Page 28: ...200K 146 11 2 2 2 2 1 LQFP216 40 to 85 NUC976DK62Y 64 1 2 1 2 1 5 1 4 4 200K 80 6 1 2 2 2 1 LQFP128 40 to 85 NUC976DK51Y 32 1 2 1 2 1 5 1 4 4 200K 80 6 1 2 2 2 1 LQFP128 40 to 85 NUC977DK62Y 64 1 24 2...

Page 29: ...ical Reference Manual Publication Release Date Dec 15 2015 29 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Pin Configuration 3 3 3 3 1 NUC972DFxxY Pin Diagram Figure 3 3 1 NUC972DFxxY LQFP 216 pin...

Page 30: ...UC970 Technical Reference Manual Publication Release Date Dec 15 2015 30 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 3 3 2 NUC976DKxxY Pin Diagram Figure 3 3 2 NUC976DKxxY LQFP 128 pin Pin Diagra...

Page 31: ...UC970 Technical Reference Manual Publication Release Date Dec 15 2015 31 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 3 3 3 NUC977DKxxY Pin Diagram Figure 3 3 3 NUC977DKxxY LQFP 128 pin Pin Diagra...

Page 32: ...eral purpose digital I O pin Port G Pin 0 I2C0_SCL O I2 C0 clock pin 5 4 4 PG 14 I O General purpose digital I O pin Port G Pin 14 I2S_LRCK O I2 S left right channel clock UART6_CTS I Clear to send in...

Page 33: ...rnal core power pin 13 DDR_VSS P DDR ground pin 14 11 11 DDR_VDD P DDR power pin 15 DDR_VSS P DDR ground pin 16 11 11 DDR_VDD P DDR power pin 17 DDR_VSS P DDR ground pin 18 12 12 DDR_VDD P DDR power p...

Page 34: ...ed TIMER toggle output pin INT0 I External interrupt 0 input pin 26 14 14 PG 9 I O General purpose digital I O pin Port G Pin 9 LCD_DEN O Data enable or display control signal 27 15 15 PG 8 I O Genera...

Page 35: ...ta output bit 20 UART9_RXD I Data receiver input pin for UART9 PWM0 O PWM0 output pin EBI_nCS4 O External I O chip select bank 4 34 PD 11 I O General purpose digital I O pin Port D Pin 11 LCD_DATA19 O...

Page 36: ...eral purpose digital I O pin Port A Pin 13 LCD_DATA13 O LCD pixel data output bit 13 KPI_COL5 I Keypad Column Scan Input Bus 5 PWM1 O PWM1 output pin 41 21 21 PA 12 I O General purpose digital I O pin...

Page 37: ...PA 7 I O General purpose digital I O pin Port A Pin 7 RMII0_RXDATA1 I RMII0 receive data bus bit 1 LCD_DATA7 O LCD pixel data output bit 7 KPI_ROW3 O Keypad Row Scan Output Bus 3 PWRON_SET7 I Power On...

Page 38: ...ort A Pin 2 RMII0_TXDATA0 O RMII0 Transmit Data bus bit 0 LCD_DATA2 O LCD pixel data output bit 2 PWRON_SET2 I Power On Setting bit 2 53 33 33 PA 1 I O General purpose digital I O pin Port A Pin 1 RMI...

Page 39: ...ull high 69 45 38 X32_IN I External 32 768kHz crystal input 70 46 39 X32_OUT O External 32 768kHz crystal output 71 PH 4 I O General purpose digital I O pin Port H Pin 4 KPI_ROW0 O Keypad Row Scan Out...

Page 40: ...O pin Port H Pin 8 KPI_COL0 I Keypad Column Scan Input Bus 0 SD1_DAT0 I O SD SDIO mode 1 data line bit 0 UART4_TXD O Data transmitter output pin for UART4 EBI_ADDR4 O External I O address bus bit 4 7...

Page 41: ..._ADDR8 O External I O address bus bit 8 80 IO_VDD P MCU I O power pin 81 CORE_VSS P MCU internal core ground pin 82 47 41 CORE_VDD P MCU internal core power pin 83 PH 13 I O General purpose digital I...

Page 42: ...put pin for UART7 EBI_DATA1 I O External I O data bus bit 1 INT6 I External interrupt 6 input pin 88 43 PI 2 I O General purpose digital I O pin Port I Pin 2 NAND_nWP O NAND flash srite protect UART7_...

Page 43: ...bus bit 5 SD1_CMD O SD SDIO mode 1 command response UART1_TXD O Data transmitter output pin for UART1 SPI1_SS0 O 1st SPI1 chip select pin 92 51 47 PI 6 I O General purpose digital I O pin Port I Pin...

Page 44: ...eMMC data line bit 0 SC1_DAT I O SmartCard1 data pin EBI_DATA8 I O External I O data bus bit 8 SD1_DAT1 I O SD SDIO mode 1 data line bit 1 UART1_CTS I Clear to send input pin for UART1 SPI1_DI SPI1_D...

Page 45: ...O SmartCard0 reset pin EBI_DATA11 I O External I O data bus bit 11 98 57 53 PI 12 I O General purpose digital I O pin Port I Pin 12 VCAP_DATA4 I Sensor interface data bus bit 4 NAND_DATA4 I O NAND fla...

Page 46: ...7 UART8_CTS I Clear to send input pin for UART8 SC0_CD I SmartCard0 card detect pin EBI_DATA15 I O External I O data bus bit 15 CLK_OUT O Clock output pin 102 CORE_VDD P MCU internal core power pin 1...

Page 47: ...capture input pin 109 62 PB 4 I O General purpose digital I O pin Port B Pin 4 UART6_RTS O Request to send output pin for UART6 110 63 PB 5 I O General purpose digital I O pin Port B Pin 5 UART6_CTS...

Page 48: ...pin for UART10 SPI1_SS0 O 1st SPI1 chip select pin 118 72 72 PB 13 I O General purpose digital I O pin Port B Pin 13 UART10_RXD I Data receiver input pin for UART10 SPI1_CLK O SPI1 serial clock pin 11...

Page 49: ...eMMC_DATA1 I O eMMC data line bit 1 125 PC 2 I O General purpose digital I O pin Port C Pin 2 NAND_DATA2 I O NAND flash data bus bit 2 eMMC_DATA2 I O eMMC data line bit 2 126 PC 3 I O General purpose...

Page 50: ...rpose digital I O pin Port C Pin 9 NAND_ALE O NAND flash address latch enable UART10_CTS I Clear to send input pin for UART10 TM1_CAP I Enhanced TIMER capture input pin 133 PC 10 I O General purpose d...

Page 51: ...O General purpose digital I O pin Port J Pin 0 JTAG_TCK O JTAG test clock 140 77 77 PJ 1 I O General purpose digital I O pin Port J Pin 1 JTAG_TMS O JTAG test mode select 141 78 78 PJ 2 I O General p...

Page 52: ...SD SDIO mode 0 clock 157 88 88 PD 2 I O General purpose digital I O pin Port D Pin 2 SD0_DAT0 I O SD SDIO mode 0 data line bit 0 158 89 89 PD 3 I O General purpose digital I O pin Port D Pin 3 SD0_DAT...

Page 53: ...n for UART9 CAN0_RXD I CAN bus receiver0 input PWM2 O PWM2 output pin INT2 I External interrupt 2 input pin 169 PE 13 I O General purpose digital I O pin Port E Pin 13 UART8_CTS I Clear to send input...

Page 54: ...General purpose digital I O pin Port E Pin 7 RMII1_REFCLK I RMII1 reference clock SD1_DAT3 I O SD SDIO mode 1 data line bit 3 UART1_DSR I Data set ready input pin for UART1 176 PE 6 I O General purpos...

Page 55: ...receiver input pin for UART0 182 97 97 PE 0 I O General purpose digital I O pin Port E Pin 0 UART0_TXD O Data transmitter output pin for UART0 183 98 98 IO_VDD P MCU I O power pin 184 99 99 XT1_IN I E...

Page 56: ...1 RMII0_MDIO I O RMII0 Management Data I O 196 111 111 PF 0 I O General purpose digital I O pin Port F Pin 0 RMII0_MDC O RMII0 Management Data Clock 197 112 112 PH 1 I O General purpose digital I O p...

Page 57: ...signal D 207 119 119 USB1_DP I O USB1 differential signal D 208 120 120 USB1_VDD P USB1 I O power pin 209 121 121 USB1_REXT I USB1 module reference Resister 210 122 122 USBPLL0_VDD P USB0 PLL power pi...

Page 58: ...OR HS Ext Crystal Osc 12 MHz LVR LS Ext Crystal Osc 32 768 kHz PLL x 2 UART X 11 IrDA RS 485 I2S I2C X 2 SPI X 2 PIC CCAN X 2 USB 2 0 High Speed Device USB 2 0 High Speed Host Ethernet MAC X 2 Smart C...

Page 59: ...er to choose between high performance and high code density The ARM926EJ S CPU core includes features for efficient execution of Java byte codes providing Java performance similar to JIT but without t...

Page 60: ...n only access CP15 registers with MRC and MCR instruction in a privileged mode Access CP15 registers with CDP LDC STC MCRR and MRRC instructions and unprivileged MRC or MCR instruction causes the unde...

Page 61: ...Data Cache D Cache and a write buffer The size of I Cache and D Cache in this chip is 16 KB respectively The caches features are The caches are virtual index virtual tag addressed using the Modified...

Page 62: ...the AMBA Specification Rev 2 0 To increase system performance write buffers are used to prevent AHB writes stalling the ARM926EJ S system 5 1 6 Power Management The ARM926EJ S processor can be put in...

Page 63: ...e System Memory Map System management registers for Product Identifier PDID Power On Setting System Wake Up Reset Control for on chip controllers peripherals and multi function pin control System Cont...

Page 64: ...o USB 2 0 PHY 0 while USB1_VDD USBPLL1_VDD provides 3 3V and 1 2 respectively to USB 2 0 PHY 1 IO power from DDR_VDD provides 1 8V to I O pins used to connect DDR2 SDRAM IO power from IO_VDD provides...

Page 65: ...ripherals is from 0xB000_0000 to 0xBBFF_FFFF while the memory space from 0xFFFF_0000 to 0xFFFF_FFFF is for 16 k byte internal Boot ROM This chip provides the shadow memory function The memory space fr...

Page 66: ...0xB000_0000 0xB800_0000 On Chip AHB Peripherals 0xFFFF_4000 0xFFFF_0000 Internal Boot ROM IBR 16 KB SDRAM Reserved 0xC000_0000 0x3000_0000 0x3C00_0000 Internal SRAM 56 KB Reserved Reserved 0x3C00_E000...

Page 67: ...0 Control Registers 0xB000_3000 0xB000_3FFF EMAC1_BA Ethernet MAC 1 Control Registers 0xB000_4000 0xB000_4FFF GDMA_BA GDMA Control Registers 0xB000_5000 0xB000_5FFF EHCI_BA USB EHCI Host Control Regis...

Page 68: ..._1800 0xB800_18FF WDT_BA Watch Dog Timer Control Registers 0xB800_1900 0xB800_19FF WWDT_BA Windowed Watch Dog Timer Control Registers 0xB800_2000 0xB800_2FFF AIC_BA Advance Interrupt Control Registers...

Page 69: ...used as the eMMC functionality in NUC972 while PI 10 5 used as the eMMC functionality in NUC976 and NUC977 Note 2 PC 14 0 used as the NAND functionality in NUC972 while PI 15 1 used as the NAND functi...

Page 70: ...ease Date Dec 15 2015 70 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL PA 9 8 NAND Flash ECC Type Selection 00 NAND Flash ECC type is BCH T12 01 NAND Flash ECC type is BCH T15 10 NAND Flash ECC typ...

Page 71: ...R W AHB IP Reset Control Register 0x0000_0000 SYS_APBIPRS T0 SYS_BA 0x064 R W APB IP Reset Control Register 0 0x0000_0000 SYS_APBIPRS T1 SYS_BA 0x068 R W APB IP Reset Control Register 1 0x0000_0000 SY...

Page 72: ...S_GPH_MFP L SYS_BA 0x0A8 R W GPIOH Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPH_MFP H SYS_BA 0x0AC R W GPIOH High Byte Multiple Function Control Register 0x0000_0000 SYS_GPI_MFP L S...

Page 73: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 73 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 2 7 Register Description...

Page 74: ...D008 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PRDNUML6 PRDNUML5 15 14 13 12 11 10 9 8 PRDNUML4 PRDNUML3 7 6 5 4 3 2 1 0 PRDNUML2 PRDNUML1 Bits Description 31 24 Reserved Reserved 23 20...

Page 75: ...ed Reserved 27 24 DID Device ID Read Only 0000 NUC970 0010 NUC972 1110 NUC976 1111 NUC977 DID 3 is also used to indicate NAND interface pin out location 1 b0 Pin PC 14 0 is used as NAND interface for...

Page 76: ...t OFF 4 JTAGON JTAG Interface ON OFF Selection When pin nRESET transited from low to high the value of pin PA 4 latched to JTAGON 0 Pin PJ 4 0 used as GPIO pin 1 Pin PJ 4 0 used as JTAG interface 3 WD...

Page 77: ...Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved LVD_SEL LVD_EN 7 6 5 4 3 2 1 0 Reserved LVR_EN Bits Description 31 10 Reserved Reserved 9 LVD_SEL Low Voltage Detect Threshold...

Page 78: ...2 0 port 1 PHY monitor mode Enabled 14 UPHY0MEN USB PHY 0 Monitor Enable 0 USB 2 0 port 0 PHY monitor mode Disabled 1 USB 2 0 port 0 PHY monitor mode Enabled 13 Reserved Reserved 12 GPIOLBEN GPIO Pin...

Page 79: ...timer reset is connected to nRESET pin internally 0 Watch dog timer reset not connected to nRESET pin internally 1 Watch dog timer reset connected to nRESET pin internally 7 2 Reserved Reserved 1 TDE...

Page 80: ...rupt Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved USBIDC_IEN LVD_IEN Bits Description 31 2 Rese...

Page 81: ...12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved USBIDC_IS LVD_IS Bits Description 31 18 Reserved Reserved 17 USB0_IDS USB0_ID Status 0 USB port 0 used as a USB device port 1 USB port 0 used as a USB h...

Page 82: ...0 USB host wake system up function disabled 1 USB host wake system up function enabled 30 USBD USB Device Wake System Up Enable 0 USB device wake system up function disabled 1 USB device wake system u...

Page 83: ...0 Wake System Up Enable 0 CAN 0 wake system up function disabled 1 CAN 0 wake system up function enabled 17 EMAC1 Ethernet MAC 1 Wake System Up Enable 0 Ethernet MAC 1 wake system up function disabled...

Page 84: ...p Enable 0 External Interrupt 5 wake system up function disabled 1 External Interrupt 5 wake system up function enabled 4 EINT4 External Interrupt 4 Wake System Up Enable 0 External Interrupt 4 wake s...

Page 85: ...6 EINT5 EINT4 EITN3 EINT2 EINT1 EINT0 Bits Description 31 USBH USB Host Wake System Up Status 0 USB host didn t wake system up 1 USB host waked system up 30 USBD USB Device Wake System Up Status 0 USB...

Page 86: ...m up 1 CAN 1 waked system up 18 CAN0 CAN 0 Wake System Up Status 0 CAN 0 didn t wake system up 1 CAN 0 waked system up 17 EMAC1 Ethernet MAC 1 Wake System Up Status 0 Ethernet MAC 1 didn t wake system...

Page 87: ...l Interrupt 5 Wake System Up Status 0 External Interrupt 5 didn t wake system up 1 External Interrupt 5 waked system up 4 EINT4 External Interrupt 4 Wake System Up Status 0 External Interrupt 4 didn t...

Page 88: ...le 0 SDIO controller reset disabled 1 SDIO controller reset enabled 23 CRYPTO Cryptographic Accelerator Reset Enable 0 Cryptographic Accelerator reset disabled 1 Cryptographic Accelerator reset enable...

Page 89: ...Controller Reset Enable 0 LCD controller reset disabled 1 LCD controller reset enabled 8 I2S I2 S Controller Reset Enable 0 I2 S controller reset disabled 1 I2 S controller reset enabled 7 4 Reserved...

Page 90: ...IMER2 TIMER1 TIMER0 7 6 5 4 3 2 1 0 ETIMER3 ETIMER2 ETIMER1 ETIMER0 GPIO Reserved Bits Description 31 27 Reserved Reserved 26 UART10 UART 10 Reset Enable 0 UART 10 reset disabled 1 UART 10 reset enabl...

Page 91: ...4 reset disabled 1 TIMER 4 reset enabled 11 TIMER3 TIMER 3 Reset Enable 0 TIMER 3 reset disabled 1 TIMER 3 reset enabled 10 TIMER2 TIMER 2 Reset Enable 0 TIMER 2 reset disabled 1 TIMER 2 reset enabled...

Page 92: ...Technical Reference Manual Publication Release Date Dec 15 2015 92 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 3 GPIO GPIO Reset Enable 0 GPIO reset disabled 1 GPIO reset enabled 2 0 Reserved Re...

Page 93: ...1 SMC0 Reserved CAN1 CAN0 7 6 5 4 3 2 1 0 Reserved SPI1 SPI0 Reserved I2C1 I2C0 Bits Description 31 28 Reserved Reserved 27 PWM PWM Reset Enable 0 PWM reset disabled 1 PWM reset enabled 26 MTPC MTP Co...

Page 94: ...0 CAN 0 Reset Enable 0 CAN 0 reset disabled 1 CAN 0 reset enabled 7 6 Reserved Reserved 5 SPI1 SPI 1 Reset Enable 0 SPI 1 reset disabled 1 SPI 1 reset enabled 4 SPI0 SPI 0 Reset Enable 0 SPI 0 reset d...

Page 95: ...he chip 5 WDTRSTS Chip Reset by Watchdog Timer Status 0 No reset from watchdog timer 1 Watchdog timer had issued reset signal to reset the chip 4 CPURSTS CPU Reset by CPU_LVL AHBIPRST 1 or CPU_PLS AHB...

Page 96: ..._GPA5 MFP_GPA4 15 14 13 12 11 10 9 8 MFP_GPA3 MFP_GPA2 7 6 5 4 3 2 1 0 MFP_GPA1 MFP_GPA0 Bits Description 31 28 MFP_GPA7 Pin PA 7 Multi Function Selection 0000 PA 7 0010 LCD_DATA7 0100 KPI_ROW3 Others...

Page 97: ...NUC970 TECHNICAL REFERENCE MANUAL 11 8 MFP_GPA2 Pin PA 2 Multi Function Selection 0000 PA 2 0010 LCD_DATA2 Others PA 2 7 4 MFP_GPA1 Pin PA 1 Multi Function Selection 0000 PA 1 0010 LCD_DATA1 Others P...

Page 98: ...18 17 16 MFP_GPA13 MFP_GPA12 15 14 13 12 11 10 9 8 MFP_GPA11 MFP_GPA10 7 6 5 4 3 2 1 0 MFP_GPA9 MFP_GPA8 Bits Description 31 28 MFP_GPA15 Pin PA 15 Multi Function Selection 0000 PA 15 0010 LCD_DATA15...

Page 99: ...Selection 0000 PA 11 0010 LCD_DATA11 0100 KPI_COL3 Others PA 11 11 8 MFP_GPA10 Pin PA 10 Multi Function Selection 0000 PA 10 0010 LCD_DATA10 0100 KPI_COL2 Others PA 10 7 4 MFP_GPA9 Pin PA 9 Multi Func...

Page 100: ...9 18 17 16 MFP_GPB5 MFP_GPB4 15 14 13 12 11 10 9 8 MFP_GPB3 MFP_GPB2 7 6 5 4 3 2 1 0 MFP_GPB1 MFP_GPB0 Bits Description 31 28 MFP_GPB7 Pin PB 7 Multi Function Selection 0000 PB 7 1011 SPI0_CLK Others...

Page 101: ...PB 2 Multi Function Selection 0000 PB 2 1001 UR6_TXD 1101 PWM0 1111 ETMR0_TGL Others PB 2 7 4 MFP_GPB1 Pin PB 1 Multi Function Selection 0000 PB 1 0101 NAND_RDY1 1001 UR5_RXD 1011 SPI1_SS1 1101 ETMR1_...

Page 102: ...20 19 18 17 16 MFP_GPB13 MFP_GPB12 15 14 13 12 11 10 9 8 MFP_GPB11 MFP_GPB10 7 6 5 4 3 2 1 0 MFP_GPB9 MFP_GPB8 Bits Description 31 28 MFP_GPB15 Pin PB 15 Multi Function Selection 0000 PB 15 1001 UR10_...

Page 103: ...0000 PB 11 1001 UR10_RXD 1011 SPI0_DATA3 1100 CAN0_TX Others PB 11 11 8 MFP_GPB10 Pin PB 10 Multi Function Selection 0000 PB 10 1001 UR10_TXD 1011 SPI0_DATA2 1100 CAN0_RX Others PB 10 7 4 MFP_GPB9 Pin...

Page 104: ...23 22 21 20 19 18 17 16 MFP_GPC5 MFP_GPC4 15 14 13 12 11 10 9 8 MFP_GPC3 MFP_GPC2 7 6 5 4 3 2 1 0 MFP_GPC1 MFP_GPC0 Bits Description 31 28 MFP_GPC7 Pin PC 7 Multi Function Selection 0000 PC 7 0101 NAN...

Page 105: ...lection 0000 PC 3 0101 NAND_DATA3 0110 eMMC_DATA3 Others PC 3 11 8 MFP_GPC2 Pin PC 2 Multi Function Selection 0000 PC 2 0101 NAND_DATA2 0110 eMMC_DATA2 Others PC 2 7 4 MFP_GPC1 Pin PC 1 Multi Function...

Page 106: ...GPC13 MFP_GPC12 15 14 13 12 11 10 9 8 MFP_GPC11 MFP_GPC10 7 6 5 4 3 2 1 0 MFP_GPC9 MFP_GPC8 Bits Description 31 28 Reserved Reserved 27 24 MFP_GPC14 Pin PC 14 Multi Function Selection 0000 PC 14 0101...

Page 107: ...Pin PC 10 Multi Function Selection 0000 PC 10 0101 NAND_CLE 1001 UR4_TXD 1101 ETMR2_TGL Others PC 10 7 4 MFP_GPC9 Pin PC 9 Multi Function Selection 0000 PC 9 0101 NAND_ALE 1001 UR10_CTS 1101 ETMR1_CAP...

Page 108: ...MFP_GPD4 15 14 13 12 11 10 9 8 MFP_GPD3 MFP_GPD2 7 6 5 4 3 2 1 0 MFP_GPD1 MFP_GPD0 Bits Description 31 28 MFP_GPD7 Pin PD 7 Multi Function Selection 0000 PD 7 Others PD 7 27 24 MFP_GPD6 Pin PD 6 Mult...

Page 109: ...n Release Date Dec 15 2015 109 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 7 4 MFP_GPD1 Pin PD 1 Multi Function Selection 0000 PD 1 0110 SD0_CLK Others PD 1 3 0 MFP_GPD0 Pin PD 0 Multi Function S...

Page 110: ...27 26 25 24 MFP_GPD15 MFP_GPD14 23 22 21 20 19 18 17 16 MFP_GPD13 MFP_GPD12 15 14 13 12 11 10 9 8 MFP_GPD11 MFP_GPD10 7 6 5 4 3 2 1 0 MFP_GPD9 MFP_GPD8 Bits Description 31 28 MFP_GPD15 Pin PD 15 Multi...

Page 111: ...S4 Others PD 12 15 12 MFP_GPD11 Pin PD 11 Multi Function Selection 0000 PD 11 0010 LCD_DATA19 1001 UR9_TXD 1110 EBI_nCS3 Others PD 11 11 8 MFP_GPD10 Pin PD 10 Multi Function Selection 0000 PD 10 0010...

Page 112: ...MFP_GPE5 MFP_GPE4 15 14 13 12 11 10 9 8 MFP_GPE3 MFP_GPE2 7 6 5 4 3 2 1 0 MFP_GPE1 MFP_GPE0 Bits Description 31 28 MFP_GPE7 Pin PE 7 Multi Function Selection 0000 PE 7 0001 RMII1_REFCLK 0110 SD1_DATA3...

Page 113: ...nction Selection 0000 PE 3 0001 RMII1_MDIO 0110 SD1_CLK 1001 UR1_RXD Others PE 3 11 8 MFP_GPE2 Pin PE 2 Multi Function Selection 0000 PE 2 0001 RMII1_MDC 0110 SD1_CMD 1001 UR1_TXD Others PE 2 7 4 MFP_...

Page 114: ...MFP_GPE12 15 14 13 12 11 10 9 8 MFP_GPE11 MFP_GPE10 7 6 5 4 3 2 1 0 MFP_GPE9 MFP_GPE8 Bits Description 31 28 MFP_GPE15 Pin PE 15 Multi Function Selection 0000 PE 15 0111 USBH_PPWR1 Others PE 15 27 24...

Page 115: ...MFP_GPE10 Pin PE 10 Multi Function Selection 0000 PE 10 0001 RMII1_CRSDV 1001 UR8_TXD Others PE 10 7 4 MFP_GPE9 Pin PE 9 Multi Function Selection 0000 PE 9 0001 RMII1_RXDATA1 0110 SD1_nPWR 1001 UR1_n...

Page 116: ...12 11 10 9 8 MFP_GPF3 MFP_GPF2 7 6 5 4 3 2 1 0 MFP_GPF1 MFP_GPF0 Bits Description 31 28 MFP_GPF7 Pin PF 7 Multi Function Selection 0000 PF 7 0001 RMII0_RXDATA1 Others PF 7 27 24 MFP_GPF6 Pin PF 6 Mult...

Page 117: ...Release Date Dec 15 2015 117 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 7 4 MFP_GPF1 Pin PF 1 Multi Function Selection 0000 PF 1 0001 RMII0_MDIO Others PF 1 3 0 MFP_GPF0 Pin PF 0 Multi Function...

Page 118: ...14 23 22 21 20 19 18 17 16 MFP_GPF13 MFP_GPF12 15 14 13 12 11 10 9 8 MFP_GPF11 MFP_GPF10 7 6 5 4 3 2 1 0 MFP_GPF9 MFP_GPF8 Bits Description 31 28 MFP_GPF15 Pin PF 15 Multi Function Selection 0000 PF 1...

Page 119: ...Multi Function Selection 0000 PF 11 1001 UR2_TXD 1101 ETMR2_TGL 1111 EINT0 Others PF 11 11 8 MFP_GPF10 Pin PF 10 Multi Function Selection 0000 PF 10 0111 USBH_PPWR Others PF 10 7 4 MFP_GPF9 Pin PF 9...

Page 120: ...P_GPG5 MFP_GPG4 15 14 13 12 11 10 9 8 MFP_GPG3 MFP_GPG2 7 6 5 4 3 2 1 0 MFP_GPG1 MFP_GPG0 Bits Description 31 28 MFP_GPG7 Pin PG 7 Multi Function Selection 0000 PG 7 0010 LCD_HSYNC Others PG 7 27 24 M...

Page 121: ...30 NUC970 TECHNICAL REFERENCE MANUAL 11 8 MFP_GPG2 Pin PG 2 Multi Function Selection 0000 PG 2 1000 I2C1_SCL Others PG 2 7 4 MFP_GPG1 Pin PG 1 Multi Function Selection 0000 PG 1 1000 I2C0_SDA Others P...

Page 122: ...1 20 19 18 17 16 MFP_GPG13 MFP_GPG12 15 14 13 12 11 10 9 8 MFP_GPG11 MFP_GPG10 7 6 5 4 3 2 1 0 MFP_GPG9 MFP_GPG8 Bits Description 31 28 MFP_GPG15 Pin PG 15 Multi Function Selection 0000 PG 15 1111 EIN...

Page 123: ...Function Selection 0000 PG 11 1000 I2S_DATAO 1001 UR6_TXD 1010 SMC0_CLK Others PG 11 11 8 MFP_GPG10 Pin PG 10 Multi Function Selection 0000 PG 10 1000 I2S_SYSCLK 1010 SMC0_RST Others PG 10 7 4 MFP_GP...

Page 124: ...MFP_GPH7 MFP_GPH6 23 22 21 20 19 18 17 16 MFP_GPH5 MFP_GPH4 15 14 13 12 11 10 9 8 MFP_GPH3 MFP_GPH2 7 6 5 4 3 2 1 0 MFP_GPH1 MFP_GPH0 Bits Description 31 28 MFP_GPH7 Pin PH 7 Multi Function Selection...

Page 125: ...4 15 12 MFP_GPH3 Pin PH 3 Multi Function Selection 0000 PH 3 1000 I2C1_SDA 1001 UR9_RXD 1100 CAN0_TX 1101 PWM3 1111 EINT3 Others PH 3 11 8 MFP_GPH2 Pin PH 2 Multi Function Selection 0000 PH 2 1000 I2C...

Page 126: ...FP_GPH14 23 22 21 20 19 18 17 16 MFP_GPH13 MFP_GPH12 15 14 13 12 11 10 9 8 MFP_GPH11 MFP_GPH10 7 6 5 4 3 2 1 0 MFP_GPH9 MFP_GPH8 Bits Description 31 28 MFP_GPH15 Pin PH 15 Multi Function Selection 000...

Page 127: ...11 Multi Function Selection 0000 PH 11 0100 KPI_COL3 0110 SD1_DATA3 1001 UR4_CTS 1110 EBI_ADDR7 Others PH 11 11 8 MFP_GPH10 Pin PH 10 Multi Function Selection 0000 PH 10 0100 KPI_COL2 0110 SD1_DATA2 1...

Page 128: ...25 24 MFP_GPI7 MFP_GPI6 23 22 21 20 19 18 17 16 MFP_GPI5 MFP_GPI4 15 14 13 12 11 10 9 8 MFP_GPI3 MFP_GPI2 7 6 5 4 3 2 1 0 MFP_GPI1 MFP_GPI0 Bits Description 31 28 MFP_GPI7 Pin PI 7 Multi Function Sele...

Page 129: ...P_PCLK 0101 NAND_CLE 1000 I2C1_SDA 1100 CAN0_TX 1110 EBI_DATA4 Others PI 4 15 12 MFP_GPI3 Pin PI 3 Multi Function Selection 0000 PI 3 0011 VCAP_CLKO 0101 NAND_ALE 1000 I2C1_SCL 1100 CAN0_RX 1101 RTC_T...

Page 130: ...ster 0x0000_0000 31 30 29 28 27 26 25 24 MFP_GPI15 MFP_GPI14 23 22 21 20 19 18 17 16 MFP_GPI13 MFP_GPI12 15 14 13 12 11 10 9 8 MFP_GPI11 MFP_GPI10 7 6 5 4 3 2 1 0 MFP_GPI9 MFP_GPI8 Bits Description 31...

Page 131: ...SD1_nCD 0101 NAND_DATA4 1001 UR8_TXD 1010 SMC0_CLK 1110 EBI_DATA12 Others PI 12 15 12 MFP_GPI11 Pin PI 11 Multi Function Selection 0000 PI 11 0011 VCAP_DATA3 0101 NAND_DATA3 1010 SMC0_RST 1110 EBI_DA...

Page 132: ...15 2015 132 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 3 0 MFP_GPI8 Pin PI 8 Multi Function Selection 0000 PI 8 0011 VCAP_DATA0 0100 SD1_DATA1 0101 NAND_DATA0 0110 eMMC_DATA0 1001 UR1_CTS 1010 S...

Page 133: ...ved MFP_GPJ4 15 14 13 12 11 10 9 8 MFP_GPJ3 MFP_GPJ2 7 6 5 4 3 2 1 0 MFP_GPJ1 MFP_GPJ0 Bits Description 31 20 Reserved Reserved 19 16 MFP_GPJ4 Pin PJ 4 Multi Function Selection 0000 PJ 4 1111 JTAG_nTR...

Page 134: ...DATA_DS ADDR_DS CTRL_DS CLK_DS Bits Description 31 8 Reserved Reserved 7 6 DATA_DS DDR Data I O Driving Strength Selection This bit controls the driving strength for DDR I O used as data 00 Reserved...

Page 135: ...se Date Dec 15 2015 135 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 1 0 CLK_DS DDR Clock I O Driving Strength Selection This bit controls the driving strength for DDR I O used as clock 00 Reserve...

Page 136: ...ite protection Bits When powered on the Power On Reset POR circuit generates a reset signal to reset whole chip function However after power is ready the POR circuit would consume a few power To minim...

Page 137: ...ction is disabled user can check the protection disable bit at address 0xB000_01FC bit0 1 is protection disable and 0 is protection enable Then user can update the target protected register value and...

Page 138: ...nored 1 Write protection Disabled for writing protected registers The protected registers are SYS_PDID Product Identifier Register address 0xB000_0000 SYS_MISCFCR Miscellaneous Function Control Regist...

Page 139: ...omes from the PLL or from the external crystal input directly For each clock there is a bit on the CLKEN register to control the clock ON or OFF individually and the divider setting is in the CLK_DIVC...

Page 140: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 140 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 3 3 Block diagram Clock Controller Top View 5 3 3 1...

Page 141: ...W_DIV UART7_SW_DIV UART8_SW_DIV UART9_SW_DIV UART10_SW_DIV USB_SW_DIV ECLKWDT ECLKTIMER0 ECLKTIMER1 ECLKTIMER2 ECLKTIMER3 ECLKTIMER4 GPIO_SW_DIV ECLKWWDT ECLKGPIO KPI_SW_DIV ECLKKPI SYS_SW_DIV SYS_CLK...

Page 142: ...ivider 5 3 3 3 APLLFout eMMC_SDIV CLK_DIVCTL3 2 0 eMMC_N CLK_DIVCTL3 15 8 eMMC_SrcCLK eMMC_CLK eMMC CLK_HCLKEN 22 ACLKOut UCLKout CLK_SW4 4 to 1 MUX CLK_DIVn eMMC_N 1 UPLLFout eMMC_S CLK_DIVCTL3 4 3 X...

Page 143: ...rcCLK ECLKGPIO GPIO CLK_PCLKEN0 3 CLK_SW2 2 to 1 MUX CLK_DIVn GPIO_N 1 X32_IN 32 768 kHz GPIO_S CLK_DIVCTL7 7 GPIO_N CLK_DIVCTL7 6 0 Note Before clock switching both the pre selected and newly selecte...

Page 144: ...CD_SrcCLK ECLKLCD LCD CLK_HCLKEN 25 ACLKOut UCLKout CLK_SW4 4 to 1 MUX CLK_DIVn LCD_N 1 UPLLFout LCD_S CLK_DIVCTL1 4 3 XT1_IN CLK_DIVn LCD_SDIV 1 CLK_DIVn LCD_SDIV 1 Note Before clock switching both t...

Page 145: ...rd Host Controller Clock Divider 5 3 3 12 XT1_IN 12 MHz ECLKSMCx SMCx CLK_PCLKEN1 x 12 CLK_DIVn SMCx_N 1 SMCx_N CLK_DIVCTL6 x 4 27 x 4 24 x 0 1 Note Before clock switching both the pre selected and ne...

Page 146: ...gure 5 3 14 UART Clock Divider Block Diagram USB 1 1 Host 48 MHz Clock Divider 5 3 3 15 USBPHY0_480M USB11_SrcCLK USB_CLK 48MZ USBH CLK_HCLKEN 18 CLK_SW2 2 to 1 MUX CLK_DIVn 10 USBPHY1_480M USBID SYS_...

Page 147: ...imer Clock Divider 5 3 3 17 WWDT_SrcCLK ECLKWWDT WWDT CLK_PCLKEN0 1 CLK_SW4 4 to 1 MUX WWDT_S CLK_DIVCTL8 11 10 XT1_IN 12 MHz X32_IN 32 768 kHz XT1_IN 128 PCLK 4096 Note Before clock switching both th...

Page 148: ...CLK_PCLKEN0 16 PCLKUART0 UART1 CLK_PCLKEN0 17 PCLKUART1 PCLKUART2 UART3 CLK_PCLKEN0 19 PCLKUART3 UART2 CLK_PCLKEN0 18 UART4 CLK_PCLKEN0 20 PCLKUART4 UART5 CLK_PCLKEN0 21 PCLKUART5 PCLKUART6 UART7 CLK...

Page 149: ...processor into a low power state until either an interrupt IRQ or FIQ or a debug request occurs In this mode the clocks of all functionalities are on The clock frequency of DRAM AHB peripherals and AP...

Page 150: ...3 4 5 To extremely reduce the power consumption user could put the chip inot Deep Power down mode without SRAM retention by turning off power supply to all power pin except RTC_VDD In this mode only R...

Page 151: ...TL1 CLK_BA 0x024 R W Clock Divider Control Register 1 0x0000_0000 CLK_DIVCTL2 CLK_BA 0x028 R W Clock Divider Control Register 2 0x0000_0000 CLK_DIVCTL3 CLK_BA 0x02C R W Clock Divider Control Register...

Page 152: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 152 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 3 6 Register description...

Page 153: ...d 23 22 21 20 19 18 17 16 PRESCALE 15 14 13 12 11 10 9 8 PRESCALE 7 6 5 4 3 2 1 0 Reserved SEN_OFF_ST Reserved XIN_CTL XTAL_EN Bits Description 31 24 Reserved Reserved 23 8 PRESCALE Pre scalar Counter...

Page 154: ...Controller Clock Enable 0 SD card controller clock disabled 1 SD card controller clock enabled 29 JPEG JPEG Codec Clock Enable 0 JPEG codec clock disabled 1 JPEG codec clock enabled 28 GE2D 2D Graphi...

Page 155: ...Host Controller Clock Enable 0 USB host controller clock disabled 1 USB host controller clock enabled 17 EMAC1 Ethernet MAC Controller 1 Clock Enable 0 Ethernet MAC controller 1 clock disabled 1 Ether...

Page 156: ...ernal AHB 4 Bus Clock Enable 0 Internal AHB 4 bus clock disabled 1 Internal AHB 4 bus clock enabled 3 HCLK3 Internal AHB 3 Bus Clock Enable 0 Internal AHB 3 bus clock disabled 1 Internal AHB 3 bus clo...

Page 157: ...TIMER3 TIMER2 TIMER1 TIMER0 7 6 5 4 3 2 1 0 ETIMER3 ETIMER2 ETIMER1 ETIMER0 GPIO RTC WWDT WDT Bits Description 31 27 Reserved Reserved 26 UART10 UART 10 Clock Enable 0 UART 10 clock disabled 1 UART 10...

Page 158: ...R3 Timer 3 Clock Enable 0 Timer 3 clock disabled 1 Timer 3 clock enabled 10 TIMER2 Timer 2 Clock Enable 0 Timer 2 clock disabled 1 Timer 2 clock enabled 9 TIMER1 Timer 1 Clock Enable 0 Timer 1 clock d...

Page 159: ...roller Clock Enable 0 GPIO controller clock disabled 1 GPIO controller clock enabled 2 RTC RTC Clock Enable 0 RTC clock disabled 1 RTC clock enabled 1 WWDT Windowed Watch dog Clock Enable 0 Windowed W...

Page 160: ...served 27 PWM PWM Clock Enable 0 PWM clock disabled 1 PWM clock enabled 26 MTPC MTP Controller Clock Enable 0 MTP controller clock disabled 1 MTP controller clock enabled 25 KPI Keypad Controller Cloc...

Page 161: ...SPI Interface 1 Clock Enable 0 SPI Interface 1 clock disabled 1 SPI Interface 1 clock enabled 4 SPI0 SPI Interface 0 Clock Enable 0 SPI Interface 0 clock disabled 1 SPI Interface 0 clock enabled 3 2 R...

Page 162: ...ber is PCLK_N 1 So PCLK HCLK1 PCLK_N 1 23 20 HCLK234_N AHB234 Clock Divider This field defines the clock divide number for clock divider to generate the HCLK for AHB2 AHB3 AHB4 bus and controllers in...

Page 163: ...cCLK is from XIN 01 Reserved 10 SYSTEM_SrcCLK is from ACLKOut 11 SYSTEM_SrcCLK is from UCLKOut 2 0 SYSTEM_SDIV System Source Clock Divider This field defines the source clock divide number for clock d...

Page 164: ...23 21 Reserved Reserved 20 19 I2S_S I2 S Controller Clock Source Selection This field selects which clock is used to be the source of engine clock for I2 S controller 00 I2S_SrcCLK is from XIN 01 Rese...

Page 165: ...ontroller 00 LCD_SrcCLK is from XIN 01 Reserved 10 LCD_SrcCLK is from ACLKOut 11 LCD_SrcCLK is from UCLKOut 2 0 LCD_SDIV LCD Engine Source Clock Divider This field defines the source clock divide numb...

Page 166: ...mber for clock divider to generate the engine clock for GE2D codec The actual clock divide number is GE2D_N 1 So ECLKge2d HCLK3 GE2D_N 1 27 12 Reserved Reserved 11 8 USB_N USB 1 1 Host Controller Engi...

Page 167: ...vide number is JPG_N 1 So ECLKjpg HCLK3 JPG_N 1 27 24 SENSOR_N Sensor Clock Divider This field defines the clock divide number for clock divider to generate the sensor clock The actual clock divide nu...

Page 168: ...C_S eMMC Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for eMMC controller 00 eMMC_SrcCLK XIN 01 eMMC_SrcCLK Reserved 10 eMMC_SrcCLK ACLKOut 11...

Page 169: ...N 1 So ECLKuart3 UART3_SrcCLK UART3_N 1 28 27 UART3_S UART3 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART3 controller 00 UART3_SrcCLK i...

Page 170: ..._N 1 So ECLKuart1 UART1_SrcCLK UART1_N 1 12 11 UART1_S UART1 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART1 controller 00 UART1_SrcCLK...

Page 171: ...ne Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output This field only takes effect while the UART0_S CLK_DIVCTL4 4 3 is 2 b10 APLL or 2 b1...

Page 172: ...N 1 So ECLKuart7 UART7_SrcCLK UART7_N 1 28 27 UART7_S UART7 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART7 controller 00 UART7_SrcCLK i...

Page 173: ..._N 1 So ECLKuart5 UART5_SrcCLK UART5_N 1 12 11 UART5_S UART5 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART5 controller 00 UART5_SrcCLK...

Page 174: ...Engine Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output This field only takes effect while the UART4_S CLK_DIVCTL5 4 3 is 2 b10 APLL or...

Page 175: ...clock for Smart card controller The actual clock divide number is SMC1_N 1 So ECLKsmc1 XIN12M SMC1_N 1 27 24 SMC0_N Smart Card 0 Engine Clock Divider This field defines the clock divide number for cl...

Page 176: ...V UART9 Engine Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output This field only takes effect while the UART9_S CLK_DIVCTL6 12 11 is 2 b1...

Page 177: ...ber is ADC_N 1 So ADC_CLK ADC_SrcCLK ADC_N 1 23 21 Reserved Reserved 20 19 ADC_S ADC Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for ADC contr...

Page 178: ...I controller The actual clock divide number is KPI_N 1 So ECLKkpi KPI_SrcCLK KPI_N 1 7 GPIO_S GPIO Engine Clock Source Selection This field selects which clock is used to be the source of engine clock...

Page 179: ...lection This field selects which clock is used to be the source of engine clock for Enhanced Timer 3 controller 00 ETIMER3_SrcCLK XIN 01 ETIMER3_SrcCLK PCLK 10 ETIMER3_SrcCLK PCLK 4096 11 ETIMER3_SrcC...

Page 180: ...tion This field selects which clock is used to be the source of engine clock for WWDT controller 00 WWDT_SrcCLK XIN 01 WWDT_SrcCLK XIN 128 10 WWDT_SrcCLK PCLK 4096 11 WWDT_SrcCLK 32 768 kHz 9 8 WDT_S...

Page 181: ...21 Reserved Reserved 20 19 CKO_S Reference Clock Out Source Selection This field selects which clock is used to be the source of reference clock output 00 CKO_SrcCLK is from XIN 01 Reserved 10 CKO_Src...

Page 182: ...troller 00 SDH_SrcCLK is from XIN 01 Reserved 10 SDH_SrcCLK is from ACLKOut 11 SDH_SrcCLK is from UCLKOut 2 0 SDH_SDIV SD Host Engine Source Clock Divider This field defines the source clock divide nu...

Page 183: ...ble Flag 0 PLL is not stable 1 PLL is stable 500us after PLL setting changed 30 RESETN Reset Mode Enable 0 PLL is in reset mode 1 PLL is in normal operation mode Default 29 BYPASS Bypass Mode Enable 0...

Page 184: ...M from 1 to 64 The M IN_DV 5 0 1 6 0 FB_DV PLL VCO Output Clock Feedback Divider Integer Part Set the feedback divider factor N from 1 to 128 The N FB_DV 6 0 1 The formula to calculate the PLL output...

Page 185: ...l Register CLK_PLLSTBCNTR Register Offset R W Description Reset Value CLK_PLLSTBC NTR CLK_BA 0x080 R W PLL Stable Counter and Test Clock Control Register 0x0000_1800 31 30 29 28 27 26 25 24 Reserved 2...

Page 186: ...t priority and the priority level 7 is the lowest In order to make this scheme work properly a certain priority level must be specified to each interrupt source during power on initialization otherwis...

Page 187: ...rrupt vector table to select the appropriate interrupt service routine vector Priority Controller 5 4 4 2 An 8 level priority encoder controls the NIRQ line Each interrupt source belongs to priority g...

Page 188: ...FIQ can be enabled or disabled individually by using the command registers AIC_MECR and AIC_MDCR The status of interrupt mask can be read from the read only register AIC_IMR A disabled interrupt doesn...

Page 189: ...debug system must not write to the AIC_IPER as this would cause undesirable effects The following table shows the main steps of an interrupt and the order in which they are performed according to the...

Page 190: ...T Positive Level EMC 0 RX Interrupt 20 EMC1_RX_INT Positive Level EMC 1 RX Interrupt 21 EMC0_TX_INT Positive Level EMC 0 TX Interrupt 22 EMC1_TX_INT Positive Level EMC 1 TX Interrupt 23 EHCI_INT Posit...

Page 191: ...r 0 Interrupt 48 ETMR1_INT Positive Level Enhanced Timer 1 Interrupt 49 ETMR2_INT Positive Level Enhanced Timer 2 Interrupt 50 ETMR3_INT Positive Level Enhanced Timer 3 Interrupt 51 SPI0_INT Positive...

Page 192: ...0x030 R W AIC Source Control Register 13 0x4747_4747 AIC_SCR14 AIC_BA 0x034 R W AIC Source Control Register 14 0x4747_4747 AIC_SCR15 AIC_BA 0x038 R W AIC Source Control Register 15 0x4747_4747 AIC_SC...

Page 193: ...Register High Undefined AIC_SSCR AIC_BA 0x140 W AIC Source Set Command Register Undefined AIC_SSCRH AIC_BA 0x144 W AIC Source Set Command Register High Undefined AIC_SCCR AIC_BA 0x148 W AIC Source Cle...

Page 194: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 194 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 4 6 Register Description...

Page 195: ...7 AIC_SCR10 AIC_BA 0x024 R W AIC Source Control Register 10 0x4747_4747 AIC_SCR11 AIC_BA 0x028 R W AIC Source Control Register 11 0x4747_4747 AIC_SCR12 AIC_BA 0x02C R W AIC Source Control Register 12...

Page 196: ...riority Level 0 7 The level 0 indicates the highest priority and the level 7 indicates the lowest priority An interrupt is treated as a FIQ for the priority level 0 and is treated as an IRQ for other...

Page 197: ...S28 IRS27 IRS26 IRS25 IRS24 23 22 21 20 19 18 17 16 IRS23 IRS22 IRS21 IRS20 IRS19 IRS18 IRS17 IRS16 15 14 13 12 11 10 9 8 IRS15 IRS14 IRS13 IRS12 IRS11 IRS10 IRS9 IRS8 7 6 5 4 3 2 1 0 IRS7 IRS6 IRS5 I...

Page 198: ...R60 ISR59 ISR58 ISR57 IRS56 23 22 21 20 19 18 17 16 IRS55 IRS54 IRS53 IRS52 IRS51 IRS50 IRS49 IRS48 15 14 13 12 11 10 9 8 IRS47 IRS46 IRS45 IRS44 IRS43 IRS42 IRS41 IRS40 7 6 5 4 3 2 1 0 IRS39 IRS38 IR...

Page 199: ...ffset R W Description Reset Value AIC_IASR AIC_BA 0x108 R AIC Interrupt Active Status Register 0x0000_0000 31 30 29 28 27 26 25 24 IAS31 IAS30 IAS29 IAS28 IAS27 IAS26 IAS25 IAS24 23 22 21 20 19 18 17...

Page 200: ...ription Reset Value AIC_IASRH AIC_BA 0x10C R AIC Interrupt Active Status Register High 0x0000_0000 31 30 29 28 27 26 25 24 Reserved IAS61 IAS60 IAS59 IAS58 IAS57 IAS56 23 22 21 20 19 18 17 16 IAS55 IA...

Page 201: ...29 28 27 26 25 24 IS31 IS30 IS29 IS28 IS27 IS26 IS25 IS24 23 22 21 20 19 18 17 16 IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16 15 14 13 12 11 10 9 8 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 7 6 5 4 3 2 1 0 IS...

Page 202: ...26 25 24 Reserved IS61 IS60 IS59 IS58 IS57 IS56 23 22 21 20 19 18 17 16 IS55 IS54 IS53 IS52 IS51 IS50 IS49 IS48 15 14 13 12 11 10 9 8 IS47 IS46 IS45 IS44 IS43 IS42 IS41 IS40 7 6 5 4 3 2 1 0 IS39 IS38...

Page 203: ...C_ISNR thereafter by the AIC This register was restored a value 0 after it was read by the interrupt handler This register can help indexing into a branch table to quickly jump to the corresponding in...

Page 204: ...pt channel number that is active enabled and has the highest priority Register Offset R W Description Reset Value AIC_ISNR AIC_BA 0x120 R AIC Interrupt Source Number Register 0x0000_0000 31 30 29 28 2...

Page 205: ...RQ and FIQ are equal to 0 it means there is no interrupt occurred Register Offset R W Description Reset Value AIC_OISR AIC_BA 0x124 R AIC Output Interrupt Status Register 0x0000_0000 31 30 29 28 27 26...

Page 206: ...IM16 15 14 13 12 11 10 9 8 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 7 6 5 4 3 2 1 0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 Reserved Bits Description 31 1 IM x Interrupt Mask This bit determines whether the corresp...

Page 207: ...14 13 12 11 10 9 8 IM47 IM46 IM45 IM44 IM43 IM42 IM41 IM40 7 6 5 4 3 2 1 0 IM39 IM38 IM37 IM36 IM35 IM34 IM33 IM32 Bits Description 31 30 Reserved Reserved 29 0 IM x Interrupt Mask This bit determines...

Page 208: ...x130 W AIC Mask Enable Command Register Undefined 31 30 29 28 27 26 25 24 MEC31 MEC30 MEC29 MEC28 MEC27 MEC26 MEC25 MEC24 23 22 21 20 19 18 17 16 MEC23 MEC22 MEC21 MEC20 MEC19 MEC18 MEC17 MEC16 15 14...

Page 209: ...sk Enable Command Register High Undefined 31 30 29 28 27 26 25 24 Reserved MEC61 MEC60 MEC59 MEC58 MEC57 MEC56 23 22 21 20 19 18 17 16 MEC55 MEC54 MEC53 MEC52 MEC51 MEC50 MEC49 MEC48 15 14 13 12 11 10...

Page 210: ...138 W AIC Mask Disable Command Register Undefined 31 30 29 28 27 26 25 24 MDC31 MDC30 MDC29 MDC28 MDC27 MDC26 MDC25 MDC24 23 22 21 20 19 18 17 16 MDC23 MDC22 MDC21 MDC20 MDC19 MDC18 MDC17 MDC16 15 14...

Page 211: ...k Disable Command Register High Undefined 31 30 29 28 27 26 25 24 Reserved MDC61 MDC60 MDC59 MDC58 MDC57 MDC56 23 22 21 20 19 18 17 16 MDC55 MDC54 MDC53 MDC52 MDC51 MDC50 MDC49 MDC48 15 14 13 12 11 10...

Page 212: ...ardware verification or software debugging Register Offset R W Description Reset Value AIC_SSCR AIC_BA 0x140 W AIC Source Set Command Register Undefined 31 30 29 28 27 26 25 24 SSC31 SSC30 SSC29 SSC28...

Page 213: ...cation or software debugging Register Offset R W Description Reset Value AIC_SSCRH AIC_BA 0x144 W AIC Source Set Command Register High Undefined 31 30 29 28 27 26 25 24 Reserved SSC61 SSC60 SSC59 SSC5...

Page 214: ...ardware verification or software debugging Register Offset R W Description Reset Value AIC_SCCR AIC_BA 0x148 W AIC Source Clear Command Register Undefined 31 30 29 28 27 26 25 24 SCC31 SCC30 SCC29 SCC...

Page 215: ...ication or software debugging Register Offset R W Description Reset Value AIC_SCCRH AIC_BA 0x14C W AIC Source Clear Command Register High Undefined 31 30 29 28 27 26 25 24 Reserved SCC61 SCC60 SCC59 S...

Page 216: ...to this register to indicate the end of its interrupt service Register Offset R W Description Reset Value AIC_EOSCR AIC_BA 0x150 W AIC End of Service Command Register Undefined 31 30 29 28 27 26 25 2...

Page 217: ...r The maximum EAHB access number is 16 The SDRAM controller also builds a BIST module to test the external memory device An internal arbiter is used to schedule the access from the masters and the BIS...

Page 218: ...s AHB 3 Bus BIST SDRAM _BIST Scheduler ReqSchedule Queue 0 Queue 1 SDRAM Type SdramType Refresh Counter PWR_REF Bank Control BankCtl SDRAM FSM SdramFSM Skew Control CLK_MUX SDRAM FSM SdramFSM I O PAD...

Page 219: ...control the SDRAM to enter self refresh mode to reduce the power consumption in power down mode The SDIC provides the fixed sequential burst type and burst length is 4 In addition SDIC implements som...

Page 220: ...ply a MRS Mode Register Set command to MR Mode Register with A8 high to set DDR SDRAM in normal operation with resetting the DLL This is accomplished by writing appropriate value with bit 8 high to th...

Page 221: ...d completed 12 Apply two or more AUTOREFRESH commands This is accomplished by writing 1 to REF_CMD SDIC_CMD 3 twice or more The REF_CMD is auto cleared after SDRAM controller completes each CAS BEFORE...

Page 222: ...10 9 8 7 6 5 4 3 2 1 For DDR2 SDRAM Type R X C R C BA2 BA1 BA0 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 128M 8Mx16 12x9 R 11 10 23 12 13 22 21 20 19 18 17 16 15 14 C AP 9 8 7 6 5 4 3 2 1 25...

Page 223: ...0 Size Register 0x0000_000X SDIC_SIZE1 SDIC_BA 0x014 R W SDRAM 1 Size Register 0x1000_0000 SDIC_MR SDIC_BA 0x018 R W SDRAM Mode Register 0x0000_0032 SDIC_EMR SDIC_BA 0x01C R W SDRAM Extended Mode Reg...

Page 224: ...e more turn around cycle is inserted between memory read and write access 19 OEDelay Output Enable Delay Half MCLK This bit control the data output enable signal If set high the data output enable wil...

Page 225: ...memory request is stop Otherwise the SDRAM is in IDLE state CKE high 0 Disable auto power down mode 1 Enable auto power down mode Default 15 11 Reserved Reserved 10 8 RDBUFTH The AHB Read SDRAM Read B...

Page 226: ...be enabled the SDRAM controller will pre charge bank after each burst read or write cycle This could make the SDRAM consume less power If set this bit high the state machine will keep on the bank act...

Page 227: ...cur Default 4 SELF_REF Self refresh Command Set this bit high the SDRAM controller will make SDRAM to enter self refresh mode SDRAM controller will not have response to any read write or refresh reque...

Page 228: ...the initialize state SDRAM controller will not accept any SDRAM read or write request The logical state of the internal circuit of the SDRAM is undefined after power on The SDRAM must be initialized...

Page 229: ...e SDRAM controller would never issue auto refresh command to SDRAM automatically However if refresh period counter is enabled the SDRAM controller will issue auto refresh command to SDRAM automaticall...

Page 230: ...the SDRAM could be mapped to address 0x0000_0000 0x1fff_ffff of system memory and shadow address on 0x8000_0000 0x9fff_ffff of system memory The minimum supported SDRAM size is 2M bytes Based on the a...

Page 231: ...e SDRAM type is DDR DDR2 the default size is 16MB 8Mx16 Otherwise the default size is 2MB 1Mx16 Note In register SDIC_SIZE1 this field is reserved 2 0 SIZE of SDRAM Byte 0 0 0 SDRAM disable 0 0 1 2M 0...

Page 232: ...Register Offset R W Description Reset Value SDIC_MR SDIC_BA 0x018 R W SDRAM Mode Register 0x0000_0032 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved...

Page 233: ...d Reserved Reserved Reserved 0 0 1 Reserved Reserved Reserved Reserved 0 1 0 2 2 2 Reserved 0 1 1 3 3 Reserved 3 1 0 0 4 Reserved Reserved 4 1 0 1 Reserved Reserved Reserved 5 Inhibit 1 1 0 Reserved 2...

Page 234: ...rnal SDRAM device SDRAM controller only supports the burst length 4 Setting burst length to be other value is inhibited Burst Length SDR DDR DDR2 0 0 0 1 Inhibit Reserved Reserved 0 0 1 2 Inhibit 2 In...

Page 235: ...e Register 0x0000_4000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved Configure 7 6 5 4 3 2 1 0 Configure DrvStrength DLLEN Bits Description 31 14 Res...

Page 236: ...command to the SDRAM This Extended Mode Register is only used for DDR2 SDRAM Register Offset R W Description Reset Value SDIC_EMR2 SDIC_BA 0x020 R W SDRAM Extended Mode Register 2 0x0000_8000 31 30 29...

Page 237: ...s only used for DDR2 SDRAM Register Offset R W Description Reset Value SDIC_EMR3 SDIC_BA 0x024 R W SDRAM Extended Mode Register 3 0x0000_C000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 R...

Page 238: ...Internal Write to Read Command Delay This timing defines the minimum delay latency from last write data to next new valid READ command and only takes effect while SDRAM type is DDR or DDR2 tWTR tHCLK...

Page 239: ...mand tRAS tHCLK tRAS 1 HCLK It s the operating clock of SDRAM controller 7 5 tRCD Active to READ or WRITE Delay This timing defines the minimum delay latency from a ACTIVE command to READ or WRITE com...

Page 240: ...r DQS1 generation Register Offset R W Description Reset Value SDIC_DQSODS SDIC_BA 0x030 R W DQS Output Delay Selection Register 0x0000_1010 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Res...

Page 241: ...lay value This delay value is controlled by the following equation DQS1 delay DQS1_ODS 11 8 DelayCLKMUX DelayCLKMUX It s the gate delay of a CLKMUX gate 7 5 Reserved Reserved 4 0 DQS0_ODS DQS0 Output...

Page 242: ...6 Decoder 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQS_ODS 3 0 DQS_ODS 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 3 2 1 0 5 bit Comparator DQS_ODS DQS_OSD_is_16 DQS_ODS_is_0 XOR DRAM_C...

Page 243: ...elay value is controlled by the following equation DQS11_CLKIn delay DQS1_DS1 DelayCLKMUX DelayCLKMUX It s the gate delay of a CLKMUX gate 19 16 DQS1_DS0 DQS1 Input Delay Selection 0 This field contro...

Page 244: ...al DataCLK If SDRAM type is DDR or DDR2 the DataCLK is used to sample the data registered by DQS11_CLKIn DQS10_CLKIn DQS01_CLKIn DQS00_CLKIn Or the DataCLK is used to sample the data outputted by SDRA...

Page 245: ...18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DALATDLY Resrved DALATDS Bits Description 31 8 Reserved Reserved 7 DALATDLY Data Latch Delay 1 MCLK Enable 0 Data latch delay 1 MCLK Di...

Page 246: ...PROM in this chip and it can be programmed 15 times User can program 256 bit key and 8 bit user defined fields each time The 256 bit key is program only and only can be used by IP Security Engine User...

Page 247: ...al Publication Release Date Dec 15 2015 247 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 6 3 Block Diagram MTP Control Logics APB_BIU_REGS APB BUS MTP Macro Cryptographic Accelerator Figure 5 6...

Page 248: ...ATA PENABLE DFT_mode MTP APB interface signals MISC interface signals MTP macro interface signals MTP_PDOB MTP_PA MPT_PTM MTP_PDIN MTP_PWE MTP_PPROG POR MTP_PRD 256 bits MTP KEY output MTP_KEY Figure...

Page 249: ...249 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 6 5 Functional Description MTP provide the software control MTP macro and provide Key to the Cryptographic Accelerator User can follow the recom...

Page 250: ...not 0 Program MTP Enable MTP refer to the Enable MTP flow Write 0x2 to MTP_CTL Write 0x60AE to MTP_PCYCLE if PCLK 75Mhz MTP_PCYCLE 24750 Write the 256 bits key to MTP_KEY0 MTP_KEY7 Write 8 bits user...

Page 251: ...000_0000 MTP_KEY2 MTP_BA 0x018 W MTP KEY Value 2 Register 0x0000_0000 MTP_KEY3 MTP_BA 0x01c W MTP KEY Value 3 Register 0x0000_0000 MTP_KEY4 MTP_BA 0x020 W MTP KEY Value 4 Register 0x0000_0000 MTP_KEY5...

Page 252: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 252 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 6 8 Register Description...

Page 253: ...Register Offset R W Description Reset Value MTP_KEYEN MTP_BA 0x000 R W MTP Key Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Rese...

Page 254: ...MTP_USERDATA MTP_BA 0x00c R W MTP User Defined Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 UDAT Bits Des...

Page 255: ...EY Value 1 Register 0x0000_0000 MTP_KEY2 MTP_BA 0x018 W MTP KEY Value 2 Register 0x0000_0000 MTP_KEY3 MTP_BA 0x01c W MTP KEY Value 3 Register 0x0000_0000 MTP_KEY4 MTP_BA 0x020 W MTP KEY Value 4 Regist...

Page 256: ...0x030 R W MTP Program Cycle Control Register 0x0000_60AE 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 PCYCLE 7 6 5 4 3 2 1 0 PCYCLE Bits Description 31 16 Re...

Page 257: ...r Offset R W Description Reset Value MTP_CTL MTP_BA 0x034 R W MTP Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4...

Page 258: ...ription Reset Value MTP_PSTART MTP_BA 0x038 R W MTP Program Start Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0...

Page 259: ...ed 24 BUSY MTP Busy Status 0 MTP engine is idle 1 MTP engine is busy 19 16 PRGCNT MTP Program Counts This register show the program times of MTP after read MTP Maximum program count is 15 15 5 Reserve...

Page 260: ...L 7 1 REGLCTL 0 REGPRTDIS Bits Description 31 8 Reserved Reserved 7 0 REGLCTL Register Write protection Code Write Only Some registers have write protection function Writing these registers have to di...

Page 261: ...s bus It supports 8 bit and 16 bit external data bus width for each bank 5 7 2 Features Support SRAM and external I O devices Support 8 16 bit data bus width Support 80 and 68 mode interface signals S...

Page 262: ...w how to configure related pins as the EBI function To enable EBI s clock for operation please set EBI CLK_HCLKEN 9 high 5 7 5 Functional Description EBI Memory Space 5 7 5 1 In this chip two system m...

Page 263: ...BA 0x000 R W EBI Control Register 0x0001_0001 EBI_BNKCTL0 EBI_BA 0x018 R W External Bus Bank 0 Control Register 0x0000_0000 EBI_BNKCTL1 EBI_BA 0x01C R W External Bus Bank 1 Control Register 0x0000_000...

Page 264: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 264 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 7 7 Register Description...

Page 265: ...d WAITVT LITTLE Bits Description 31 29 Reserved Reserved 28 EXBE4 External Bus Bank 4 Byte Enable This bit and M68E4 EBI_CTL 23 defines how the pins EBI_nBE1 EBI_nBE0 and EBI_nWE are used when externa...

Page 266: ...sed when external bus bank 2 accessed Please refer to the table shown below for detail information EXBE2 M68E2 Description 0 0 80 type interface Pin EBI_nBE1 and EBI_nBE0 used as byte write strobe sig...

Page 267: ...how the pins EBI_nBE1 EBI_nBE0 and EBI_nWE are used when external bus bank 3 accessed Please refer to the description of EXBE3 EBI_CTL 27 for detail information 21 M68E2 External Bus Bank 2 M68 Mode E...

Page 268: ...0000 EBI_BNKCTL 4 EBI_BA 0x028 R W External Bus Bank 4 Control Register 0x0000_0000 31 30 29 28 27 26 25 24 BASADDR 23 22 21 20 19 18 17 16 BASADDR SIZE 15 14 13 12 11 10 9 8 ADRS tACC tCOH 7 6 5 4 3...

Page 269: ...MCLK 010 Chip Selection Hold On Time on nOE or nWBE is 2 MCLK 011 Chip Selection Hold On Time on nOE or nWBE is 3 MCLK 100 Chip Selection Hold On Time on nOE or nWBE is 4 MCLK 101 Chip Selection Hold...

Page 270: ...Reference Manual Publication Release Date Dec 15 2015 270 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 1 0 DBWD Programmable Data Bus Width for External I O Bank 0 4 00 Disable bus 01 8 bit 10 16...

Page 271: ...hnical Reference Manual Publication Release Date Dec 15 2015 271 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Figure 5 7 2 External I O Write operation timing Figure 5 7 3 External I O Read operat...

Page 272: ...y user to meet various system configurations and design requirements After reset all 148 I O pins are configured in General Purpose I O Input mode When any of the 148 I O pins used as a General Purpos...

Page 273: ...register SYS_GPA_MFPL SYS_GPA_MFPH SYS_GPB_MFPL SYS_GPB_MFPH SYS_GPC_MFPL SYS_GPC_MFPH SYS_GPD_MFPL SYS_GPD_MFPH SYS_GPE_MFPL SYS_GPE_MFPH SYS_GPF_MFPL SYS_GPF_MFPH SYS_GPG_MFPL SYS_GPG_MFPH SYS_GPH_...

Page 274: ...rt A Interrupt Mode Register 0x0000_0000 GPIOA_IREN GPIO_BA 0x010 R W GPIO Port A Interrupt Rising Edge or Level High Enable Register 0x0000_0000 GPIOA_IFEN GPIO_BA 0x014 R W GPIO Port A Interrupt Fal...

Page 275: ...0 GPIOC_ICEN GPIO_BA 0x0A8 R W GPIO Port C CMOS Input Enable Register 0x0000_EFFF GPIOC_ISEN GPIO_BA 0x0AC R W GPIO Port C Schmitt Trigger Input Enable Register 0x0000_0000 GPIOD_DIR GPIO_BA 0x0C0 R W...

Page 276: ...Port F Interrupt Falling Edge or Level Low Enable Register 0x0000_0000 GPIOF_ISR GPIO_BA 0x158 R W GPIO Port F Interrupt Status Register 0x0000_0000 GPIOF_DBEN GPIO_BA 0x15C R W GPIO Port F De bounce...

Page 277: ...Control Register 0x0000_0000 GPIOI_DATAOUT GPIO_BA 0x204 R W GPIO Port I Data Output Register 0x0000_0000 GPIOI_DATAIN GPIO_BA 0x208 R GPIO Port I Data Input Register 0x0000_xxxx GPIOI_IMD GPIO_BA 0x2...

Page 278: ...00 GPIOJ_PUEN GPIO_BA 0x260 R W GPIO Port J Pull Up Enable Register 0x0000_0000 GPIOJ_PDEN GPIO_BA 0x264 R W GPIO Port J Pull Down Enable Register 0x0000_0000 GPIOJ_ICEN GPIO_BA 0x268 R W GPIO Port J...

Page 279: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 279 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 8 7 Register Description...

Page 280: ..._0000 GPIOF_DIR GPIO_BA 0x140 R W GPIO Port F Direction Control Register 0x0000_0000 GPIOG_DIR GPIO_BA 0x180 R W GPIO Port G Direction Control Register 0x0000_0000 GPIOH_DIR GPIO_BA 0x1C0 R W GPIO Por...

Page 281: ...BA 0x144 R W GPIO Port F Data Output Register 0x0000_0000 GPIOG_DATAOUT GPIO_BA 0x184 R W GPIO Port G Data Output Register 0x0000_0000 GPIOH_DATAOUT GPIO_BA 0x1C4 R W GPIO Port H Data Output Register...

Page 282: ...ata Input Register 0x0000_xxxx GPIOI_DATAIN GPIO_BA 0x208 R GPIO Port I Data Input Register 0x0000_xxxx GPIOJ_DATAIN GPIO_BA 0x248 R GPIO Port J Data Input Register 0x0000_00xx 31 30 29 28 27 26 25 24...

Page 283: ...W GPIO Port F Interrupt Mode Register 0x0000_0000 GPIOG_IMD GPIO_BA 0x18C R W GPIO Port G Interrupt Mode Register 0x0000_0000 GPIOH_IMD GPIO_BA 0x1CC R W GPIO Port H Interrupt Mode Register 0x0000_000...

Page 284: ...Level High Enable Register 0x0000_0000 GPIOE_IREN GPIO_BA 0x110 R W GPIO Port E Interrupt Rising Edge or Level High Enable Register 0x0000_0000 GPIOF_IREN GPIO_BA 0x150 R W GPIO Port F Interrupt Risi...

Page 285: ...ng edge or level high detection of a General Purpose I O When this bit is high and corresponding bit of GPIOx_IMD is low rising edge detection enabled When this bit is high and corresponding bit of GP...

Page 286: ...r Level Low Enable Register 0x0000_0000 GPIOE_IFEN GPIO_BA 0x114 R W GPIO Port E Interrupt Falling Edge or Level Low Enable Register 0x0000_0000 GPIOF_IFEN GPIO_BA 0x154 R W GPIO Port F Interrupt Fall...

Page 287: ...ing edge or level low detection of a General Purpose I O When this bit is high and corresponding bit of GPIOx_IMD is low falling edge detection enabled When this bit is high and corresponding bit of G...

Page 288: ...0x158 R W GPIO Port F Interrupt Status Register 0x0000_0000 GPIOG_ISR GPIO_BA 0x198 R W GPIO Port G Interrupt Status Register 0x0000_0000 GPIOH_ISR GPIO_BA 0x1D8 R W GPIO Port H Interrupt Status Regis...

Page 289: ...F_DBEN GPIO_BA 0x15C R W GPIO Port F De bounce Enable Register 0x0000_0000 GPIOG_DBEN GPIO_BA 0x19C R W GPIO Port G De bounce Enable Register 0x0000_0000 GPIOH_DBEN GPIO_BA 0x1DC R W GPIO Port H De bo...

Page 290: ...Register 0x0000_0000 GPIOG_PUEN GPIO_BA 0x1A0 R W GPIO Port G Pull Up Enable Register 0x0000_0000 GPIOH_PUEN GPIO_BA 0x1E0 R W GPIO Port H Pull Up Enable Register 0x0000_0000 GPIOI_PUEN GPIO_BA 0x220...

Page 291: ...Register 0x0000_0000 GPIOG_PDEN GPIO_BA 0x1A4 R W GPIO Port G Pull Down Enable Register 0x0000_0000 GPIOH_PDEN GPIO_BA 0x1E4 R W GPIO Port H Pull Down Enable Register 0x0000_0000 GPIOI_PDEN GPIO_BA 0x...

Page 292: ...ble Register 0x0000_FFFF GPIOG_ICEN GPIO_BA 0x1A8 R W GPIO Port G CMOS Input Enable Register 0x0000_FFFF GPIOH_ICEN GPIO_BA 0x1E8 R W GPIO Port H CMOS Input Enable Register 0x0000_FFFF GPIOI_ICEN GPIO...

Page 293: ...mitt Trigger Input Enable Register 0x0000_0000 GPIOE_ISEN GPIO_BA 0x12C R W GPIO Port E Schmitt Trigger Input Enable Register 0x0000_0000 GPIOF_ISEN GPIO_BA 0x16C R W GPIO Port F Schmitt Trigger Input...

Page 294: ...This fields controls the Schmitt trigger input buffer enable of the pin that can be configured as a General Purpose I O This control bit always takes effect no matter the pin configured as a General...

Page 295: ...Reserved Reserved 5 ICLK_ON Interrupt Clock on Mode This bit controls the interrupt detection clock enable of the pin that can be configured as a General Purpose I O When this bit is high interrupt d...

Page 296: ...upt input once per 16 clocks 0101 Sample interrupt input once per 32 clocks 0110 Sample interrupt input once per 64 clocks 0111 Sample interrupt input once per 128 clocks 1000 Sample interrupt input o...

Page 297: ...terrupt Status This bit indicates if the GPIO interrupt triggered by pin of GPIO port J 0 GPIO port J did not trigger GPIO interrupt 1 GPIO port J trigger GPIO interrupt 8 GPIOIINT GPIO Port I Interru...

Page 298: ...Status This bit indicates if the GPIO interrupt triggered by pin of GPIO port D 0 GPIO port D did not trigger GPIO interrupt 1 GPIO port D trigger GPIO interrupt 2 GPIOCINT GPIO Port C Interrupt Statu...

Page 299: ...n stopped The CPU can recognize the completion of a GDMA operation by software polling or when it receives an internal GDMA interrupt The GDMA controller can increment source or destination address de...

Page 300: ...ngle operation The GDMA transfer is completed when the current transfer count register reaches zero Descriptor Mode 5 9 5 4 The descriptor fetch function works when RUN GDMA_DADRx 3 is set and NON_DSP...

Page 301: ...xt Descriptor Address 0 Source Address 0 Destination Address 0 Command Information 0 Next Descriptor Address 1 Source Address 1 Destination Address 1 Command Information 1 Next Descriptor Address 2 So...

Page 302: ...ription The Allocation of Command Information in Descriptor List 4 GDMA will depend on the information to request a bus ownership and start the data transfer when GDMA has gotten a bus grant from the...

Page 303: ...Fetch Function 5 9 5 9 The non descriptor fetch function will take place when current GDMA_DADRx NON_DSPTRMODE is set and the GDMA_DADRx register will have no any intention for the GDMA controller The...

Page 304: ...nel 1 Source Base Address Register 0x0000_0000 GDMA_DSTBA1 GDMA_BA 0x028 R W Channel 1 Destination Base Address Register 0x0000_0000 GDMA_TCNT1 GDMA_BA 0x02C R W Channel 1 Transfer Count Register 0x00...

Page 305: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 305 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 9 7 Register Description...

Page 306: ...BNDERR DABNDERR and GDMAERR can be read at descriptor fetch mode Regardless of GDMA operate in descriptor mode or non descriptor mode when transfer width is 16 bit half word and the address with decre...

Page 307: ...ter bits just can be read only 20 Reserved Reserved 19 AUTOIEN Auto Initialization Enable 0 Disables auto initialization 1 Enables auto initialization the GDMA_CSRC0 1 GDMA_CDST0 1 and GDMA_CTCNT0 1 r...

Page 308: ...data were transferred from multiple sources to a single destination 5 DADIR Source Address Direction 0 Source address is incremented successively 1 Source address is decremented successively 4 DADIR D...

Page 309: ...the bus during the period of transfer 16 SOFTREQ Software Triggered GDMA Request Software can request the GDMA transfer service by setting this bit to 1 This bit is automatically cleared by hardware...

Page 310: ...ination address is decremented successively 3 2 GDMAMS GDMA Mode Select 00 Software mode Memory to Memory 01 Reserved 10 Reserved 11 Reserved 1 BME Burst Mode Enable 0 Disables the 8 data burst mode 1...

Page 311: ...GDMA_SRCBA0 GDMA_BA 0x004 R W Channel 0 Source Base Address Register 0x0000_0000 GDMA_SRCBA1 GDMA_BA 0x024 R W Channel 1 Source Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 BADDR 23 22 21...

Page 312: ...00_0000 GDMA_DSTBA1 GDMA_BA 0x028 R W Channel 1 Destination Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 BADDR 23 22 21 20 19 18 17 16 BADDR 15 14 13 12 11 10 9 8 BADDR 7 6 5 4 3 2 1 0 BA...

Page 313: ...DMA_BA 0x02C R W Channel 1 Transfer Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 COUNT 15 14 13 12 11 10 9 8 COUNT 7 6 5 4 3 2 1 0 COUNT Bits Description 31 24 R...

Page 314: ...ource Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CADDR 23 22 21 20 19 18 17 16 CADDR 15 14 13 12 11 10 9 8 CADDR 7 6 5 4 3 2 1 0 CADDR Bits Description 31 0 CADDR Current Source Address The...

Page 315: ...Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CADDR 23 22 21 20 19 18 17 16 CADDR 15 14 13 12 11 10 9 8 CADDR 7 6 5 4 3 2 1 0 CADDR Bits Description 31 0 CADDR Current Destination Address The...

Page 316: ...nnel 0 Current Transfer Count Register 0x0000_0000 GDMA_CTCNT1 GDMA_BA 0x038 R Channel 1 Current Transfer Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CCNT 15 14...

Page 317: ...escriptor interrupt is determined by bit 10 of the GDMA_CTLx Register 0 Stops the channel 1 Starts the channel Note must co operate to NON_DSPTRMODE to start the channel with Descriptor fetch function...

Page 318: ...rom the current GDMA_DADRx Descriptor Address register GDMA_DADRx ORDEN is relevant only for descriptor fetch function GDMA_DADRx NON_DSPTRMODE 0 0 Disable descriptor ordering Fetch the next descripto...

Page 319: ...0x08C R GDMA Internal Buffer Word 3 Register 0x0000_0000 GDMA_BUFFER4 GDMA_BA 0x090 R GDMA Internal Buffer Word 4 Register 0x0000_0000 GDMA_BUFFER5 GDMA_BA 0x094 R GDMA Internal Buffer Word 5 Register...

Page 320: ...Buffer Read Select 00 Read Internal Buffer for Channel 0 01 Read Internal Buffer for Channel 1 10 RESERVED 11 RESERVED 15 12 Reserved Reserved 11 TERR1F Channel 1 Transfer Error O No error occurs 1 H...

Page 321: ...c 1 TC0 is the GDMA interrupt flag TC0 or GDMATERR0 will generate interrupt 7 4 Reserved Reserved 3 TEER1EN Channel 1 Interrupt Enable for Transfer Error 0 Disable Interrupt 1 Enable Interrupt 2 TC1EN...

Page 322: ...programmable counting period The timer can generate an interrupt signal upon timeout or provide the current value of count during operation 5 10 2 Features Independent Clock Source for each Timer cha...

Page 323: ...to enable clock of each Timer 5 10 5 Functional Description Timer controller provides One shot Periodic and Continuous operation modes Each operating function mode is shown as follows One Shot Mode 5...

Page 324: ...nterrupt flag TIF TMRx_ISR 0 is cleared by software once the timer counter value TDR TMRx_DR 23 0 reaches timer compare register TCMP TMRx_CMPR 23 0 value again TIF TMRx_ISR 0 will set to 1 also That...

Page 325: ...ister 1 0x0000_0005 TMR1_CMPR TMR1_BA 0x004 R W Timer Compare Register 1 0x0000_0000 TMR1_DR TMR1_BA 0x008 R Timer Data Register 1 0x0000_0000 TMR2_CSR TMR2_BA 0x000 R W Timer Control and Status Regis...

Page 326: ...21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 PRESCALE Bits Description 31 Reserved Reserved 30 CE Counter Enable 0 Stops counting 1 Starts counting 29 IE Interrupt Enable...

Page 327: ...rdware automatically 25 CACT Timer Is in Active This bit indicates the counter status of timer 0 Timer is not active 1 Timer is in active 24 8 Reserved Reserved 7 0 PRESCALE Clock Pre scale Divide Cou...

Page 328: ...are Register 4 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 TCMP 23 16 15 14 13 12 11 10 9 8 TCMP 15 8 7 6 5 4 3 2 1 0 TCMP 7 0 Bits Description 30 24 Reserved Reserved 23 0 TC...

Page 329: ...1_BA 0x008 R Timer Data Register 1 0x0000_0000 TMR2_DR TMR2_BA 0x008 R Timer Data Register 2 0x0000_0000 TMR3_DR TMR3_BA 0x008 R Timer Data Register 3 0x0000_0000 TMR4_DR TMR4_BA 0x008 R Timer Data Re...

Page 330: ...0 It indicates that the timer 3 does not count up to TCMP TMR3_CMPR 23 0 value yet Software can reset this bit after the timer interrupt 3 had occurred 1 It indicates that the counter of timer 3 is i...

Page 331: ...upt Flag 0 0 It indicates that the timer 0 does not count up to TCMP TMR0_CMPR 23 0 value yet Software can reset this bit after the timer interrupt 0 had occurred 1 It indicates that the counter of ti...

Page 332: ...24 bit up counter is readable through TDR Timer Data Register Supports One shot Periodic Output Toggle and Continuous Counting Operation mode Supports external pin capture for interval measurement Sup...

Page 333: ...ating function mode is shown as follows One Shot Mode 5 11 5 1 If the timer is operated in One shot mode MODE_SEL 1 0 is 00 and ETMR_EN ETMRn_CTL 0 timer counter enable bit is set to 1 the timer count...

Page 334: ...pt enable bit is set to 1 then the interrupt signal is generated and sent to AIC to inform CPU for indicating that the timer counting overflow happens If ETMR_IE ETMRn_IER 0 timer interrupt enable bit...

Page 335: ...om 224 1 to 0 TMRx_DR 100 TMRx_DR 200 TMRx_DR 300 TMRx_DR 400 TMRx_DR 500 TMRx_DR 224 1 TMRx_DR 200 and TMR_IS 1 Clear TMR_IS as 0 and Set TMRx_CMPR 500 TMRx_DR 500 and TMR_IS 1 Clear TMR_IS as 0 and...

Page 336: ...ssary and recommended 5 11 6 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value ETMR Base Address ETMR0_BA 0x4001_0000 ETMR1_BA 0x4001_0100 ETMR2...

Page 337: ...recommended to save power consumption 21 Reserved Reserved 20 CAP_CNT_MOD Timer Capture Counting Mode Selection This bit indicates the behavior of 24 bit up counting timer while TCAP_EN is set to high...

Page 338: ...timer to start counting while 2nd rising edge triggers 24 bit timer to stop counting 10 Falling edge on Tcapture pin triggers 24 bit timer to start counting while rising edge triggers 24 bit timer to...

Page 339: ...n this mode the associated interrupt signal is generated periodically if ETMR_IER ETMR_IE is enabled while the value of 24 bit up counter equals the ETMRn_CMPR After that the 24 bit counter will be re...

Page 340: ...1 Reset Timer s pre scale counter internal 24 bit up counter and ETMR_CTL ETMR_EN bit Note This bit will be auto cleared and takes at least 3 ECLKetmr clock cycles 0 ETMR_EN Timer Counter Enable Bit 0...

Page 341: ...alue ETMRn_PRE CNT n 0 1 2 3 ETMRn_BA 0x004 R W Enhance Timer n Pre Scale Counter Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved...

Page 342: ...Reserved 23 0 ETMR_CMP Timer Compared Value ETMR_CMP is a 24 bit compared register When the internal 24 bit up counter counts and its value is equal to ETMR_CMP value a Timer Interrupt is requested if...

Page 343: ...4 3 2 1 0 Reserved TCAP_IE ETMR_IE Bits Description 31 2 Reserved Reserved 1 TCAP_IE Timer Capture Function Interrupt Enable 0 Timer External Pin Function Interrupt Disabled 1 Timer External Pin Funct...

Page 344: ...detect before CPU clearing TCAP_IS status 1 New incoming capture event detected before CPU clearing TCAP_IS status 4 ETMR_WAKE_ST S Timer Wake up Status If timer causes CPU wakes up from power down m...

Page 345: ...ister Offset R W Description Reset Value ETMRn_DR n 0 1 2 3 ETMRn_BA 0x014 R Enhance Timer n Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 TDR 15 14 13 12 11 10 9...

Page 346: ...ance Timer n Capture Data Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CAP 15 14 13 12 11 10 9 8 CAP 7 6 5 4 3 2 1 0 CAP Bits Description 31 24 Reserved Reserved 23 0...

Page 347: ...generator is enabled two outputs of the corresponding PWM channel pair will be replaced by the output of Dead Zone generator The Dead Zone generator is used to control off chip power device To preven...

Page 348: ...e PWM pin functions are configured in PA_H_MFP PB_L_MFP PC_H_MFP PD_H_MFP and PH_L_MFP registers The clock enable of PWM function is configured in PCLKEN1 27 5 12 5 Functional Description PWM Timer Op...

Page 349: ...If CH0MOD PWM_CTL 3 is set to one periodic mode the controller loads CNR PWM_CNR 15 0 to PWM counter when PWM counter reaches zero If CNR PWM_CNR 15 0 is set to zero PWM counter will be halt when PWM...

Page 350: ...ime gap called Dead Zone to delay PWM rising output and it is in order to prevent damage for the power switch devices that connected to the PWM output pins User can program Dead Zone counter to determ...

Page 351: ..._CNR 15 0 for setting PWM period and duty length Enable PWM down counter start running Set CH0EN 1 PWM_PCR 0 The procedure mentioned above may be set up not in the order and PWM Timer can still work f...

Page 352: ...0 0x0000_0000 PWM0_PDR PWM_BA 0x014 R PWM Data Register 0 0x0000_0000 PWM1_CNR PWM_BA 0x018 R W PWM Counter Register 1 0x0000_0000 PWM1_CMR PWM_BA 0x01C R W PWM Comparator Register 1 0x0000_0000 PWM1_...

Page 353: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 353 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 12 7 Register Description...

Page 354: ...Register 1 These 8 bits determine the dead zone length of channel 2 3 pair The unit time of dead zone length is received from clock selector 1 23 16 DZL01 Dead Zone Length Register 0 These 8 bits dete...

Page 355: ...14 12 CLKSEL3 Channel 3 Clock Source Selection Select PWM clock source for PWM timer channel 3 000 Prescale output divided by 2 001 Prescale output divided by 4 010 Prescale output divided by 8 011 P...

Page 356: ...nnel 3 Inverter Switch 0 Inverter OFF The output polarity of PWM channel 3 will be kept as usual 1 Inverter ON The output polarity of PWM channel 3 will be inverted 17 Reserved Reserved 16 CH3EN Chann...

Page 357: ...0 Disable the Dead Zone output of PWM channel 2 3 1 Enable the Dead Zone output of PWM channel 2 3 4 DZEN01 Dead zone Generator 0 Enable Disable 0 Disable the Dead Zone output of PWM channel 0 1 1 En...

Page 358: ...0x0000_0000 PWM2_CNR PWM_BA 0x024 R W PWM Counter Register 2 0x0000_0000 PWM3_CNR PWM_BA 0x030 R W PWM Counter Register 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved...

Page 359: ...1 0x0000_0000 PWM2_CMR PWM_BA 0x028 R W PWM Comparator Register 2 0x0000_0000 PWM3_CMR PWM_BA 0x034 R W PWM Comparator Register 3 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16...

Page 360: ...Register 0 0x0000_0000 PWM1_PDR PWM_BA 0x020 R PWM Data Register 1 0x0000_0000 PWM2_PDR PWM_BA 0x02C R PWM Data Register 2 0x0000_0000 PWM3_PDR PWM_BA 0x038 R PWM Data Register 3 0x0000_0000 31 30 29...

Page 361: ...R1 PIER0 Bits Description 31 4 Reserved Reserved 3 PIER3 PWM Timer Channel 3 Interrupt Enable 0 Disable the PWM interrupt function of channel 3 1 Enable the PWM interrupt function of channel 3 2 PIER2...

Page 362: ...served 3 PIIR3 PWM Timer Channel 3 Interrupt Flag This flag is set by hardware when PWM3 down counter reaches zero software can clear this bit by writing a one into this bit 2 PIIR2 PWM Timer Channel...

Page 363: ...orts to force WDT enabled after chip powered on or reset by setting WDTON in PWRON register Supports WDT time out wake up function only if WDT clock source is selected as 32 kHz 5 13 3 Block Diagram 1...

Page 364: ...the TOUTSEL WDTCR 10 8 settings WDT time out interrupt will occur then WDT time out interrupt flag IF WDT_CTL 3 will be set to 1 immediately WDT Reset Delay Period and Reset System 5 13 5 2 There is...

Page 365: ...dog Reset Period TRST 00 5 3 us 01 682 us 10 87 3 ms 11 1 95 ms Table 5 13 2 Watchdog Reset Period Selection TTIS WDT reset low reset TRSTD TRST TWDT TWDT Watchdog Clock Time Period TTIS Watchdog Time...

Page 366: ...led Notice that user should set XTAL_EN CLK_PMCON 0 to enable crystal clock source before system entries power down mode because the system peripheral clock are disabled when system is power down mode...

Page 367: ...NICAL REFERENCE MANUAL 5 13 6 Register Map R read only W write only R W both read and write Register Offset R W Description Reset Value WDT Base Address WDT_BA 0xB800_1800 WDT_CTL WDT_BA 0x00 R W WDT...

Page 368: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 368 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 13 7 Register Description...

Page 369: ...edgement affects WDT counting WDT up counter will be held while CPU is held by ICE 1 ICE debug mode acknowledgement Disabled WDT up counter will keep going no matter CPU is held by ICE or not Note Thi...

Page 370: ...p by WDT time out interrupt signal generated only if WDT clock source is selected to 32 kHz oscillator 3 IF WDT Time out Interrupt Flag This bit will set to 1 while WDT up counter value reaches the se...

Page 371: ...ription 31 2 Reserved Reserved 1 0 RSTDSEL WDT Reset Delay Selection Write Protect When WDT time out happened user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT WDT_CT...

Page 372: ...Supports 4 bit value PSCSEL to programmable maximum 11 bit prescale counter period of WWDT counter 5 14 3 Block Diagram 6 bit down counter 11 bit Prescale 6 bit compare value CMPDAT WWDT_CLK 0x3F Wri...

Page 373: ...WWDT_CLK 32 KHz 0000 1 1 64 TWWDT 2 ms 0001 2 2 64 TWWDT 4 ms 0010 4 4 64 TWWDT 8 ms 0011 8 8 64 TWWDT 16 ms 0100 16 16 64 TWWDT 32 ms 0101 32 32 64 TWWDT 64 ms 0110 64 64 64 TWWDT 128 ms 0111 128 128...

Page 374: ...terrupt 5 14 5 2 During down counting by the WWDT counter the WWDTIF WWDT_STATUS 0 is set to 1 while the WWDT counter value CNTDAT is equal to window compare value CMPDAT and WWDTIF can be cleared by...

Page 375: ...o 0 and generate WWDT reset system signal to info system reset If current CNTDAT WWDT_CNT 5 0 is larger than CMPDAT WWDT_CTL 21 16 and user writes 0x00005AA5 to the WWDT_RLDCNT register the WWDT reset...

Page 376: ...d command to actually perform reload action Notice that if user set PSCSEL WWDT_CTL 11 8 to 0000 the counter prescale value should be as 1 and the CMPDAT WWDT_CTL 21 16 must be larger than 2 Otherwise...

Page 377: ...nly R W both read and write Register Offset R W Description Reset Value WWDT Base Address WWDT_BA 0xB800_1900 WWDT_RLDC NT WWDT_BA 0x00 W WWDT Reload Counter Register 0x0000_0000 WWDT_CTL WWDT_BA 0x04...

Page 378: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 378 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 14 7 Register Description...

Page 379: ...3 22 21 20 19 18 17 16 WWDT_RLDCNT 23 16 15 14 13 12 11 10 9 8 WWDT_RLDCNT 15 8 7 6 5 4 3 2 1 0 WWDT_RLDCNT 7 0 Bits Description 31 0 WWDT_RLDCNT WWDT Reload Counter Register Writing 0x00005AA5 to thi...

Page 380: ...WDT Window Compare Register Set this register to adjust the valid reload window Note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and...

Page 381: ...cale is 1536 Max time out period is 1536 64 TWWDT 1111 Pre scale is 2048 Max time out period is 2048 64 TWWDT 7 2 Reserved Reserved 1 INTEN WWDT Interrupt Enable Control Bit If this bit is enabled the...

Page 382: ...Reserved 7 6 5 4 3 2 1 0 Reserved WWDTRF WWDTIF Bits Description 31 2 Reserved Reserved 1 WWDTRF WWDT Timer out Reset Flag This bit indicates the system has been reset by WWDT time out reset or not 0...

Page 383: ...fset R W Description Reset Value WWDT_CNT WWDT_BA 0x0C R WWDT Counter Value Register 0x0000_003F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5...

Page 384: ...al to alarm time and calendar settings in RTC_TALM and RTC_CALM the ALMIF RTC_INTSTS 0 RTC Alarm Interrupt Flag is set to 1 and the RTC alarm interrupt signal is generated if the ALMIEN RTC_INTEN 0 Al...

Page 385: ...clock for RTC control register access By setting MFP_GPH4 SYS_MFP_GPHL 19 16 and MFP_GPI3 SYS_MFP_GPIL 15 12 properly RTC will output tick signal to pin PH 4 or PI 4 Please refer to register SYS_MFP_...

Page 386: ...5 6 Count from Sunday to Saturday Tick Time interrupt 5 15 5 7 RTC block use a counter to calibrate the tick time count value When the value in counter reaches zero RTC will issue an interrupt RTC re...

Page 387: ...0000 RTC_INTSTS RTC_BA 0x02C R W RTC Interrupt Status Register 0x0000_0000 RTC_TICK RTC_BA 0x030 R W RTC Time Tick Register 0x0000_0000 RTC_PWRCTL RTC_BA 0x034 R W RTC Power Control Register 0x0000_70...

Page 388: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 388 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL RTC_SPR15 RTC_BA 0x07C R W RTC Spare Register 15 0x0000_0000...

Page 389: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 389 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 15 7 Register Description...

Page 390: ...20 19 18 17 16 INIT 15 14 13 12 11 10 9 8 INIT 7 6 5 4 3 2 1 0 INIT INIT Active Bits Description 31 1 INIT RTC Initiation After RTC block is powered on RTC is at reset state User has to write a numbe...

Page 391: ...18 17 16 Reserved RWENF 15 14 13 12 11 10 9 8 RWENPASSWD 7 6 5 4 3 2 1 0 RWENPASSWD Bits Description 31 17 Reserved Reserved 16 RWENF RTC Register Access Enable Flag Read Only 0 RTC register read writ...

Page 392: ...art Integer part of detected value RTC_FREQADJ 11 8 Integer part of detected value RTC_FREQADJ 11 8 32776 1111 32768 0111 32775 1110 32767 0110 32774 1101 32766 0101 32773 1100 32765 0100 32772 1011 3...

Page 393: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 393 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Fraction part 0 27 X 60 16 2 0x10 RTC_FREQADJ 5 0 0x10...

Page 394: ...23 22 21 20 19 18 17 16 Reserved TENHOUR HOUR 15 14 13 12 11 10 9 8 Reserved TENMINUTE MINUTE 7 6 5 4 3 2 1 0 Reserved TENSECOND SECOND Bits Description 31 22 Reserved Reserved 21 20 TENHOUR 10 Hour...

Page 395: ...d 23 22 21 20 19 18 17 16 TENYEAR YEAR 15 14 13 12 11 10 9 8 Reserved TENMONTH MONTH 7 6 5 4 3 2 1 0 Reserved TENDAY DAY Bits Description 31 24 Reserved Reserved 23 20 TENYEAR 10 Year Calendar Digit 0...

Page 396: ...3 2 1 0 Reserved 24HEN Bits Description 31 1 Reserved Reserved 0 24HEN 24 hour 12 hour Mode Selection It indicate that TLR and TAR are in 24 hour mode or 12 hour mode 0 12 hour time format with am an...

Page 397: ...ription Reset Value RTC_WEEKDAY RTC_BA 0x018 R W RTC Day of the Week Register 0x0000_0006 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1...

Page 398: ...OUR RTC_TALM 19 16 could trigger RTC time alarm 1 TENHOUR RTC_TALM 21 20 and HOUR RTC_TALM 19 16 couldn t trigger RTC time alarm 29 MINALM_MSK Minute Alarm Mask This bit control if TENMINUTE RTC_TALM...

Page 399: ...70 TECHNICAL REFERENCE MANUAL 11 8 MINUTE 1 Min Time Digit 0 9 7 Reserved Reserved 6 4 TENSECOND 10 Sec Time Digit 0 5 3 0 SECOND 1 Sec Time Digit 0 9 Note1 RTC_TALM is a BCD digit counter and RTC wil...

Page 400: ...dn t trigger RTC time alarm 30 YRALM_MSK Year Alarm Mask This bit controls if TENYEAR RTC_CALM 23 20 and YEAR RTC_CALM 19 16 could trigger RTC timer alarm 0 TENYEAR RTC_CALM 23 20 and YEAR RTC_CALM 19...

Page 401: ...day 111 Reserved 23 20 TENYEAR 10 Year Calendar Digit 0 9 19 16 YEAR 1 Year Calendar Digit 0 9 15 13 Reserved Reserved 12 TENMINUTE 10 Month Calendar Digit 0 1 11 8 MINUTE 1 Month Calendar Digit 0 9 7...

Page 402: ...iption Reset Value RTC_LEAPYEAR RTC_BA 0x024 R RTC Leap Year Indicator Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2...

Page 403: ...Reserved 5 KEYPRESIEN Key Press Interrupt Enable 0 Key Press interrupt disable 1 RTC Relative Alarm interrupt enable 4 RELALMIEN Relative Alarm Interrupt Enable 0 RTC Relative Alarm interrupt disable...

Page 404: ...tes the SYS_nWAKEUP keep in low user pressed the key for 1 second when SYS_PWREN is high stage machine is in Power_On state User can write 1 to clear this bit 0 SYS_nWAKEUP pin didn t keep in low for...

Page 405: ...m low to high 1 TICKINT RTC Time Tick Interrupt Indication REGISTER This bit indicates the RTC timer tick value configured in RTC_TICK has reached User can write 1 to clear this bit 0 RTC timer tick v...

Page 406: ...ter 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TTR Bits Description 2 0 TTR RTC Tick Time Interrupt Request I...

Page 407: ...alarm condition 0 Pin SYS_PWREN be forced to low by alarm function Disabled 1 Pin SYS_PWREN be forced to low by alarm function Enabled 27 16 RELALM_TIME Relative Alarm Time This field defines the rel...

Page 408: ...interrupt status to high 0 Alarm function Disabled 1 Alarm function Enabled 2 HW_PCLR_EN Hardware Power Clear Enable 0 H W wouldn t take any active on SYS_PWREN pin 1 H W set SYS_PWREN pin to low auto...

Page 409: ...5 4 3 2 1 0 RELARM_CNT Bits Description 31 21 Reserved Reserved 20 16 PWR_OFF_CNT Power Off Counter Current Value This field shows the current value of power off counter This field is read only and w...

Page 410: ...58 R W RTC Spare Register 6 0x0000_0000 RTC_SPR7 RTC_BA 0x05C R W RTC Spare Register 7 0x0000_0000 RTC_SPR8 RTC_BA 0x060 R W RTC Spare Register 8 0x0000_0000 RTC_SPR9 RTC_BA 0x064 R W RTC Spare Regist...

Page 411: ...d All of the controllers support auto flow control function that uses two low level signals CTS clear to send and RTS request to send to control the flow of data transfer between the UART and external...

Page 412: ...l individually Supports CTS wake up function Supports 8 bit receiver buffer time out detection function Programmable transmitting data delay time between the last stop and the next start bit by settin...

Page 413: ...control block RX shift Register This block is the shifting the receiving data in serially control block Baud Rate Generator Divide the external clock by the divisor to get the desired baud rate clock...

Page 414: ...diagram demonstrates the auto flow control block diagram Refer to Auto Flow Control section for detail description Figure 5 16 2 Auto Flow Control Block Diagram 5 16 4 Basic Configuration Before using...

Page 415: ...Forced Mask Parity 1 0 1 Parity bit always logic 1 Parity bit on the serial byte is set to 1 regardless of total number of 1 s even or odd counts Forced Space Parity 1 1 1 Parity bit always logic 0 P...

Page 416: ...2 A 62 B 8 A 46 B 11 A 34 B 15 0x2800_003E 0x2B00_002E 0x2F00_0022 A 574 0x3000_023E 19200 A 70 0x0000_0046 A 126 B 8 A 94 B 11 A 70 B 15 0x2800_007E 0x2B00_005E 0x2F00_0046 A 1150 0x3000_047E 9600 A...

Page 417: ...cts CTSn is asserted CTSn high from external device If a valid asserted CTSn is not detected the UART controller will not send data out The auto flow function is implemented in High speed UART only Th...

Page 418: ...decoder The IrDA SIR protocol is half duplex only So it cannot transmit and receive data at the same time The IrDA SIR physical layer specifies a minimum 10 ms transfer delay between transmission and...

Page 419: ...late Non Return to Zero NRZ transmit bit stream output from UART The IrDA SIR physical layer specifies use of Return to Zero Inverted RZI modulation scheme which represent logic 0 as an infra light pu...

Page 420: ...ecoder The IrDA SIR Receive Decoder demodulates the return to zero bit stream from the input detector and outputs the NRZ serial bits stream to the UART received data input The decoder input is normal...

Page 421: ...the 9 th bit When the PBE UA_LCR 3 EPE UA_LCR 4 and SPE UA_LCR 5 are set the 9 th bit is transmitted 0 and when PBE and SPE are set and EPE is cleared the 9 th bit is transmitted 1 The Controller sup...

Page 422: ...ed in the RX FIFO If the receiver is be enabled RX_DIS UA_FCR 8 is low all received byte data will be accepted and stored in the RX FIFO and if the receiver is disabled RX_DIS UA_FCR 8 is high all rec...

Page 423: ...AAD mode don t fill any value to RX_DIS UA_CTL 2 bit Program Sequence example 1 Program FUN_SEL UART_FUN_SEL 1 0 to select RS 485 function 2 Program the RS485_AAD UA_ALT_CSR 9 3 When an address byte...

Page 424: ...n control function The RS 485 driver control is implemented using the RTS control signal from an asynchronous serial port to enable the RS 485 driver The RTS line is connected to the RS 485 driver ena...

Page 425: ...s programmed for auto address match value Determine auto direction control by programming RS 485_AUD Figure 5 16 10 RS 485 Frame Structure LIN Local Interconnection Network Mode 5 16 5 8 The UART supp...

Page 426: ...header provided by the master task consists of a break field and sync field followed by a frame identifier frame ID The frame identifier uniquely defines the purpose of the frame The slave task appoin...

Page 427: ...d software must handle the sequence to sending a complete header to bus by filled frame ID data to UA_THR register 3 If the header selected is break field sync field and frame ID field hardware will c...

Page 428: ...dware LIN_IDPEN UA_LIN_CTL 9 1 software fill ID0 ID5 hardware will calculi P0 and P1 Procedure with software error monitoring in Master mode 1 Choose if the hardware transmission header field only inc...

Page 429: ...ection and break flag is shown in the following figure Case 1 break signal not long enough ignore this break signal and LIN_BKDET_F is not set Case 2 break signal long enough break detect and LIN_BKDE...

Page 430: ...state Case 3 break occurring while a data is being received not master sending break state Figure 5 16 13 Relationship between Break Detection and Frame Error Detection IDLE Sync 0x55 PID Data SIN RD...

Page 431: ...er can transmitter response master is the publisher of the response and receive response master is the subscriber of the response When the master is the publisher of the response the master send respo...

Page 432: ...stop bit NSB UA_LCR 2 1 with value one recessive in accordance with the LIN standard In LIN slave mode software may need some initial process and the initialization process flow of LIN slave mode is s...

Page 433: ...r is received the LINS_HDET_F UA_LIN_SR 0 flag will be set If the LIN_RX_BRK_IEN UA_IER 8 1 an interrupt will be generated User can enable frame ID parity check function by setting LIN_IDPEN UA_LIN_CT...

Page 434: ...he subscriber of the response the slave received n data bytes by other slave node the maximum of n is 8 Note When LIN data transmission is active software can monitor the LIN bus transfer state by har...

Page 435: ...out counter If the entire header is not received within the maximum time limit of 57 bit times the header error flag LIN_HERR_F UA_LIN_SR 1 will be set The time out counter is enabled at each break d...

Page 436: ...CTL 23 22 is break field when detect a valid LIN break delimiter the controller will enable the receiver left mute mode and the following data sync data and frame ID data will be stored in RX FIFO Whi...

Page 437: ...n to fix the communication baud rate When operating in without automatic resynchronization mode software needs some initial process and the initialization process flow of without automatic resynchroni...

Page 438: ...tween five falling edges is sampled on engine clock and the result of this measurement is stored in an internal 13 bit register BAUD_LIN and the result will be updated to UA_BAUD register automaticall...

Page 439: ...elease Date Dec 15 2015 439 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Case1 UA_BAUD read write operation when LINS_DUM_EN UA_LIN_CTL 3 0 Case2 UA_BAUD read write operation when LINS_DUM_EN UA_L...

Page 440: ...set If the difference between 15 and 14 the header error flag LINS_HERR_F UA_LIN_SR 1 may either set or not depending on the data dephasing Check2 Based on measurement of time between each falling ed...

Page 441: ...c field measure time out with automatic resynchronization mode LIN header reception time out Interrupt 5 16 5 9 The UART Controller supports seven types of interrupts including 1 LIN function interrup...

Page 442: ...the counting clock baud rate clock whenever the RX FIFO receives a new data word Once the content of time out counter TOUT_CNT is equal to that of time out interrupt comparator TOIC UA_TOR 7 0 a recei...

Page 443: ...0 UARTn_BA 0x000 W UART n Transmit Holding Register Undefined UAn_IER n 0 1 2 3 4 5 6 7 8 9 10 UARTn_BA 0x004 R W UART n Interrupt Enable Register 0x0000_0000 UAn_FCR n 0 1 2 3 4 5 6 7 8 9 10 UARTn_BA...

Page 444: ...ARTn_BA 0x028 R W UART n IrDA Control Register 0x0000_0040 UAn_ALT_CSR n 0 1 2 3 4 5 6 7 8 9 10 UARTn_BA 0x02C R W UART n Alternate Control Status Register 0x0000_000C UAn_FUN_SEL n 0 1 2 3 4 5 6 7 8...

Page 445: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 445 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 16 7 Register Description...

Page 446: ...ption Reset Value UAn_RBR n 0 1 2 3 4 5 6 7 8 9 10 UARTn_BA 0x000 R UART n Receive Buffer Register Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Res...

Page 447: ...ion Reset Value UAn_THR n 0 1 2 3 4 5 6 7 8 9 10 UARTn_BA 0x000 W UART n Transmit Holding Register Undefined 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Res...

Page 448: ...n CTS auto flow is enabled the UART will send data to external device when CTS input assert UART will not send data to device until CTS is asserted 12 AUTO_RTS_EN RTS Auto Flow Control Enable Control...

Page 449: ...RTO_IEN RX Time out Interrupt Enable Control 0 INT_TOUT masked off 1 INT_TOUT Enabled 3 MODEM_IEN Modem Status Interrupt Enable Control 0 INT_MODEM masked off 1 INT_MODEM Enabled 2 RLS_IEN Receive Li...

Page 450: ...14 Trigger Level Bytes 0100 30 14 High speed Normal Speed Trigger Level Bytes 0101 46 14 High speed Normal Speed Trigger Level Bytes 0110 62 14 High speed Normal Speed Trigger Level Bytes others 62 14...

Page 451: ...2 TFR TX Field Software Reset When TFR UA_FCR 2 is set all the byte in the transmit FIFO and TX internal state machine are cleared 0 No effect 1 Reset the TX internal state machine and pointers Note...

Page 452: ...er logic 5 SPE Stick Parity Enable Control 0 Stick parity Disabled 1 If bit 3 and 4 are logic 1 the parity bit is transmitted and checked as logic 0 If bit 3 is 1 and bit 4 is 0 then the parity bit is...

Page 453: ...UC970 Technical Reference Manual Publication Release Date Dec 15 2015 453 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 01 6 bit character length 10 7 bit character length 11 8 bit character length...

Page 454: ...2 3 4 5 6 7 8 9 10 UARTn_BA 0x010 R W UART n Modem Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved RTS_ST Reserved LEV_RTS...

Page 455: ...n RTS_ST MCR 13 UART Mode LEV_RTS MCR 9 0 RS 485 Mode LEV_RTS MCR 9 0 TX Pin RTS_ST MCR 13 TX Pin RTS_ST MCR 13 RS 485 Mode LEV_RTS MCR 9 1 Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Start Bit D0 D1 D2 D3 D4 D...

Page 456: ...9 8 Reserved LEV_CTS 7 6 5 4 3 2 1 0 Reserved CTS_ST Reserved DCTSF Bits Description 31 9 Reserved Reserved 8 LEV_CTS CTS Trigger Level This bit can change the CTS trigger level 0 Low level triggered...

Page 457: ...it is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed 27 25 Reserved Reserved 24 TX_OVER_IF TX Overflow Error Interrupt Flag Read Only 0 TX FIFO is not...

Page 458: ...bits and is reset whenever the CPU writes 1 to this bit Note This bit is read only but it can be cleared by writing 1 to it 5 FEF Framing Error Flag Read Only 0 No any frame data error in stop bit 1 T...

Page 459: ...NUC970 TECHNICAL REFERENCE MANUAL 0 RX FIFO no overflow 1 RX FIFO overflow Note If the number of bytes of received data is greater than RX_FIFO UA_RBR size 64 16 bytes of High Speed UART Low Speed UAR...

Page 460: ...set to 1 0 No LIN RX Break interrupt is generated 1 LIN RX Break interrupt is generated 14 Reserved Reserved 13 BUF_ERR_INT Buffer Error Interrupt Indicator Read Only This bit is set if BUF_ERR_IEN UA...

Page 461: ...enerated Note This bit is cleared when both TX_OVER_IF UA_FSR 24 and RX_OVER_IF UA_FSR 0 are cleared 4 TOUT_IF Time out Interrupt Flag Read Only This bit is set when the RX FIFO is not empty and no ac...

Page 462: ...Receive Data Available Interrupt Flag Read Only When the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set If RDA_IEN UA_IER 0 is enabled the RDA interrupt will be generated...

Page 463: ...2 1 0 TOIC Bits Description 31 16 Reserved Reserved 15 8 DLY TX Delay Time Value This field is use to programming the transfer delay time between the last stop bit and next start bit Note The counter...

Page 464: ...d Reserved 29 DIV_X_EN Divider X Enable Control 0 Divider X Disabled the equation of M 16 1 Divider X Enabled the equation of M X 1 but DIVIDER_X UA_BAUD 27 24 must 8 Refer to the table below for more...

Page 465: ...9 8 Reserved 7 6 5 4 3 2 1 0 TPS INV_RX INV_TX Reserved TX_SELECT Reserved Bits Description 31 7 Reserved Reserved 7 TPS TX Pulse Width 0 IrDA TX output Pulse width is equal to UART s 3 16 bit frame...

Page 466: ...ddress Detection Enable Control This bit is use to enable RS 485 address detection mode 0 address detection mode Disabled 1 Address detection mode Enabled Note This field is used for RS 485 any operat...

Page 467: ...eader Enabled Note When transmitter header field it may be break or break sync or break sync frame ID selected by LIN_HEAD_SEL UA_LIN_CTL 23 22 field transfer operation finished this bit will be clear...

Page 468: ...1 2 3 4 5 6 7 8 9 10 UARTn_BA 0x030 R W UART n Function Select Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Re...

Page 469: ...PEN UA_LIN_CTL 9 1 user fill ID0 ID5 hardware will calculi P0 and P1 otherwise user must filled frame ID and parity in this field Note1 User can fill any 8 bit value to this field and the bit 24 indic...

Page 470: ...he BIT_ERR_F UA_LIN_SR 9 flag will be asserted 11 LIN_RX_DIS If the receiver is be enabled LIN_RX_DIS 0 all received byte data will be accepted and stored in the RX FIFO and if the receiver is disable...

Page 471: ...ception Note1 This bit only valid in LIN slave mode LINS_EN UA_LIN_CTL 0 1 Note2 This bit is used for LIN slave automatic resynchronization mode for non automatic resynchronization mode this bit shoul...

Page 472: ...ed Reserved 9 BIT_ERR_F Bit Error Detect Status Flag Read Only 0 The input pin SIN state is equals to the output pin SOUT state 1 The input pin SIN state not equals to the output pin SOUT state Note1...

Page 473: ...1 LINS_HERR_F LIN Slave Header Error Flag Read Only This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it The header include break delimi...

Page 474: ...bit timers for Answer to Request ATR and waiting times processing Supports auto inverse convention function Supports transmitter and receiver error retry and error number limiting function Supports ha...

Page 475: ...x_N 1 SCx_EN CLK_KEEPx SCx_CLK Clock Controller x SCx_EN CLK_KEEPx 0 PCLKEN1 12 SC0_PINCSR 6 1 PCLKEN1 13 SC1_PINCSR 6 SCx_N CLK_DIV6 27 24 CLK_DIV6 31 28 Figure 5 17 1 SC Clock Control Diagram 4 bit...

Page 476: ...K Output UART Transmit Data Table 5 17 2 UART Pin Description 5 17 5 Functional description Basically the smart card interface acts as a half duplex asynchronous communication port and its data format...

Page 477: ...programming procedure provides user has a simple setting for activation sequence Following is the activation control sequence generated by hardware 1 Set activation timing by setting INITSEL SC_ALTCT...

Page 478: ...TCTL 4 to 1 and the interface will perform the warm reset sequence by hardware The SC_RST to SC_DATA reception mode T4 and SC_DATA reception mode to SC_RST assert T5 can be selected by programming INI...

Page 479: ...PWR by programming PWRSTS SC_PINCTL 18 to 0 The deactivation sequence can be controlled in two ways The procedure is shown as follows Software Timing Control Set SC_PINCTL and SC_TMRCTL0 to process th...

Page 480: ...t to CPU at the same time if INITIEN SC_IER 8 1 Undefined Time Comment 00 01 10 11 97 145 177 177 83 87 131 135 163 167 163 167 Unit SC Clock T9 T7 T8 T7 T8 T9 T7 T8 T9 SC_PWR SC_CLK SC_RST SC_DATA IN...

Page 481: ...gure If the TS pattern is 1100_0000 it is inverse convention When decoded by inverse convention the conveyed byte is equal to 0x3F If the TS pattern is 1101_1100 it is direct convention When decoded b...

Page 482: ...RTY SC_CTL 22 20 The re transmit number is up to TXRTY 1 and if the re transmit number is equal to TXRTY 1 TXOVERR flag will be set by hardware and if TERRIEN SC_INTEN 2 SC controller will generate a...

Page 483: ...ed when counter time out The time out value will be CNT SC_TMRCTL0 23 0 SC_TMRCTL1 7 0 SC_TMRCTL2 7 0 1 Start Start counting when the first START bit reception detected bit after CNTENx SC_ALTCTL 7 5...

Page 484: ...T SC_TMRCTL0 23 0 SC_TMRCTL1 7 0 SC_TMRCTL2 7 0 1 Start Start counting when the first START bit detected after CNTENx SC_ALTCTL 7 5 set to 1 End Stop counting after CNTENx SC_ALTCTL 7 5 set to 0 1000...

Page 485: ...with 12000000 115200 1 5 Select the data format include data length by setting WLS SC_UARTCTL 5 4 parity format by setting OPE SC_UARTCTL 7 and PBOFF SC_UARTCTL 6 and stop bit length by setting NSB S...

Page 486: ...r 0x0000_0000 SC_ETUCTL x 0 1 SCx_BA 0x014 R W SC ETU Control Register 0x0000_0173 SC_INTEN x 0 1 SCx_BA 0x018 R W SC Interrupt Enable Control Register 0x0000_0000 SC_INTSTS x 0 1 SCx_BA 0x01C R W SC...

Page 487: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 487 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL...

Page 488: ...00 R W SC Receiving Transmit Holding Buffer Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DAT Bits Description 3...

Page 489: ...When hardware detects the card detect pin SC_CD from high to low it indicates a card is detected 1 When hardware detects the card detect pin from low to high it indicates a card is detected Note Softw...

Page 490: ...le RXRTYEN first and then fill in new retry value 15 NSB Stop Bit Length This field indicates the length of stop bit 0 The stop bit length is 2 ETU 1 The stop bit length is 1 ETU Note The default stop...

Page 491: ...and the TS is direct convention CONSEL SC_CTL 5 4 will be set to 00 automatically otherwise if the TS is inverse convention and CONSEL SC_CTL 5 4 will be set to 11 If software enables auto convention...

Page 492: ...eserved 16 OUTSEL Smartcard Data Pin Output Mode Selection Use this bit to select smartcard data pin SC_DATA output mode 0 Quasi mode 1 Open drain mode 15 ACTSTS2 Internal Timer2 Active State Read Onl...

Page 493: ...counting Note1 This field is used for internal 8 bit timer when TMRSEL SC_CTL 14 13 11 Don t fill CNTEN2 when TMRSEL SC_CTL 14 13 00 or TMRSEL SC_CTL 14 13 01 or TMRSEL SC_CTL 14 13 10 Note2 If the o...

Page 494: ...N SC_CTL 0 is not enabled this field cannot be programmed 3 ACTEN Activation Sequence Generator Enable Bit This bit enables SC controller to initiate the card by activation sequence 0 No effect 1 Acti...

Page 495: ...30 NUC970 TECHNICAL REFERENCE MANUAL 0 TXRST TX Software Reset When TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared 0 No effect 1 Reset the TX internal...

Page 496: ...n Reset Value SC_EGT x 0 1 SCx_BA 0x00C R W SC Extend Guard Time Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 E...

Page 497: ...13 12 11 10 9 8 Reserved RFTM 7 6 5 4 3 2 1 0 RFTM Bits Description 31 9 Reserved Reserved 8 0 RFTM SC Receiver FIFO Time out ETU Base The time out counter resets and starts counting whenever the RX...

Page 498: ...Reserved ETURDIV 7 6 5 4 3 2 1 0 ETURDIV Bits Description 31 16 Reserved Reserved 15 CMPEN Compensation Mode Enable Bit This bit enables clock compensation function When this bit enabled hardware will...

Page 499: ...tion error interrupt Enabled 9 RXTOIEN Receiver Buffer Time out Interrupt Enable Bit This field is used for receiver buffer time out interrupt enable 0 Receiver buffer time out interrupt Disabled 1 Re...

Page 500: ...S register which includes receiver break error BEF SC_STATUS 6 frame error FEF SC_STATUS 5 parity error PEF SC_STATUS 4 receiver buffer overflow error RXOV SC_STATUS 0 transmit buffer overflow error T...

Page 501: ...us flag Note This field is the status flag of receiver buffer time out state If software wants to clear this bit software must read all receivers buffer remaining data by reading SC_DAT buffer 8 INITI...

Page 502: ...mit buffer overflow error TXOV SC_STATUS 8 receiver retry over limit error RXOVERR SC_STATUS 22 and transmitter retry over limit error TXOVERR SC_STATUS 30 Note This field is the status flag of BEF SC...

Page 503: ...retry number limitation Note This bit is read only but it can be cleared by writing 1 to it 29 TXRERR Transmitter Retry Error Read Only This bit is set by hardware when transmitter re transmits Note1...

Page 504: ...e cleared by writing 1 to it Note2 The card detect engine will start after SCEN SC_CTL 0 set 11 CREMOVE Card Detect Removal Status of SC_CD Pin Read Only This bit is set whenever card has been removal...

Page 505: ...whenever the received character does not have a valid parity bit Note1 This bit is read only but it can be cleared by writing 1 to it Note2 If CPU sets receiver retries function by setting RXRTY_EN SC...

Page 506: ...ing a new value to SC_PINCTL register 0 Synchronizing is completion user can write new data to SC_PINCTL register 1 Last value is synchronizing Note This bit is read only 29 19 Reserved Reserved 18 RS...

Page 507: ...e SCDATOUT pin to low 1 Drive SCDATOUT pin to high Note When SC is at activation warm reset or deactivation mode this bit will be changed automatically So don t fill this field when SC is in these mod...

Page 508: ...e SC_PWR pin Refer PWRINV SC_PINCTL 11 description for programming SC_PWR pin voltage level Read this field to get SC_PWR pin status 0 SC_PWR pin status is low 1 SC_PWR pin status is high Note When op...

Page 509: ...ontrol Register 0 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OPMODE 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 28 Reserved Reserved 27 24 OPMODE Ti...

Page 510: ...1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OPMODE 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CNT Bits Description 31 28 Reserved Reserved 27 24 OPMODE Timer 1...

Page 511: ...2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OPMODE 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CNT Bits Description 31 28 Reserved Reserved 27 24 OPMODE Timer 2...

Page 512: ...or check the data word and parity bits in receiving mode Note This bit has effect only when PBOFF bit is 0 6 PBOFF Parity Bit Disable Control 0 Parity bit is generated or checked between the last data...

Page 513: ...rence Manual Publication Release Date Dec 15 2015 513 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Bits Description 0 Note3 When UART is enabled hardware will generate a reset to reset FIFO and in...

Page 514: ...ister Offset R W Description Reset Value SC_TMRDAT0 x 0 1 SCx_BA 0x038 R SC Timer Current Data Register 0 0x0000_07FF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 CNT0 15 14 13 12 11 10 9...

Page 515: ...x 0 1 SCx_BA 0x03C R SC Timer Current Data Register 1 0x0000_7F7F 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CNT2 7 6 5 4 3 2 1 0 CNT1 Bits Description 31...

Page 516: ...ave with byte by byte basis Each data byte is 8 bits long There is one SCL clock pulse for each data bit with the MSB being transmitted first An acknowledge bit follows each transferred byte Each bit...

Page 517: ...y it s necessary to configure I O pins as the I2C function and enable I 2 C s clock Write 0x8 to MFP_GPG0 SYS_GPG_MFPL 3 0 and MFP_GPG1 SYS_GPG_MFPL 7 4 configures pin PG 0 and PG 1 to be I2C0_SCL and...

Page 518: ...RT or STOP Please refer to the following figure for more detailed I 2 C BUS Timing tBUF STOP SDA SCL START tHD STA tLOW tHD DAT tHIGH tf tSU DAT Repeated START tSU STA tSU STO STOP tr Figure 5 18 2 I...

Page 519: ...ree idle meaning no master device is engaging the bus both SCL and SDA lines are high a master can initiate a transfer by sending a START signal A START signal usually referred to as the S bit is defi...

Page 520: ...2 A3 A4 A5 A6 slave address The first byte after the START procedure Data Transfer 5 18 5 5 When a slave receives a correct address with an R W bit the data will follow R W bit specified to transfer E...

Page 521: ...knowledge on the I 2 C bus Data transfer on the I 2 C bus 5 18 5 6 The following figure shows a master transmits data to slave A master addresses a slave with a 7 bit address and 1 bit write index to...

Page 522: ...er from the highest byte first For example if CSR Tx_NUM 0x3 Tx 31 24 will be transmitted first then Tx 23 16 and so on In case of a data transfer all bits will be treated as data In case of a slave a...

Page 523: ...not visible Example 2 Read a byte of data from an I 2 C memory device using single byte transfer mode Slave address 0x4E 7 b1001110 Memory location to read from 0x20 I 2 C sequence generate start sig...

Page 524: ...and sequence ACK Second command sequence SCL SDA R ACK Third command sequence NACK P Fourth command sequence Sr D6 D7 D5 D4 D3 D2 D1 D0 Figure 5 18 10 Read a byte of data NOTE Please note that the tim...

Page 525: ...tion Release Date Dec 15 2015 525 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL sda_pad_i Software can read write this register at any time but the output enable scl_padoen_o and sda_padoen_o are c...

Page 526: ...R W I2C n Control and Status Register 0x0000_0000 I2Cn_DIVIDER n 0 1 I2Cn_BA 0x004 R W I2C n Clock Prescale Register 0x0000_0000 I2Cn_CMDR n 0 1 I2Cn_BA 0x008 R W I2C n Command Register 0x0000_0000 I...

Page 527: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 527 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 18 7 Register Description...

Page 528: ...y Read Only 0 After STOP signal detected 1 After START signal detected 9 I2C_AL Arbitration Lost Read Only This bit is set when the I2 C core lost arbitration Arbitration is lost when A STOP signal is...

Page 529: ...completed Transfer has not been completed but slave responded NACK in multi byte transmit mode Arbitration is lost NOTE This bit is read only but can be cleared by writing 1 to this bit 1 IE Interrupt...

Page 530: ...erved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DIVIDER 15 8 7 6 5 4 3 2 1 0 DIVIDER 7 0 Bits Description 15 0 DIVIDER Clock Prescale Register It is used to prescale the SCL clock line Du...

Page 531: ...TOP READ WRITE ACK NOTE Software can write this register only when I2C_EN 1 Bits Description 31 5 Reserved Reserved 4 START Generate Start Condition Generate repeated start condition on I2 C bus 3 STO...

Page 532: ...1 0 Reserved SDR SCR Reserved SDW SCW Bits Description 31 5 Reserved Reserved 4 SDR Serial Interface SDA Status Read Only 0 SDA is Low 1 SDA is High 3 SCR Serial Interface SCK Status Read Only 0 SCL i...

Page 533: ...cription Reset Value I2Cn_RXR n 0 1 I2Cn_BA 0x010 R I2C n Data Receive Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2...

Page 534: ...egister Offset R W Description Reset Value I2Cn_TXR n 0 1 I2Cn_BA 0x014 R W I2C n Data Transmit Register 0x0000_0000 31 30 29 28 27 26 25 24 Tx 23 22 21 20 19 18 17 16 Tx 15 14 13 12 11 10 9 8 Tx 7 6...

Page 535: ...rsion on data characters received from CPU This interface can drive up to 2 external peripherals and is seen as the master 5 19 2 Features Support master mode Full duplex synchronous serial data trans...

Page 536: ...slave device 5 19 4 Basic Configuration Before using SPI functionality it s necessary to configure I O pins as the SPI function and enable SPI s clock Write 0xB to MFP_GPB6 SYS_GPB_MFPL 27 24 MFP_GPB7...

Page 537: ...32 bit transmit receive buffers and can provide burst mode operation The maximum bits can be transmitted received is 32 bits and can transmit receive data up to four times successive It also supports...

Page 538: ...t is cleared slave select signals are asserted and de asserted by setting and clearing related bits in SSR register If this bit is set mw_ss_o signals are generated automatically It means that device...

Page 539: ...is used to define the direction of the transfer data When set the DIR_2QM bit to 1 the controller will send the data to external device When the DIR_2QM bit set 0 the controller will read the data fr...

Page 540: ...Technical Reference Manual Publication Release Date Dec 15 2015 540 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Figure 5 19 5 Dual IO Input Sequence SS SCLK mw_si_i 0 Input mw_si_i 1 Input DUALM...

Page 541: ...cification of device for the detailed steps Write a divisor into DIVIDER to determine the frequency of serial clock Write in SSR set ASS 0 SS_LVL 0 and SSR 0 or SSR 1 to 1 to activate the device you w...

Page 542: ...ave Select Register 0x0000_0000 SPIn_RX0 n 0 1 SPIn_BA 0x010 R SPI n Data Receive Register 0 0x0000_0000 SPIn_RX1 n 0 1 SPIn_BA 0x014 R SPI n Data Receive Register 1 0x0000_0000 SPIn_RX2 n 0 1 SPIn_BA...

Page 543: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 543 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 19 7 Register Description...

Page 544: ...e polarity 22 DUALM Dual I O Mode Enable Control 0 Dual I O mode Disabled 1 Dual I O mode Enabled 21 QUADM Quad I O Mode Enable Control 0 Quad I O mode Disabled 1 Quad I O mode Enabled 20 DIR_2QM Quad...

Page 545: ...it receive will be executed in one transfer 10 Three successive transmit receive will be executed in one transfer 11 Four successive transmit receive will be executed in one transfer 7 3 Tx_BIT_LEN Tr...

Page 546: ...ter Offset R W Description Reset Value SPIn_DIVIDER n 0 1 SPIn_BA 0x004 R W SPI n Clock Divider Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10...

Page 547: ...unction Enabled 2 SS_LVL Slave Select Active Level 0 The slave select signal mw_ss_o is active on low level 1 The slave select signal mw_ss_o is active on high level 1 0 SSR Slave Select Register If S...

Page 548: ...0x01C R SPI n Data Receive Register 3 0x0000_0000 31 30 29 28 27 26 25 24 Rx 23 22 21 20 19 18 17 16 Rx 15 14 13 12 11 10 9 8 Rx 7 6 5 4 3 2 1 0 Rx Bits Description 31 0 Rx Data Receive Register The D...

Page 549: ...Description 31 0 Tx Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer Valid bits depend on the transmit bit length field in the CNTRL register Fo...

Page 550: ...n LSB of a 32 bit word The following are the property of the DMA When 16 bit precision the DMA always 8 beat incrementing burst FIFO_TH 0 or 4 beat incrementing burst FIFO_TH 1 When 24 20 18 bit preci...

Page 551: ...agram 5 20 4 Basic Configuration Before using I 2 S functionality it s necessary to configure I O pins as the I 2 S function and enable I 2 S s clock Write 0x8 to MFP_GPG10 SYS_GPG_MFPH 11 8 MFP_GPG11...

Page 552: ...gnals are shown as the following figure I2S Controller Master I2S_LRCK I2S_BCLK I2S_DO I2S_DI I2S_MCLK Audio Codec Slave Figure 5 20 2 I 2 S Interface Signal of Master Mode I2S Controller Slave I2S_LR...

Page 553: ...LSB MSB word N 1 right channel word N lef channel word N 1 right channel BCLK WS DI DO MSB Justified format Figure 5 20 4 I 2 S MSB Justified Format The sampling rate bit shift clock frequency could b...

Page 554: ...0 NUC970 TECHNICAL REFERENCE MANUAL SLOT1 BCLK FS DI DO SLOT position 0 1 2 7 8 MSB LSB 16 SLOT2 17 23 MSB LSB FS_PERIOD 1 0 SLOT1_x_START SLOT2_x_START SLOT1_O_START ACTL_PCMS1ST 25 16 1 SLOT2_O_STAR...

Page 555: ...PDESB I2S_BA 0x014 R W I2S Play DMA Destination Base Address Register 0x0000_0000 I2S_PDES_LENGTH I2S_BA 0x018 R W I2S Play DMA Destination Length Register 0x0000_0000 I2S_PDESC I2S_BA 0x01C R I2S Pla...

Page 556: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 556 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 20 7 Register Description...

Page 557: ...pt Request Enable Bit 0 not allowed to generation R_FIFO_FULL_IRQ 1 allowed to generation R_FIFO_FULL_IRQ The R_FIFO_FULL_IRQ_EN bit is read write 18 R_FIFO_EMPTY_IRQ_EN Record FIFO Empty Interrupt Re...

Page 558: ...destination end address the P_DMA_RIA_IRQ will be issued 11 When play DMA address reach each eighth of DMA play destination end address the P_DMA_RIA_IRQ will be issued The P_DMA_IRQ_SEL bits are rea...

Page 559: ...is set to 1 The IRQ_DMA_CNTER_EN bit is read write 3 IRQ_DMA_DATA_ZERO_EN IRQ_DMA_DATA Zero and Sign Detect Enable Bit 0 not allowed to set P_DMA_IRQ I2S_CON 10 if I2S_PSR 3 is set to 1 1 allowed to s...

Page 560: ...ot1 Slot2 Data Note this bit work at stereo dual slot mode only 1 Left channel data at I2S_RDESB I2S_PDESB address Right channel data at I2S_RDESB2 I2S_PDESB2 0 Left Right channel data place at I2S_RD...

Page 561: ...0x0 R R R R 19 17 Reserved Reserved 16 RESET Audio Controller Reset Control Bit 0 The audio controller is normal operation 1 The whole audio controller is reset The RESET bit is read write 15 14 RECOR...

Page 562: ...This function is supported to count playback data for software monitoring When one playback data is transferred to codec the DMA counter subtracts 1 When the I2S_COUNTER 31 0 register is Zero that set...

Page 563: ...Reset Value I2S_RDESB I2S_BA 0x008 R W I2S Record DMA Destination Base Address Register 0x0000_0000 Bits Description 31 0 AUDIO_RDESB 32 bit Record Destination Base Address This bit field indicates th...

Page 564: ...Value I2S_RDES_LENGTH I2S_BA 0x00C R W I2S Record DMA Destination Length Register 0x0000_0000 Bits Description 31 0 AUDIO_RDES_L 32 bit Record Destination Address Length The AUDIO_RDES_L 31 0 bits are...

Page 565: ...set Value I2S_RDESC I2S_BA 0x010 R I2S Record DMA Destination Current Address Register 0x0000_0000 Bits Description 31 0 AUDIO_RDESC 32 bit Record Destination Current Address This bit field indicates...

Page 566: ...n Reset Value I2S_PDESB I2S_BA 0x014 R W I2S Play DMA Destination Base Address Register 0x0000_0000 Bits Description 31 0 AUDIO_PDESB 32 bit Play Destination Base Address This bit field indicates the...

Page 567: ...Value I2S_PDES_LENGTH I2S_BA 0x018 R W I2S Play DMA Destination Length Register 0x0000_0000 Bits Description 31 0 AUDIO_PDES_L 32 bit Play Destination Address Length The AUDIO_PDES_L 31 0 bits are re...

Page 568: ...Reset Value I2S_PDESC I2S_BA 0x01C R I2S Play DMA Destination Current Address Register 0x0000_0000 Bits Description 31 0 AUDIO_PDESC 32 bit Play Destination Current Address This bit field indicates th...

Page 569: ...of record FIFO is not happened 1 the full error of record FIFO is happened The R_FIFO_FULL bit is readable and only can be clear by write 1 to this bit 1 R_FIFO_EMPTY Record FIFO EMPTY Indicator Bit...

Page 570: ...unter subtracts 1 The counting of playback data number is used for software monitoring If the DMA counter I2S_COUNTER 31 0 is Zero this bit DMA_CNTER_IRQ will be set to 1 0 DMA counter I2S_COUNTER 31...

Page 571: ...EMPTY Playback FIFO EMPTY Indicator Bit When playback FIFO is empty and the playback data is read from playback FIFO the P_FIFO_EMPTY bit is set to 1 This bit indicates the empty error of playback FIF...

Page 572: ...ALER Selection Bits FPLL Is the Input PLL Frequency MCLK Is the Output Main Clock 0000 MCLK FPLL 1 0001 MCLK FPLL 2 0010 MCLK FPLL 3 0011 MCLK FPLL 4 0100 MCLK FPLL 5 0101 MCLK FPLL 6 0110 MCLK FPLL 7...

Page 573: ...ween PLL and I2 S serial data clock The frequency of I2 S serial data clock follows the formula below BCLK PLL PRS BCLK_DIV 1 2 4 MCLK_SEL MCLK Clock Selection Bit 0 I2 S MCLK output will follow the P...

Page 574: ...gister 0xFFFF_FFFF Bits Description 31 0 COUNTER Play DMA Down Counter This bit field is used to count playback data number for software monitoring When one playback data is transferred to codec the D...

Page 575: ...1 PCM_MCLK FPLL 4 0100 PCM_MCLK FPLL 5 0101 PCM_MCLK FPLL 6 0110 PCM_MCLK FPLL 7 0111 PCM_MCLK FPLL 8 1000 RESERVED 1001 PCM_MCLK FPLL 10 1010 RESERVED 1011 PCM_MCLK FPLL 12 1100 RESERVED 1101 PCM_MCL...

Page 576: ...70 TECHNICAL REFERENCE MANUAL 15 8 PCM_PRS PCM_BCLK Frequency PRE_SCALER Selection Bits BCLK PCM_MCLK 2 PCM_PRS 1 7 1 Reserved Reserved 0 BCLKP BCLK Polarity 0 send data at rising edge latch data at f...

Page 577: ...t Position This bit field is used to set the start position of slot1 output data Example For Short Frame Sync set SLOT1_O_START to 1 For Long Frame Sync set SLOT1_O_START to 0 15 10 Reserved Reserved...

Page 578: ...r 0x0000_0000 Bits Description 31 26 Reserved Reserved 25 16 SLOT2_O_START Slot 2 Data Out Start Position This bit field is used to set the start position of slot2 output data 15 10 Reserved Reserved...

Page 579: ...I2S_RDESB2 I2S_BA 0x040 R W I2S Record DMA Destination Base Address 2 Register 0x0000_0000 Bits Description 31 0 AUDIO_RDESB2 32 bit Record Destination Base Address for Right Channel This bit field in...

Page 580: ...e I2S_PDESB2 I2S_BA 0x044 R W I2S Play DMA Destination Base Address 2 Register 0x0000_0000 Bits Description 31 0 AUDIO_PDESB2 32 bit Play Destination Base Address for Right Channel This bit field indi...

Page 581: ...e EMAC supports RMII Reduced MII interface to connect with external Ethernet PHY 5 21 2 Features Supports IEEE Std 802 3 CSMA CD protocol Supports Ethernet frame time stamping for IEEE Std 1588 2002 p...

Page 582: ...ngine IEEE 1588 PTP Engine Figure 5 21 1 Ethernet MAC Controller Block Diagram 5 21 4 Basic Configuration Before using EMAC functionality it s necessary to configure I O pins as the EMAC function and...

Page 583: ...fter the finish of the frame transmission the TXDMA updates the transmit status of current frame and write the transmit descriptor back to the system memory to indicate the frame transmission has fini...

Page 584: ...sent data will be assembled with the preamble the start frame delimiter SFD the frame check sequence and the padding for enforcing those less than 64 bytes to meet the minimum size frame and CRC sequ...

Page 585: ...cribes how the 64 bit counter works to generate the reference timing The 64 bit counter formed by two 32 bit counters the EMACn_TSSEC and EMACn_TSSUBSEC a updated using the EMAC s input reference cloc...

Page 586: ...ation of each frame Through the descriptor CPU and EMAC exchange the information for frame reception and transmission Two different descriptors defined in EMAC One named as RXDMA descriptor for frame...

Page 587: ...0 If the O 1 b0 indicates the CPU is the owner of RX descriptor After the CPU completed the frame processing it modified the ownership field to 1 b1 and released the RX descriptor to EMAC RXDMA 0 The...

Page 588: ...me is a long frame 18 Reserved Reserved 17 CRCE CRC Error The CRCE indicates the frame stored in the data buffer pointed by RX descriptor incurred CRC error 0 The frame does not incur CRC error 1 The...

Page 589: ...ow 31 30 29 28 27 26 25 24 RXBSA TSLSB 23 22 21 20 19 18 17 16 RXBSA TSLSB 15 14 13 12 11 10 9 8 RXBSA TSLSB 7 6 5 4 3 2 1 0 RXBSA TSLSB Bits Description 31 0 RXBSA Receive Buffer Starting Address The...

Page 590: ...sion V1 30 NUC970 TECHNICAL REFERENCE MANUAL RXDES 2 RXDMA Descriptor Word 2 The RXDMA descriptor word 2 is reserved 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10...

Page 591: ...21 20 19 18 17 16 NRXDSA TSMSB 15 14 13 12 11 10 9 8 NRXDSA TSMSB 7 6 5 4 3 2 1 0 NRXDSA TSMSB Bits Description 31 0 NRXDSA Next RX Descriptor Starting Address NRXDSA is the starting address of the n...

Page 592: ...of four 32 bit words The data structure of TXDMA descriptor shown in figure below 0 15 31 Transmit Frame Buffer Starting Address Time Stamp Least Significant 32 Bit P Next TxDMA Descriptor Starting A...

Page 593: ...for frame transmission After the frame transmission completed EMAC TXDMA modify ownership field to 1 b0 and return the ownership of TX descriptor to CPU If the O 1 b0 indicates the CPU is the owner o...

Page 594: ...PP is enabled the 4 bytes CRC checksum will be appended to frame at the end of frame transmission 0 4 bytes CRC appending Disabled 1 4 bytes CRC appending Enabled 0 PADEN Padding Enable Control The PA...

Page 595: ...24 TXBSA TSLSB 23 22 21 20 19 18 17 16 TXBSA TSLSB 15 14 13 12 11 10 9 8 TXBSA TSLSB 7 6 5 4 3 2 1 0 TXBSA TSLSB Bits Description 31 2 TXBSA Transmit Buffer Starting Address The TXBSA is the starting...

Page 596: ...smitted out on MII RMII 0 TX Descriptor Word 1 and TX Descriptor Word 3 does not keep the time stamp value 1 TX Descriptor Word 1 and TX Descriptor Word 3 keep the time stamp value 26 SQE SQE Error Th...

Page 597: ...CRS signal does not active at the start of or during the packet transmission 1 CRS signal actives correctly 20 EXDEF Defer Exceed The EXDEF indicates the frame waiting for transmission has deferred ov...

Page 598: ...TXDSA TSMSB 15 14 13 12 11 10 9 8 NTXDSA TSMSB 7 6 5 4 3 2 1 0 NTXDSA TSMSB Bits Description 31 0 NTXDSA Next TX Descriptor Starting Address NTXDSA is the starting address of the next TX descriptor Wh...

Page 599: ...Least Significant Word Register 0x0000_0000 EMACn_CAM2M n 0 1 EMACn_BA 0x018 R W EMAC n CAM 2 Most Significant Word Register 0x0000_0000 EMACn_CAM2L n 0 1 EMACn_BA 0x01C R W EMAC n CAM 2 Least Signif...

Page 600: ...11 Most Significant Word Register 0x0000_0000 EMACn_CAM11L n 0 1 EMACn_BA 0x064 R W EMAC n CAM 11 Least Significant Word Register 0x0000_0000 EMACn_CAM12M n 0 1 EMACn_BA 0x068 R W EMAC n CAM 12 Most S...

Page 601: ...errupt Status Register 0x0000_0000 EMACn_MGSTA n 0 1 EMACn_BA 0x0B4 R W EMAC n MAC General Status Register 0x0000_0000 EMACn_MPCNT n 0 1 EMACn_BA 0x0B8 R W EMAC n Missed Packet Count Register 0x0000_7...

Page 602: ..._BA 0x11C R W EMAC n Time Stamp Addend Register 0x0000_0000 EMACn_UPDSEC n 0 1 EMACn_BA 0x120 R W EMAC n Time Stamp Update Second Register 0x0000_0000 EMACn_UPDSUBSEC n 0 1 EMACn_BA 0x124 R W EMAC n T...

Page 603: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 603 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 21 8 Register Description...

Page 604: ...to receive a packet with specific destination MAC address configures the MAC address into CAM 12 0 then enables that CAM entry and set ECMP to 1 0 CAM comparison function for destination MAC address...

Page 605: ...all unicast packets CAMCMR Setting and Comparison Results The following table is the address recognition result in different CAMCMR configuration The column Result shows the incoming packet type that...

Page 606: ...MANUAL 1 0 0 0 1 C B 1 0 0 1 0 C M 1 0 0 1 1 C M B 1 0 1 0 0 C U 1 0 1 0 1 C U B 1 0 1 1 0 C U M 1 0 1 1 1 C U M B 1 1 0 0 0 U M B 1 1 0 0 1 U M B 1 1 0 1 0 U M B 1 1 0 1 1 U M B 1 1 1 0 0 C U M B 1 1...

Page 607: ...0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 CAM15EN CAM14EN CAM13EN CAM12EN CAM11EN CAM10EN CAM9EN CAM8EN 7 6 5 4 3 2 1 0 CAM7EN CAM6EN CAM5EN C...

Page 608: ...ificant Word Register 0x0000_0000 EMACn_CAM2M n 0 1 EMACn_BA 0x018 R W EMAC n CAM 2 Most Significant Word Register 0x0000_0000 EMACn_CAM3M n 0 1 EMACn_BA 0x020 R W EMAC n CAM 3 Most Significant Word R...

Page 609: ...2 11 10 9 8 CAMxM 7 6 5 4 3 2 1 0 CAMxM Bits Description 31 0 CAMxM CAMx Most Significant Word The CAMxM keeps the bit 47 16 of MAC address The x can be the 0 12 The register pair EMACn_CAMxM EMACn_CA...

Page 610: ...nt Word Register 0x0000_0000 EMACn_CAM2L n 0 1 EMACn_BA 0x01C R W EMAC n CAM 2 Least Significant Word Register 0x0000_0000 EMACn_CAM3L n 0 1 EMACn_BA 0x024 R W EMAC n CAM 3 Least Significant Word Regi...

Page 611: ...erved 7 6 5 4 3 2 1 0 Reserved Bits Description 31 16 CAMxL CAMx Least Significant Word The CAMxL keeps the bit 15 0 of MAC address The x can be the 0 14 The register pair EMACn_CAMxM EMACn_CAMxL repr...

Page 612: ...estination MAC address The corresponding CAM enable bit CAMxEN EMACn_CAMEN x is also needed be enabled The x can be the 0 to 12 The register pairs EMACn_CAM13M EMACn_CAM13L EMACn_CAM14M EMACn_CAM14L a...

Page 613: ...keep a destination MAC address The corresponding CAM enable bit CAMxEN EMACn_CAMEN x is also needed be enabled The x can be the 0 to 12 The register pairs EMACn_CAM13M EMACn_CAM13L EMACn_CAM14M EMACn...

Page 614: ...n Reset Value EMACn_TXDLS A n 0 1 EMACn_BA 0x088 R W EMAC n Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC 31 30 29 28 27 26 25 24 TXDLSA 23 22 21 20 19 18 17 16 TXDLSA 15 14 13 12 1...

Page 615: ...ption Reset Value EMACn_RXDLSA n 0 1 EMACn_BA 0x08C R W EMAC n Receive Descriptor Link List Start Address Register 0xFFFF_FFFC 31 30 29 28 27 26 25 24 RXDLSA 23 22 21 20 19 18 17 16 RXDLSA 15 14 13 12...

Page 616: ...erved NDEF TXON 7 6 5 4 3 2 1 0 PTP_SRC MGP_WAKE SPCRC AEP ACP ARP ALP RXON Bits Description 31 25 Reserved Reserved 24 SWR Software Reset The SWR implements a reset function to make the EMAC return d...

Page 617: ...the SDPZ will be cleared automatically It is recommended that only enabling SPDZ while EMAC is operating in Full Duplex mode 0 PAUSE control frame transmission completed 1 PAUSE control frame transmis...

Page 618: ...reception If the ACP is set to high the EMAC will accept the control frame Otherwise the control frame will be dropped It is recommended that S W only enable ACP while EMAC is operating on full duple...

Page 619: ...mand or the data that is read from the registers of external PHY for read command Register Offset R W Description Reset Value EMACn_MIID n 0 1 EMACn_BA 0x09 4 R W EMAC n MII Management Data Register 0...

Page 620: ...controls the MDC clock generation If the MDCON is set to high the MDC clock actives always Otherwise the MDC will only active while S W issues a MII management command 0 MDC clock only actives while S...

Page 621: ...unction is used for the purpose of controlling the PHY and gathering status from the PHY The MII management frame format is shown as follow Management Frame Fields PRE ST OP PHYAD REGAD TA DATA IDLE R...

Page 622: ...n_FFTCR also defines the burst length of AHB bus cycle for system memory access Register Offset R W Description Reset Value EMACn_FFTCR n 0 1 EMACn_BA 0x09 C R W EMAC n FIFO Threshold Control Register...

Page 623: ...than TXFIFO high threshold the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO 00 Undefined 10 TXFIFO low threshold is 80B and high threshold is 160B 01 TXFIFO l...

Page 624: ...17 16 TSD 15 14 13 12 11 10 9 8 TSD 7 6 5 4 3 2 1 0 TSD Bits Description 31 0 TSD Transmit Start Demand If the TX descriptor is not available for use of TXDMA after the TXON EMACn_MCMDR 8 is enabled...

Page 625: ...18 17 16 RSD 15 14 13 12 11 10 9 8 RSD 7 6 5 4 3 2 1 0 RSD Bits Description 31 0 RSD Receive Start Demand If the RX descriptor is not available for use of RXDMA after the RXON EMACn_MCMDR 0 is enabled...

Page 626: ...F C n 0 1 EMACn_BA 0x0 A8 R W EMAC n Maximum Receive Frame Control Register 0x0000_0800 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXMS 7 6 5 4 3 2 1 0 RXM...

Page 627: ...ion 31 29 Reserved Reserved 28 TSALMIEN Time Stamp Alarm Interrupt Enable Control The TSALMIEN controls the TSALS EMACn_MISTA 28 interrupt generation If TSALS EMACn_MISTA 28 is set and both TSALMIEN a...

Page 628: ...generated to CPU even the TXABT EMACn_MISTA 21 is set 0 TXABT EMACn_MISTA 21 trigger TX interrupt Disabled 1 TXABT EMACn_MISTA 21 trigger TX interrupt Enabled 20 NCSIEN No Carrier Sense Interrupt Enab...

Page 629: ...s the RX interrupt to CPU If WOLIEN or RXIEN EMACn_MIEN 0 is disabled no RX interrupt is generated to CPU even the MPR EMACn_MISTA 15 is set 0 MPR EMACn_MISTA 15 trigger RX interrupt Disabled 1 MPR EM...

Page 630: ...0 is disabled no RX interrupt is generated to CPU even the MMP EMACn_MISTA 7 is set 0 MMP EMACn_MISTA 7 trigger RX interrupt Disabled 1 MMP EMACn_MISTA 7 trigger RX interrupt Enabled 6 RPIEN Runt Pac...

Page 631: ...interrupt Disabled 1 RXOV EMACn_MISTA 2 trigger RX interrupt Enabled 1 CRCEIEN CRC Error Interrupt Enable Control The CRCEIEN controls the CRCE EMACn_MISTA 1 interrupt generation If CRCE EMACn_MISTA...

Page 632: ...4 3 2 1 0 MMP RP ALIE RXGD PTLE RXOV CRCE RXINTR Bits Description 31 29 Reserved Reserved 28 TSALS Time Stamp Alarm Interrupt The TSALS high indicates the EMACn_TSMSR register value equals to EMACn_T...

Page 633: ...operating on half duplex mode If the TXABT is high and TXABTIEN EMACn_MIEN 21 is enabled the TXINTR will be high Write 1 to this bit clears the TXABT status 0 Packet does not incur 16 consecutive coll...

Page 634: ...s a logic OR result clears EMC_MISTA 28 17 makes TXINTR be cleared too 0 No status bit in EMACn_MISTA 28 17 is set or no enable bit in EMACn_MIEN 28 17 is enabled 1 At least one status in EMACn_MISTA...

Page 635: ...ng packet doesn t exceed the length limitation configured in DMARFC 1 The length of the incoming packet has exceeded the length limitation configured in DMARFC 7 MMP More Missed Packet Interrupt The M...

Page 636: ...uring packet reception 1 RXFIFO overflow occurred during packet reception 1 CRCE CRC Error Interrupt The CRCE high indicates the incoming packet incurred the CRC error and the packet is dropped If the...

Page 637: ...counting actives After Ethernet MAC controller sent PAUSE frame out successfully it starts the remote pause counter down counting When this bit high it s predictable that remote Ethernet MAC controlle...

Page 638: ...during a packet transmission If the packet incurred 16 consecutive collisions during transmission the CCNT will be 4 h0 and bit TXABT will be set to 1 3 Reserved Reserved 2 RXFFULL RXFIFO Full The RX...

Page 639: ...ounter is overflow the MMP EMACn_MISTA 7 will be set Register Offset R W Description Reset Value EMACn_MPCNT n 0 1 EMACn_BA 0x0B8 R W EMAC n Missed Packet Count Register 0x0000_7FFF 31 30 29 28 27 26...

Page 640: ...l keep the same while TX of EMAC is pausing due to the PAUSE control frame is received The EMACn_MRPC is read only and write to this register has no effect Register Offset R W Description Reset Value...

Page 641: ...R W EMAC n DMA Receive Frame Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RXFLT 7 6 5 4 3 2 1 0 RXFLT Bits Description 31 16 Res...

Page 642: ...Cn_CTXDSA n 0 1 EMACn_BA 0x0CC R EMAC n Current Transmit Descriptor Start Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CTXDSA 23 22 21 20 19 18 17 16 CTXDSA 15 14 13 12 11 10 9 8 CTXDSA 7 6 5...

Page 643: ...Cn_CTXBSA n 0 1 EMACn_BA 0x0D 0 R EMAC n Current Transmit Buffer Start Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CTXBSA 23 22 21 20 19 18 17 16 CTXBSA 15 14 13 12 11 10 9 8 CTXBSA 7 6 5 4 3...

Page 644: ...Cn_CRXDSA n 0 1 EMACn_BA 0x0D 4 R EMAC n Current Receive Descriptor Start Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CRXDSA 23 22 21 20 19 18 17 16 CRXDSA 15 14 13 12 11 10 9 8 CRXDSA 7 6 5...

Page 645: ...ACn_CRXBSA n 0 1 EMACn_BA 0x0D8 R EMAC n Current Receive Buffer Start Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CRXBSA 23 22 21 20 19 18 17 16 CRXBSA 15 14 13 12 11 10 9 8 CRXBSA 7 6 5 4 3...

Page 646: ...to EMACn_ALMSEC and EMACn_TSSUBSEC equals to EMACn_ALMSUBSEC 0 Alarm disabled when EMACn_TSSEC equals to EMACn_ALMSEC and EMACn_TSSUBSEC equals to EMACn_ALMSUBSEC 1 Alarm enabled when EMACn_TSSEC equ...

Page 647: ...After the load operation finished Ethernet MAC controller clear this bit to low automatically 0 Time stamp counter initialization done 1 Time stamp counter initialization Enabled 0 TSEN Time Stamp Fun...

Page 648: ...lue EMACn_TSSEC n 0 1 EMACn_BA 0x110 R W EMAC n Time Stamp Counter Second Register 0x0000_0000 31 30 29 28 27 26 25 24 SEC 23 22 21 20 19 18 17 16 SEC 15 14 13 12 11 10 9 8 SEC 7 6 5 4 3 2 1 0 SEC Bit...

Page 649: ...SSUB SEC n 0 1 EMACn_BA 0x114 R W EMAC n Time Stamp Counter Sub Second Register 0x0000_0000 31 30 29 28 27 26 25 24 SUBSEC 23 22 21 20 19 18 17 16 SUBSEC 15 14 13 12 11 10 9 8 SUBSEC 7 6 5 4 3 2 1 0 S...

Page 650: ...Cn_BA 0x118 R W EMAC n Time Stamp Increment Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CNTINC Bits Descriptio...

Page 651: ...0 29 28 27 26 25 24 ADDEND 23 22 21 20 19 18 17 16 ADDEND 15 14 13 12 11 10 9 8 ADDEND 7 6 5 4 3 2 1 0 ADDEND Bits Description 31 0 ADDEND Time Stamp Counter Addend This register keeps a 32 bit value...

Page 652: ...MACn_UPDSE C n 0 1 EMACn_BA 0x120 R W EMAC n Time Stamp Update Second Register 0x0000_0000 31 30 29 28 27 26 25 24 SEC 23 22 21 20 19 18 17 16 SEC 15 14 13 12 11 10 9 8 SEC 7 6 5 4 3 2 1 0 SEC Bits De...

Page 653: ...EC n 0 1 EMACn_BA 0x12 4 R W EMAC n Time Stamp Update Sub Second Register 0x0000_0000 31 30 29 28 27 26 25 24 SUBSEC 23 22 21 20 19 18 17 16 SUBSEC 15 14 13 12 11 10 9 8 SUBSEC 7 6 5 4 3 2 1 0 SUBSEC...

Page 654: ...e Stamp Alarm Second Register 0x0000_0000 31 30 29 28 27 26 25 24 SEC 23 22 21 20 19 18 17 16 SEC 15 14 13 12 11 10 9 8 SEC 7 6 5 4 3 2 1 0 SEC Bits Description 31 0 SEC Time Stamp Counter Second Alar...

Page 655: ...Alarm Sub Second Register 0x0000_0000 31 30 29 28 27 26 25 24 SUBSEC 23 22 21 20 19 18 17 16 SUBSEC 15 14 13 12 11 10 9 8 SUBSEC 7 6 5 4 3 2 1 0 SUBSEC Bits Description 31 0 SUBSEC Time Stamp Counter...

Page 656: ...erface The USB device controller is complaint with USB 2 0 specification and it contains 12 configurable endpoints in addition to control endpoint These endpoints could be configured to BULK INTERRUPT...

Page 657: ...Description Operation of different In transfer modes 5 22 5 1 The data for any in transfer is written into the internal buffer when in turn is sent to the host on receipt of an in token There are thre...

Page 658: ...ken This mode requires intervention of CPU for each transfer But this would be useful if the data count to be sent each time is not fixed and it is being decided by CPU EPxTXCNT Written Data Availabil...

Page 659: ...s the real memory address and length The descriptor will be an 8 byte format like the following Format 31 30 29 0 Word0 MEM_ADDR 31 0 Word1 EOT RD Reserved Count 19 0 MEM_ADDR It specifies the memory...

Page 660: ...0x034 R W Control Endpoint Interrupt Status 0x0000_1800 USBD_CEPTXCNT USBD_BA 0x038 R W Control Endpoint In Transfer Data Count 0x0000_0000 USBD_CEPRXCNT USBD_BA 0x03C R Control Endpoint Out Transfer...

Page 661: ...nt B RAM Start Address Register 0x0000_0000 USBD_EPBBUFEND USBD_BA 0x0B0 R W Endpoint B RAM End Address Register 0x0000_0000 USBD_EPCDAT USBD_BA 0x0B4 R W Endpoint C Data Register 0x0000_0000 USBD_EPC...

Page 662: ...oint E RAM End Address Register 0x0000_0000 USBD_EPFDAT USBD_BA 0x12C R W Endpoint F Data Register 0x0000_0000 USBD_EPFINTSTS USBD_BA 0x130 R W Endpoint F Interrupt Status Register 0x0000_0003 USBD_EP...

Page 663: ...point I Data Register 0x0000_0000 USBD_EPIINTSTS USBD_BA 0x1A8 R W Endpoint I Interrupt Status Register 0x0000_0003 USBD_EPIINTEN USBD_BA 0x1AC R W Endpoint I Interrupt Enable Register 0x0000_0000 USB...

Page 664: ...0x0000_00B2 USBD_EPKBUFSTART USBD_BA 0x214 R W Endpoint K RAM Start Address Register 0x0000_0000 USBD_EPKBUFEND USBD_BA 0x218 R W Endpoint K RAM End Address Register 0x0000_0000 USBD_EPLDAT USBD_BA 0x...

Page 665: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 665 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 22 7 Register Description...

Page 666: ...interrupt event is occurred 12 EPKIF Endpoints K Interrupt When set the corresponding Endpoint K s interrupt status register should be read to determine the cause of the interrupt 0 No interrupt event...

Page 667: ...occurred 4 EPCIF Endpoints C Interrupt When set the corresponding Endpoint C s interrupt status register should be read to determine the cause of the interrupt 0 No interrupt event occurred 1 The rel...

Page 668: ...bled 1 The related interrupt Enabled 12 EPKIEN Interrupt Enable Control for Endpoint K When set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K 0 The...

Page 669: ...related interrupt Disabled 1 The related interrupt Enabled 4 EPCIEN Interrupt Enable Control for Endpoint C When set this bit enables a local interrupt to be generated when an interrupt is pending for...

Page 670: ...ear this bit to 0 7 Reserved Reserved 6 PHYCLKVLDIF Usable Clock Interrupt 0 Usable clock is not available 1 Usable clock is available from the transceiver Note Write 1 to clear this bit to 0 5 DMADON...

Page 671: ...as occurred Note Write 1 to clear this bit to 0 1 RSTIF Reset Status When set this bit indicates that either the USB root port reset is end 0 No USB root port reset is end 1 USB root port reset is end...

Page 672: ...rupt Enable Control This bit enables the VBUS floating detection interrupt 0 VBUS floating detection interrupt Disabled 1 VBUS floating detection interrupt Enabled 7 Reserved Reserved 6 PHYCLKVLDIEN U...

Page 673: ...EN Resume This bit enables the Resume interrupt 0 Resume interrupt Disabled 1 Resume interrupt Enabled 1 RSTIEN Reset Status This bit enables the USB Reset interrupt 0 USB Reset interrupt Disabled 1 U...

Page 674: ...on 31 3 Reserved Reserved 2 CURSPD USB Current Speed 0 The device has settled in Full Speed 1 The USB device controller has settled in High speed 1 HISPDEN USB High speed 0 The USB device controller t...

Page 675: ...me Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved FRAMECNT 7 6 5 4 3 2 1 0 FRAMECNT MFRAMECNT Bits Description 31 14 Reserv...

Page 676: ...Reset Value USBD_FADDR USBD_BA 0x020 R W USB Function Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Rese...

Page 677: ...W USB Test Mode Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved TESTMODE Bits Description 31 3 Reserved...

Page 678: ...ffset R W Description Reset Value USBD_CEPDAT USBD_BA 0x028 R W Control Endpoint Data Buffer 0x0000_0000 31 30 29 28 27 26 25 24 DAT 23 22 21 20 19 18 17 16 DAT 15 14 13 12 11 10 9 8 DAT 7 6 5 4 3 2 1...

Page 679: ...packet to the host during Data stage to an IN token 1 USB device controller can send a zero length packet to the host during Data stage to an IN token This bit gets cleared once the zero length data...

Page 680: ...ce controller will be responding with NAKs for the subsequent status phase This mechanism holds the host from moving to the next request until the local CPU is also ready to process the next request 1...

Page 681: ...ndpoint Enabled 11 BUFFULLIEN Buffer Full Interrupt 0 The buffer full interrupt in Control Endpoint Disabled 1 The buffer full interrupt in Control Endpoint Enabled 10 STSDONEIEN Status Completion Int...

Page 682: ...t Control Endpoint Enabled 3 INTKIEN In Token Interrupt 0 The IN token interrupt in Control Endpoint Disabled 1 The IN token interrupt in Control Endpoint Enabled 2 OUTTKIEN Out Token Interrupt 0 The...

Page 683: ...e 1 to clear this bit to 0 11 BUFFULLIF Buffer Full Interrupt 0 The control endpoint buffer is not full 1 The control endpoint buffer is full Note Write 1 to clear this bit to 0 10 STSDONEIF Status Co...

Page 684: ...oken from the host 1 The control endpoint receives a ping token from the host Note Write 1 to clear this bit to 0 3 INTKIF In Token Interrupt 0 The control endpoint does not received an IN token from...

Page 685: ...0 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 TXCNT Bits Description 31 8 Reserved Reserved 7 0 TXCNT In transfer Data Count There is no mode selection for the control endpoint...

Page 686: ...Reset Value USBD_CEPRXCNT USBD_BA 0x03C R Control Endpoint Out Transfer Data Count 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4...

Page 687: ...set R W Description Reset Value USBD_CEPDATCNT USBD_BA 0x040 R Control Endpoint Data Count 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 DATCNT 7...

Page 688: ...10 9 8 SETUP1 7 6 5 4 3 2 1 0 SETUP0 Bits Description 31 16 Reserved Reserved 15 8 SETUP1 Setup Byte 1 15 8 This register provides byte 1 of the last setup packet received For a Standard Device Reque...

Page 689: ...7 0 This register provides byte 0 of the last setup packet received For a Standard Device Request the following bmRequestType information is returned Bit 7 Direction 0 Host to device 1 Device to host...

Page 690: ...ved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 SETUP3 7 6 5 4 3 2 1 0 SETUP2 Bits Description 31 16 Reserved Reserved 15 8 SETUP3 Setup Byte 3 15 8 This register provides byte 3 of the las...

Page 691: ...served 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 SETUP5 7 6 5 4 3 2 1 0 SETUP4 Bits Description 31 16 Reserved Reserved 15 8 SETUP5 Setup Byte 5 15 8 This register provides byte 5 of the...

Page 692: ...ed 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 SETUP7 7 6 5 4 3 2 1 0 SETUP6 Bits Description 31 16 Reserved Reserved 15 8 SETUP7 Setup Byte 7 15 8 This register provides byte 7 of the last...

Page 693: ...W Description Reset Value USBD_CEPBUFSTART USBD_BA 0x054 R W Control Endpoint RAM Start Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10...

Page 694: ...R W Description Reset Value USBD_CEPBUFEND USBD_BA 0x058 R W Control Endpoint RAM End Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9...

Page 695: ...tion 31 8 Reserved Reserved 7 DMARST Reset DMA State Machine 0 No reset the DMA state machine 1 Reset the DMA state machine 6 SGEN Scatter Gather Function Enable Control 0 Scatter gather function Disa...

Page 696: ...R W Description Reset Value USBD_DMACNT USBD_BA 0x060 R W DMA Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved DMACNT 15 14 13 12 11 10 9 8 DMACNT 7 6 5 4...

Page 697: ...0000 USBD_EPFDAT USBD_BA 0x12C R W Endpoint F Data Register 0x0000_0000 USBD_EPGDAT USBD_BA 0x154 R W Endpoint G Data Register 0x0000_0000 USBD_EPHDAT USBD_BA 0x17C R W Endpoint H Data Register 0x0000...

Page 698: ...er 0x0000_0003 USBD_EPHINTSTS USBD_BA 0x180 R W Endpoint H Interrupt Status Register 0x0000_0003 USBD_EPIINTSTS USBD_BA 0x1A8 R W Endpoint I Interrupt Status Register 0x0000_0003 USBD_EPJINTSTS USBD_B...

Page 699: ...received from the host 1 A Data PING token has been received from the host Note Write 1 to clear this bit to 0 6 INTKIF Data IN Token Interrupt 0 Not Data IN token has been received from the host 1 A...

Page 700: ...t a count of 0 1 The currently selected buffer has a count of 0 or no buffer is available on the local side nothing to read Note This bit is read only 0 BUFFULLIF Buffer Full For an IN endpoint the cu...

Page 701: ...dpoint G Interrupt Enable Register 0x0000_0000 USBD_EPHINTEN USBD_BA 0x184 R W Endpoint H Interrupt Enable Register 0x0000_0000 USBD_EPIINTEN USBD_BA 0x1AC R W Endpoint I Interrupt Enable Register 0x0...

Page 702: ...ontrol When set this bit enables a local interrupt to be set when a PING token has been received from the host 0 PING token interrupt Disabled 1 PING token interrupt Enabled 6 INTKIEN Data IN Token In...

Page 703: ...host 0 Short data packet interrupt Disabled 1 Short data packet interrupt Enabled 1 BUFEMPTYIEN Buffer Empty Interrupt When set this bit enables a local interrupt to be set when a buffer empty conditi...

Page 704: ...USBD_EPFDATCN T USBD_BA 0x138 R Endpoint F Data Available Count Register 0x0000_0000 USBD_EPGDATCN T USBD_BA 0x160 R Endpoint G Data Available Count Register 0x0000_0000 USBD_EPHDATCN T USBD_BA 0x188...

Page 705: ...ICAL REFERENCE MANUAL 15 0 DATCNT Data Count For an IN endpoint EPDIR USBD_EPxCFG 3 is high this register returns the number of valid bytes in the IN endpoint packet buffer For an OUT endpoint EPDIR U...

Page 706: ...sponse Control Register 0x0000_0000 USBD_EPFRSPCT L USBD_BA 0x13C R W Endpoint F Response Control Register 0x0000_0000 USBD_EPGRSPCT L USBD_BA 0x164 R W Endpoint G Response Control Register 0x0000_000...

Page 707: ...t on reception of an IN token 4 HALT Endpoint Halt This bit is used to send a STALL handshake as response to the token from the host When an Endpoint Set Feature ep_halt is detected by the local CPU i...

Page 708: ...USBD_EPFMPS USBD_BA 0x140 R W Endpoint F Maximum Packet Size Register 0x0000_0000 USBD_EPGMPS USBD_BA 0x168 R W Endpoint G Maximum Packet Size Register 0x0000_0000 USBD_EPHMPS USBD_BA 0x190 R W Endpo...

Page 709: ...1C R W Endpoint E Transfer Count Register 0x0000_0000 USBD_EPFTXCN T USBD_BA 0x144 R W Endpoint F Transfer Count Register 0x0000_0000 USBD_EPGTXCN T USBD_BA 0x16C R W Endpoint G Transfer Count Registe...

Page 710: ...15 2015 710 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 10 0 TXCNT Endpoint Transfer Count For IN endpoints this field determines the total number of bytes to be sent to the host in case of manua...

Page 711: ...ndpoint E Configuration Register 0x0000_0052 USBD_EPFCF G USBD_BA 0x148 R W Endpoint F Configuration Register 0x0000_0062 USBD_EPGCF G USBD_BA 0x170 R W Endpoint G Configuration Register 0x0000_0072 U...

Page 712: ...dpoint Direction 0 out endpoint Host OUT to Device 1 in endpoint Host IN to Device Note A maximum of one OUT and IN endpoint is allowed for each endpoint number 2 1 EPTYPE Endpoint Type This field sel...

Page 713: ...USBD_EPFBUFSTART USBD_BA 0x14C R W Endpoint F RAM Start Address Register 0x0000_0000 USBD_EPGBUFSTAR T USBD_BA 0x174 R W Endpoint G RAM Start Address Register 0x0000_0000 USBD_EPHBUFSTAR T USBD_BA 0x1...

Page 714: ...0 USBD_EPFBUFEND USBD_BA 0x150 R W Endpoint F RAM End Address Register 0x0000_0000 USBD_EPGBUFEND USBD_BA 0x178 R W Endpoint G RAM End Address Register 0x0000_0000 USBD_EPHBUFEND USBD_BA 0x1A0 R W End...

Page 715: ...Offset R W Description Reset Value USBD_DMAADDR USBD_BA 0x700 R W AHB DMA Address Register 0x0000_0000 31 30 29 28 27 26 25 24 DMAADDR 23 22 21 20 19 18 17 16 DMAADDR 15 14 13 12 11 10 9 8 DMAADDR 7 6...

Page 716: ...20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved PHYEN DPPUEN 7 6 5 4 3 2 1 0 Reserved Bits Description 31 VBUSDET VBUS Status 0 The VBUS is not detected yet 1 The VBUS is detected 30 25 Reserv...

Page 717: ...s The attached peripherals share USB bandwidth through a host scheduled token based protocol Peripherals may be attached configured used and detached while the host and other peripherals continue oper...

Page 718: ...als and performs the necessary operation register read writes The CPU acts as a bus master having initiated this transfer At that time EHCI acts as a target and responds to the transfer initiated by t...

Page 719: ...ntroller is through the slave interface List Processing The List Processor manages the data structures from the Host Controller Driver and coordinates all activity within the Host Controller Frame Man...

Page 720: ...ll as the Serial Interface Engine SIE and USB clock generator The interface combines responsibility for executing bus transactions requested by the HC as well as the hub and port management specified...

Page 721: ...CI_BA 0x068 R W USB Port 1 Status and Control Register 0x0000_2000 USBPCR0 EHCI_BA 0x0C4 R W USB PHY 0 Control Register 0x0000_0060 USBPCR1 EHCI_BA 0x0C8 R W USB PHY 1 Control Register 0x0000_0020 HcR...

Page 722: ...H OHCI_BA 0x044 R W Host Controller Low Speed Threshold Register 0x0000_0628 HcRhDeA OHCI_BA 0x048 R W Host Controller Root Hub Descriptor A Register 0x0100_0002 HcRhDeB OHCI_BA 0x04C R W Host Control...

Page 723: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 723 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 23 7 Register Description...

Page 724: ...4 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 CRLEN Bits Description 31 16 VERSION Host Controller Interface Version Number This is a two byte register containing a BCD encoding of the EHCI revision numb...

Page 725: ...r companion host controller It is used to indicate the port routing configuration to system software For example if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of...

Page 726: ...ous Scheduling Threshold This field indicates relative to the current position of the executing host controller where software can reliably update the isochronous schedule When bit 7 is zero the value...

Page 727: ...eshold Control R W This field is used by system software to select the maximum rate at which the host controller will issue interrupts The only valid values are defined below If software writes an inv...

Page 728: ...ter to access the Periodic Schedule 3 2 FLSZ Frame List Size R W or RO This field is R W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one This field specifies the size o...

Page 729: ...troller completes the current and any actively pipelined transactions on the USB and then halts The Host Controller must halt within 16 micro frames after software clears the Run bit The HC Halted bit...

Page 730: ...c Schedule Status RO The bit reports the current real status of the Periodic Schedule If this bit is a zero then the status of the Periodic Schedule is disabled If this bit is a one then the status of...

Page 731: ...a one as a result of a J K transition detected on a suspended port This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownersh...

Page 732: ...ontroller will issue an interrupt The interrupt is acknowledged by software clearing the Host System Error bit 3 FLREN Frame List Rollover Enable When this bit is a one and the Frame List Rollover bit...

Page 733: ...0 9 8 Reserved FI 7 6 5 4 3 2 1 0 FI Bits Description 31 14 Reserved Reserved 13 0 FI Frame Index The value in this register increment at the end of each time frame e g micro frame Bits N 3 are used f...

Page 734: ...gister Offset R W Description Reset Value UPFLBAR EHCI_BA 0x034 R W USB Periodic Frame List Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 BADDR 23 22 21 20 19 18 17 16 BADDR 15 14 13 12 11...

Page 735: ...escription Reset Value UCALAR EHCI_BA 0x038 R W USB Current Asynchronous List Address Register 0x0000_0000 31 30 29 28 27 26 25 24 LPL 23 22 21 20 19 18 17 16 LPL 15 14 13 12 11 10 9 8 LPL 7 6 5 4 3 2...

Page 736: ...18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved ASTMR 7 6 5 4 3 2 1 0 ASTMR Bits Description 31 11 Reserved Reserved 11 0 ASSTMR Asynchronous Schedule Sleep Timer This field defines the AsyncSchedSl...

Page 737: ...16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved CF Bits Description 31 1 Reserved Reserved 0 CF Configure Flag CF Host software sets this bit as the last action in its process of c...

Page 738: ...0x1 Test J_STATE 0x2 Test K_STATE 0x3 Test SE0_NAK 0x4 Test Packet 0x5 Test FORCE_ENABLE 15 14 Reserved Reserved 13 PO Port Owner R W This bit unconditionally goes to a 0b when the Configured bit in t...

Page 739: ...reset sequence Software must keep this bit at a one long enough to ensure the reset sequence as specified in the USB Specification Revision 2 0 completes Note when software writes this bit to a one i...

Page 740: ...hen the effects on the bus are undefined Software sets this bit to a 1 to drive resume signaling The Host Controller sets this bit to a 1 if a J to K transition is detected while the port is in the Su...

Page 741: ...es not change until the port state actually changes There may be a delay in disabling or enabling a port due to other host controller and bus events When the port is disabled 0b downstream propagation...

Page 742: ...id This bit is a flag to indicate if the UTMI clock from USB 2 0 PHY is ready S W program must prevent to write other control registers before this UTMI clock valid flag is active 0 UTMI clock is not...

Page 743: ...5 14 13 12 11 10 9 8 Reserved SUSPEND 7 6 5 4 3 2 1 0 Reserved Bits Description 31 9 Reserved Reserved 8 SUSPEND Suspend Assertion This bit controls the suspend mode of USB PHY 1 While PHY was suspend...

Page 744: ...tion Reset Value HcRev OHCI_BA 0x000 R Host Controller Revision Register 0x0000_0010 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 RE...

Page 745: ...ote wakeup signal supported this bit is ignored 9 RWC Remote Wakeup Connected This bit indicated whether the HC supports a remote wakeup signal This implementation does not support any such signal The...

Page 746: ...be serviced While processing the Periodic List the Host Controller will check this bit when it finds an isochronous ED 2 PLE Periodic List Enable When set this bit enables processing of the Periodic i...

Page 747: ...t wraps from 11 to 00 15 4 Reserved Reserved 3 OCR Ownership Chang Request When set by software this bit sets the OwnershipChange field in HcInterruptStatus The bit is cleared by software 2 BLF Bulk L...

Page 748: ...OwnershipChangeRequest bit of HcCommandStatus is set 29 7 Reserved Reserved 6 RHSC Root Hub Status Change This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register h...

Page 749: ...ts to be enabled via the specific enable bits listed above 30 OC Ownership Change Enable 0 Ignore 1 Enables interrupt generation due to Ownership Change 29 7 Reserved Reserved 6 RHSC Root Hub Status C...

Page 750: ...hnical Reference Manual Publication Release Date Dec 15 2015 750 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 SO Scheduling Overrun Enable 0 Ignore 1 Enables interrupt generation due to Scheduli...

Page 751: ...disables all interrupts 30 OC Ownership Change Disable 0 Ignore 1 Disables interrupt generation due to Ownership Change 29 7 Reserved Reserved 6 RHSC Root Hub Status Change Disable 0 Ignore 1 Disables...

Page 752: ...nical Reference Manual Publication Release Date Dec 15 2015 752 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 SO Scheduling Overrun Disable 0 Ignore 1 Disables interrupt generation due to Schedul...

Page 753: ...gister HcHCCA Register Offset R W Description Reset Value HcHCCA OHCI_BA 0x018 R W Host Controller Communication Area Register 0x0000_0000 31 30 29 28 27 26 25 24 HCCA 23 22 21 20 19 18 17 16 HCCA 15...

Page 754: ...ter HcPerCED Register Offset R W Description Reset Value HcPerCED OHCI_BA 0x01C R W Host Controller Period Current ED Register 0x0000_0000 31 30 29 28 27 26 25 24 PCED 23 22 21 20 19 18 17 16 PCED 15...

Page 755: ...egister HcCtrHED Register Offset R W Description Reset Value HcCtrHED OHCI_BA 0x020 R W Host Controller Control Head ED Register 0x0000_0000 31 30 29 28 27 26 25 24 CHED 23 22 21 20 19 18 17 16 CHED 1...

Page 756: ...HcCtrCED Register Offset R W Description Reset Value HcCtrCED OHCI_BA 0x024 R W Host Controller Control Current ED Register 0x0000_0000 31 30 29 28 27 26 25 24 CCED 23 22 21 20 19 18 17 16 CCED 15 14...

Page 757: ...D Register HcBlkHED Register Offset R W Description Reset Value HcBlkHED OHCI_BA 0x028 R W Host Controller Bulk Head ED Register 0x0000_0000 31 30 29 28 27 26 25 24 BHED 23 22 21 20 19 18 17 16 BHED 1...

Page 758: ...ister HcBlkCED Register Offset R W Description Reset Value HcBlkCED OHCI_BA 0x02C R W Host Controller Bulk Current ED Register 0x0000_0000 31 30 29 28 27 26 25 24 BCED 23 22 21 20 19 18 17 16 BCED 15...

Page 759: ...Head Register HcDoneH Register Offset R W Description Reset Value HcDoneH OHCI_BA 0x030 R W Host Controller Done Head Register 0x0000_0000 31 30 29 28 27 26 25 24 DH 23 22 21 20 19 18 17 16 DH 15 14...

Page 760: ...FSMPS 23 22 21 20 19 18 17 16 FSMPS 15 14 13 12 11 10 9 8 Reserved FI 7 6 5 4 3 2 1 0 FI Bits Description 31 FIT Frame Interval Toggle This bit is toggled by HCD when it loads a new value into FrameIn...

Page 761: ...erved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved FRT 7 6 5 4 3 2 1 0 FRT Bits Description 31 FR Frame Remaining Toggle Loaded with FrameIntervalToggle when FrameRemaining is loade...

Page 762: ...on Reset Value HcFNum OHCI_BA 0x03C R Host Controller Frame Number Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 FN 7 6 5 4 3 2 1 0 FN Bi...

Page 763: ...on Reset Value HcPerSt OHCI_BA 0x040 R W Host Controller Periodic Start Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved PS 7 6 5 4...

Page 764: ...tten to anything other than 1h but limited adjustment is provided This field should be written to support system implementation This field should always be written to a non zero value 23 13 Reserved R...

Page 765: ...CHNICAL REFERENCE MANUAL 8 PSM Power Switching Mode Global power switching mode implemented in HYDRA 2 This bit is only valid when NoPowerSwitching is cleared This bit should be written 0 0 Global Swi...

Page 766: ...r switching This field is only valid if NoPowerSwitching is cleared and PowerSwitchingMode is set individual port switching When set the port only responds to individual port power switching commands...

Page 767: ...ntIndicator changes Writing a 1 clears this bit Writing a 0 has no effect 16 LPSC Read LocalPowerStatusChange Not supported Always read 0 Write SetGlobalPower Write a 1 issues a SetGlobalPower command...

Page 768: ...mpleted 0 Port reset is not complete 1 Port reset is complete 19 OCIC Port over Current Indicator Change This bit is set when OverCurrentIndicator changes Writing a 1 clears this bit Writing a 0 has n...

Page 769: ...ng a 1 sets PortResetStatus Writing a 0 has no effect 3 POCI Read PortOverCurrentIndicator 2 supports global over current reporting This bit reflects the state of the OVRCUR pin dedicated to this port...

Page 770: ...e When set waits for all USB bus activity to complete prior to returning completion status to the List Processor This is a failsafe mechanism to avoid potential problems with the clk_dr transition bet...

Page 771: ...unctions concerning the handling of messages are implemented in the Message Handler These functions include acceptance filtering the transfer of messages between the CAN Core and the Message RAM and t...

Page 772: ...or serial parallel conversion of messages Message RAM Stores Message Objects and Identifier Masks Registers All registers used to control and to configure the C_CAN Message Handler State Machine that...

Page 773: ...HIGH The Error Management Logic EML counters are unchanged Setting the Init bit does not change any configuration register To initialize the CAN Controller software has to set up the Bit Timing Regist...

Page 774: ...automatic retransmission of frames that have lost arbitration or have been disturbed by errors during transmission The frame transmission service will not be confirmed to the user before the transmiss...

Page 775: ...in Loop Back Mode C_CAN CAN_TX CAN_RX CAN_Core Tx Rx Figure 5 24 3 CAN Core in Loop Back Mode This mode is provided for self test functions To be independent from external stimulation the CAN Core ig...

Page 776: ...message the contents of the shift register is stored into the IF2 Registers without any acceptance filtering Additionally the actual contents of the shift register can be monitored during the message...

Page 777: ...transmitted through the CAN bus The application software reads received messages and updates messages to be transmitted through the IFn Interface Registers Depending on the configuration the applicati...

Page 778: ...ANUAL Message RAM Therefore the data transfer from the IFn Registers to the Message RAM requires a read modify write cycle First those parts of the Message Object that are not to be changed are read f...

Page 779: ...sk Register will be left unchanged Message Transmission 5 24 7 4 If the shift register of the CAN Core cell is ready for loading and if there is no data transfer between the IFn Registers and Message...

Page 780: ...age RAM is reached If a match occurs the scan is stopped and the Message Handler FSM proceeds depending on the type of frame Data Frame or Remote Frame received Reception of Data Frame The Message Han...

Page 781: ...The ID17 ID0 can then be disregarded If the TxIE bit is set the IntPnd bit will be set after a successful transmission of the Message Object If the RmtEn bit is set a matching received Remote Frame wi...

Page 782: ...he received Data Length Code and eight data bytes If the Data Length Code is less than 8 the remaining bytes of the Message Object will be overwritten by unspecified values The Mask Registers Msk28 0...

Page 783: ...atching to a FIFO Buffer are stored into a Message Object of this FIFO Buffer starting with the Message Object with the lowest message number When a message is stored into a Message Object of a FIFO B...

Page 784: ...int to the pending interrupt with the highest priority disregarding their chronological order An interrupt remains pending until the START Read Interrupt Pointer Case Interrupt Pointer 0x8000 else 0x0...

Page 785: ...et The application software has two possibilities to follow the source of a message interrupt First it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Regis...

Page 786: ...o compensate for edge phase errors Sync_Seg Prop_Seg Phase_Seg1 Phase_Seg2 Normal CAN Bit Time 1 Time Quantum tq Sample Point Figure 5 24 7 Bit Timing Parameter Range Remark BRP 1 32 Defines the lengt...

Page 787: ...bit transmitted by node B will arrive at node A after the delay B_to_A Due to oscillator tolerances the actual position of node A s Sample Point can be anywhere inside the nominal range of node A s P...

Page 788: ...is shortened If the magnitude of the phase error is less than SJW Phase_Seg2 is shortened by the magnitude of the phase error else it is shortened by SJW When the magnitude of the phase error of the...

Page 789: ...Sync_Seg Reacting to the early edge Phase_Seg2 is shortened and Sync_Seg is omitted so that the distance from the edge to the Sample Point is the same as it would have been from an Sync_Seg to the Sam...

Page 790: ...ion 1 0 was never implemented in silicon The option to synchronize on edges from dominant to recessive became obsolete only edges from recessive to dominant are considered for synchronization The prot...

Page 791: ...ore instead of values in the range of 1 n values in the range of 0 n 1 are programmed That way e g SJW functional range of 1 4 is represented by only two bits Therefore the length of the bit time is p...

Page 792: ...erations of the following steps First part of the bit time to be defined is the Prop_Seg Its length depends on the delay times measured in the APB clock A maximum bus length as well as a maximum node...

Page 793: ...lay of bus driver 50 ns delay of receiver circuit 30 ns delay of bus line 40m 220 ns tProp 600 ns 6 tq tSJW 100 ns 1 tq tTSeg1 700 ns tProp tSJW tTSeg2 200 ns Information Processing Time 1 tq tSync Se...

Page 794: ...q s 2 tAPB_CLK delay of bus driver 200 ns delay of receiver circuit 80 ns delay of bus line 40m 220 ns tProp 1 q tSJW 4 q tTSeg1 5 Prop tSJW tTSeg2 4 Information Processing Time 3 tq tSync Seg 1 1 tq...

Page 795: ...0x84 R W IFn Command Mask Registers 0x0000_0000 CAN_IF1_MASK1 CAN_IF2_MASK1 CANx_BA 0x28 CANx_BA 0x88 R W IFn Mask 1 Register 0x0000_FFFF CAN_IF1_MASK2 CAN_IF2_MASK2 CANx_BA 0x2C CANx_BA 0x8C R W IFn...

Page 796: ...0x0000_0000 CAN_WU_STATUS CANx_BA 0x16C R W Wake up Function Status 0x0000_0000 Note 1 0x00 0br0000000 where r signifies the actual value of the CAN_RX 2 IFn The two sets of Message Interface Registe...

Page 797: ...eset and the output CAN_TX is set to recessive HIGH The value 0x0001 Init 1 in the CAN Control Register enables the software initialization The C_CAN does not influence the CAN bus until the applicati...

Page 798: ...US Reserved BOff EWarn EPass RxOk TxOk LEC 08h CAN_ERR RP REC6 0 TEC7 0 0Ch CAN_BTIME Res TSeg2 TSeg1 SJW BRP 10h CAN_IIDR IntId15 8 IntId7 0 14h CAN_TEST Reserved Rx Tx1 Tx0 LBack Silent Basic Reserv...

Page 799: ...1 Data 1 Data 0 40h CAN_IF1_DAT_ A2 Data 3 Data 2 44h CAN_IF1_DAT_ B1 Data 5 Data 4 48h CAN_IF1_DAT_ B2 Data 7 Data 6 80h CAN_IF2_CREQ Busy Reserved Message Number 84h CAN_IF2_CMAS K Reserved WR RD Ma...

Page 800: ...AN_TXREQ1 TxRqst16 1 104h CAN_TXREQ2 TxRqst32 17 120h CAN_NDAT1 NewDat16 1 124h CAN_NDAT2 NewDat32 17 140h CAN_IPND1 IntPnd16 1 144h CAN_IPND2 IntPnd32 17 160h CAN_MVLD1 MsgVal16 1 164h CAN_MVLD2 MsgV...

Page 801: ...scription The C_CAN allocates an address space of 256 bytes The registers are organized as 16 bit registers The two sets of interface registers IF1 and IF2 control the software access to the Message R...

Page 802: ...t Timing Register 1 Write access to the Bit Timing Register CAN_BTIME CAN_BRP allowed while Init bit 1 5 DAR Automatic Re transmission Disable Control 0 Automatic Retransmission of disturbed messages...

Page 803: ...Once Init has been cleared by the CPU the device will then wait for 129 occurrences of Bus Idle 129 11 consecutive recessive bits before resuming normal operations At the end of the busoff recovery s...

Page 804: ...passive state as defined in the CAN Specification 4 RxOK Received a Message Successfully 0 No message has been successfully received since this bit was last reset by the CPU This bit is never reset by...

Page 805: ...lue 0 but the monitored Bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceedings o...

Page 806: ...19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RP REC 6 0 7 6 5 4 3 2 1 0 TEC 7 0 Bits Description 31 16 Reserved Reserved 15 RP Receive Error Passive 0 The Receive Error Counter is below the error passi...

Page 807: ...x0F valid values for TSeg1 are 1 15 The actual interpretation by the hardware of this value is such that one more than the value programmed is used 7 6 SJW Re Synchronization Jump Width 0x0 0x3 Valid...

Page 808: ...r chronological order An interrupt remains pending until the application software has cleared it If IntId is different from 0x0000 and IE is set the IRQ interrupt signal to the EIC is active The inter...

Page 809: ...5 Tx 1 0 Tx 1 0 Control of CAN_TX Pin 00 Reset value CAN_TX is controlled by the CAN Core 01 Sample Point can be monitored at CAN_TX pin 10 CAN_TX pin drives a dominant 0 value 11 CAN_TX pin drives a...

Page 810: ...ler Extension Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved BRPE Bits Description 31 4 Reserved Reserve...

Page 811: ...rface Register sets Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command Registers The Command Mask Register specifies the direction of the data transfe...

Page 812: ...ssage Number Message Number 0x01 0x20 Valid Message Number the Message Object in the Message RAM is selected for data transfer 0x00 Not a valid Message Number interpreted as 0x20 0x21 0x3F Not a valid...

Page 813: ...n 31 8 Reserved Reserved 7 WR RD Write Read 0 Read Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers 1 Write Transfer data from...

Page 814: ...ask Register bit TxRqst in the IFn Message Control Register will be ignored Access New Data Bit when Direction Read 0 NewDat bit remains unchanged 1 Clear NewDat bit in the Message Object Note A read...

Page 815: ...28 0x88 R W IFn Mask 1 Registers 0x0000_FFFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Msk 15 8 7 6 5 4 3 2 1 0 Msk 7 0 Bits Description 31 16 Reserved Re...

Page 816: ...e acceptance filtering 1 The extended identifier bit IDE is used for acceptance filtering Note When 11 bit standard Identifiers are used for a Message Object the identifiers of received Data Frames ar...

Page 817: ...W Description Reset Value CAN_IFn_ARB1 CANx_BA 0x30 0x90 R W IFn Arbitration 1 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 ID 15 8 7 6...

Page 818: ...ets bit Init in the CAN Control Register This bit must also be reset before the identifier Id28 0 the control bits Xtd Dir or the Data Length Code DLC3 0 are modified or if the Messages Object is no l...

Page 819: ...ost since last time this bit was reset by the CPU 1 The Message Handler stored a new message into this object when NewDat was still set the CPU has lost a message 13 IntPnd Interrupt Pending 0 This me...

Page 820: ...Frame has 0 8 data bytes 9 15 Data Frame has 8 data bytes Note The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other...

Page 821: ...t R W Description Reset Value CAN_IFn_DAT_A1 CANx_BA 0x3C 0x9C R W IFn Data A1 Registers 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 1 7 6...

Page 822: ...set R W Description Reset Value CAN_IFn_DAT_A2 CANx_BA 0x40 0xA0 R W IFn Data A2 Registers 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 3 7...

Page 823: ...set R W Description Reset Value CAN_IFn_DAT_B1 CANx_BA 0x44 0xA4 R W IFn Data B1 Registers 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 5 7...

Page 824: ...isters 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Data 7 7 6 5 4 3 2 1 0 Data 6 Bits Description 31 16 Reserved Reserved 15 8 Data 7 Data Byte...

Page 825: ...a Message Object in the Message Memory The Arbitration Registers ID28 0 Xtd and Dir are used to define the identifier and type of outgoing messages and are used together with the mask registers Msk28...

Page 826: ...e IFn Message Interface Registers or by the Message Handler after reception of a Remote Frame or after a successful transmission Register Offset R W Description Reset Value CAN_TXREQ1 CANx_BA 0x100 R...

Page 827: ...ransmission Request Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 TxRqst32 25 7 6 5 4 3 2 1 0 TxRqst24 17 Bits Description 31 16 Reserv...

Page 828: ...reception of a Data Frame or after a successful transmission Register Offset R W Description Reset Value CAN_NDAT1 CANx_BA 0x120 R New Data Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23...

Page 829: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 NewData 32 25 7 6 5 4 3 2 1 0 NewData 24 17 Bits Description 31 16 Reserved Reserved 15 0 NewData 32 17 New Data Bits 32 17 of All Message Objec...

Page 830: ...essage Interface Registers or by the Message Handler after reception or after a successful transmission of a frame This will also affect the value of IntId in the Interrupt Register Register Offset R...

Page 831: ...IPND2 CANx_BA 0x144 R Interrupt Pending Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 IntPnd 32 25 7 6 5 4 3 2 1 0 IntPnd 24 17 Bits De...

Page 832: ...Interface Registers Register Offset R W Description Reset Value CAN_MVLD1 CANx_BA 0x160 R Message Valid Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14...

Page 833: ...5 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 MsgVal 32 25 7 6 5 4 3 2 1 0 MsgVal 24 17 Bits Description 31 16 Reserved Reserved 15 0 MsgVal 32 17 Message Valid Bits 32 17 of Al...

Page 834: ...U_EN CANx_BA 0x168 R W Wake up Enable Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WAKUP_EN Bi...

Page 835: ...cription Reset Value CAN_WU_STATUS CANx_BA 0x16C R W Wake up Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1...

Page 836: ...rt eMMC and NAND type flash and the FMI is cooperated with DMAC to provide a fast data transfer between system memory and cards 5 25 2 Features Support single DMA channel and address in non word bound...

Page 837: ...ted pin configuration please refer to the register SYS_MFP_GPBL SYS_MFP_GPCL SYS_MFP_GPCH SYS_MFP_GPGL SYS_MFP_GPIL and SYS_MFP_GPIH to know how to configure related pins as the NAND eMMC function Set...

Page 838: ...face Controller FMI 5 25 5 2 The Flash Memory Interface supports eMMC and NAND type flash FMI is cooperated with DMAC to provide a fast data transfer between system memory and cards There is a single...

Page 839: ...s triggered eMMC controller will receive response R2 136 bits from eMMC device CRC 7 and end bit will be dropped The receiving data will be placed at DMAC s buffer starting from address offset 0x0 Thi...

Page 840: ...hm can correct up to 4 bits errors 8 bits errors 12 bits errors 15 bits errors or 24 bits errors By reading ECC_FLD_IF FMI_NANDINTSTS 2 to check the error occurrence while by reading FMI_NANDECCES0 FM...

Page 841: ...es Redundant Area 64 Bytes Redundant Data Parity Data Redundant Area FMI_NANDRA0 FMI_NANDRA15 Figure 5 25 2 Data Arrangement for 2 kB Page Size NAND Flash Data Area 4096 Bytes Redundant Area Defined b...

Page 842: ...te Dec 15 2015 842 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Data Area 8192 Bytes Redundant Area Defined by FMI_NANDRACTL Redundant Data Parity Data Redundant Area FMI_NANDRA0 FMI_NANDRAx Figur...

Page 843: ...MI_BA 0x824 R W eMMC Command Argument Register 0x0000_0000 FMI_EMMCINTEN FMI_BA 0x828 R W eMMC Interrupt Enable Register 0x0000_0000 FMI_EMMCINTST S FMI_BA 0x82C R W eMMC Interrupt Status Register 0x0...

Page 844: ...Error Byte Address 3 Register 0x0000_0000 FMI_NANDECCE A4 FMI_BA 0x910 R NAND Flash ECC Error Byte Address 4 Register 0x0000_0000 FMI_NANDECCE A5 FMI_BA 0x914 R NAND Flash ECC Error Byte Address 5 Reg...

Page 845: ...se Date Dec 15 2015 845 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL FMI_NANDECCE D5 FMI_BA 0x974 R NAND Flash ECC Error Data Register 5 0x8080_8080 FMI_NANDRAn n 0 1 117 FMI_BA 0xA00 0x4 n R W NA...

Page 846: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 846 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 25 7 Register Description...

Page 847: ...for FMI Enable DMA scatter gather function or not 0 Normal operation DMAC will treat the starting address in FMI_DMASA as starting pointer of a single block memory 1 Enable scatter gather operation DM...

Page 848: ...d will be interpreted as a starting address of Physical Address Descriptor PAD table 0 ORDER Determined to the PAD Table Fetching Is in Order or Out of Order 0 PAD table is fetched in order 1 PAD tabl...

Page 849: ...eched next PAD tables sequentially if ORDER FMI_DMASA 0 set as low FMI fetehced next PAD tables based on the Next Descriptor Physical Base Address of PAD table if ORDER FMI_DMASA 0 set as high PAD Tab...

Page 850: ...e FMI_DMABCNT FMI_BA 0x40C R FMI DMA Transfer Byte Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved BCNT 23 22 21 20 19 18 17 16 BCNT 15 14 13 12 11 10 9 8 BCNT 7 6 5 4 3 2 1 0 BCNT Bits De...

Page 851: ...24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WEOT_IE TABORT_IE Bits Description 31 2 Reserved Reserved 1 WEOT_IE Wrong EOT Encountered Interrupt...

Page 852: ...transfer finished that means the total sector count of all PAD is less than the sector count of FMI this bit will be set 0 No EOT encountered before DMA transfer finished 1 EOT encountered before DMA...

Page 853: ..._EN SW_RST Bits Description 31 4 Reserved Reserved 3 NAND_EN NAND Flash Functionality Enable 0 Disable NAND flash functionality of FMI 1 Enable NAND flash functionality of FMI 2 Reserved Reserved 1 eM...

Page 854: ...I_INTEN FMI_BA 0x804 R W FMI Interrupt Enable Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTA_IE Bits...

Page 855: ...11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTA_IF Bits Description 31 1 Reserved Reserved 0 DTA_IF DMAC READ WRITE Target Abort Interrupt Flag Read Only This bit indicates DMAC received an ERROR res...

Page 856: ...K_CNT Block Counts to Be Transferred or Received This field contains the block counts for data in and data out transfer For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command using this function to...

Page 857: ...rite 0 to this bit the controller will be abnormal 3 DO_EN Data Output Enable 0 No effect Please use SW_RST FMI_EMMCCTL 14 to clear this bit 1 Enable eMMC host will transfer block data and the CRC 16...

Page 858: ...D FMI_BA 0x824 R W eMMC Command Argument Register 0x0000_0000 31 30 29 28 27 26 25 24 CMDARG 23 22 21 20 19 18 17 16 CMDARG 15 14 13 12 11 10 9 8 CMDARG 7 6 5 4 3 2 1 0 CMDARG Bits Description 31 0 CM...

Page 859: ...rrupts generation of eMMC controller when data input time out Time out value is specified at FMI_EMMCTMOUT 0 Disable 1 Enable 12 RITO_IE Response Time out Interrupt Enable Enable Disable interrupts ge...

Page 860: ...en receiving data waiting start bit 0 Not time out 1 Data input time out NOTE This bit is read only but can be cleared by writing 1 to it 12 RITO_IF Response Time out Interrupt Flag Read Only This bit...

Page 861: ...esponse in data in or data out CRC status error transfer When CRC error is occurred it s necessary to reset eMMC engine Some response ex R3 doesn t have CRC 7 information with it However eMMC host wil...

Page 862: ...0 FMI_BA 0x830 R eMMC Receiving Response Token Register 0 0x0000_0000 31 30 29 28 27 26 25 24 RESPONSE 23 22 21 20 19 18 17 16 RESPONSE 15 14 13 12 11 10 9 8 RESPONSE 7 6 5 4 3 2 1 0 RESPONSE Bits Des...

Page 863: ...0x834 R eMMC Receiving Response Token Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 RESPONSE Bits Description...

Page 864: ...838 R W eMMC Block Length Register 0x0000_01FF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved BLK_LENGTH 7 6 5 4 3 2 1 0 BLK_LENGTH Bits Description 3...

Page 865: ...18 17 16 TIMEOUT 15 14 13 12 11 10 9 8 TIMEOUT 7 6 5 4 3 2 1 0 TIMEOUT Bits Description 31 24 Reserved Reserved 23 0 TIMEOUT eMMC Response Data in Time out Value A 24 bit value specifies the time out...

Page 866: ...hip Select 1 Enable 0 Chip select 1 enable 1 Chip select 1 disable 25 CS0 NAND Flash Chip Select 0 Enable 0 Chip select 0 enable 1 Chip select 0 disable 24 Reserved Reserved 23 ECC_EN ECC Algorithm En...

Page 867: ...ot be cleared This bit will be auto cleared after few clock cycles 8 PROT_3BEN Protect_3Byte Software Data Enable The ECC algorithm only protects data area and hardware ECC parity code User can choose...

Page 868: ...me buffer into NAND Flash or NAND type flash 0 No effect 1 Enable DMA write data transfer NOTE When DMA transfer completed this bit will be cleared automatically 1 DRD_EN DMA Read Data Enable This bit...

Page 869: ...time can be calculated using following equation tCLS CALE_SH 1 TAHB tCLH CALE_SH 2 2 TAHB tALS CALE_SH 1 TAHB tALH CALE_SH 2 2 TAHB 15 8 HI_WID Read Write Enable Signal High Pulse Width This field co...

Page 870: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 870 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Timing Controlled by FMI_NANDTMCTL Register...

Page 871: ...R B rising edge detect interrupt generation 10 RB0_IE Ready Busy Rising Edge Detect Interrupt Enable 0 Disable R B rising edge detect interrupt generation 1 Enable R B rising edge detect interrupt ge...

Page 872: ...he Ready Busy pin status of NAND Flash 18 RB0_Status Ready Busy 0 Pin Status Read Only This bit reflects the Ready Busy pin status of NAND Flash 17 12 Reserved Reserved 11 RB1_IF Ready Busy 1 Rising E...

Page 873: ...field 512bytes of data transfer Read this bit to check if the error occurred 0 No occurrence of ECC error 1 Occurrence of ECC error NOTE This bit is read only but can be cleared by writing 1 to it 1 R...

Page 874: ...er Offset R W Description Reset Value FMI_NANDCM D FMI_BA 0x8B0 W NAND Flash Command Port Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 R...

Page 875: ...14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADDRESS Bits Description 31 EOA End of Address Writing this bit to indicate if this address is the last one or not By writing address port with this bit lo...

Page 876: ...AND Flash Data Port Register 0xXXXX_XXXX 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DATA Bits Description 31 8 Reserved Reserved 7...

Page 877: ...and write out FF to NAND ECC parity for 512 Bytes page size or 2K 4K 8K page size first 512 field 0x02 Mask ECC parity and write out FF to NAND ECC parity for 512 Bytes page size or 2K 4K 8K page size...

Page 878: ...sh Extend Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WP Bits Description 31 1 Reserved Reser...

Page 879: ...For this ECC core BCH algorithm only when F4_STAT equals to 0x01 the value in this field is meaningful F4_ECNT means how many errors depending on which ECC is used 25 24 F4_STAT ECC Status of Field 4...

Page 880: ...f Field 2 This field contains the ECC correction status BCH algorithm of ECC field 2 00 No error 01 Correctable error 10 Uncorrectable error 11 Reserved 7 Reserved Reserved 6 2 F1_ECNT Error Count of...

Page 881: ...For this ECC core BCH algorithm only when F8_STAT equals to 0x01 the value in this field is meaningful F8_ECNT means how many errors depending on which ECC is used 25 24 F8_STAT ECC Status of Field 8...

Page 882: ...of Field 6 This field contains the ECC correction status BCH algorithm of ECC field 6 00 No error 01 Correctable error 10 Uncorrectable error 11 Reserved 7 Reserved Reserved 6 2 F5_ECNT Error Count of...

Page 883: ...r this ECC core BCH algorithm only when F12_STAT equals to 0x01 the value in this field is meaningful F12_ECNT means how many errors depending on which ECC is used 25 24 F12_STAT ECC Status of Field 1...

Page 884: ...of Field 10 This field contains the ECC correction status BCH algorithm of ECC field 10 00 No error 01 Correctable error 10 Uncorrectable error 11 Reserved 7 Reserved Reserved 6 2 F9_ECNT Error Count...

Page 885: ...or this ECC core BCH algorithm only when F16_STAT equals to 0x01 the value in this field is meaningful F16_ECNT means how many errors depending on which ECC is used 25 24 F16_STAT ECC Status of Field...

Page 886: ...Field 14 This field contains the ECC correction status BCH algorithm of ECC field 14 00 No error 01 Correctable error 10 Uncorrectable error 11 Reserved 7 Reserved Reserved 6 2 F13_ECNT Error Count of...

Page 887: ...0 FMI_BA 0x8E0 R W NAND Flash Protect Region End Address 0 Register 0x0000_0000 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 7 6 5 4 3 2 1 0 ADDR Bits Descripti...

Page 888: ...W NAND Flash Protect Region End Address 1 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 ADDR Bits Description 31...

Page 889: ...15 14 13 12 11 10 9 8 Reserved ERR_ADDR0 7 6 5 4 3 2 1 0 ERR_ADDR0 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR1 ECC Error Address First Field of Error 1 This field contains an 11 bit ECC...

Page 890: ...15 14 13 12 11 10 9 8 Reserved ERR_ADDR2 7 6 5 4 3 2 1 0 ERR_ADDR2 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR3 ECC Error Address First Field of Error 3 This field contains an 11 bit ECC e...

Page 891: ...15 14 13 12 11 10 9 8 Reserved ERR_ADDR4 7 6 5 4 3 2 1 0 ERR_ADDR4 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR5 ECC Error Address First Field of Error 5 This field contains an 11 bit ECC...

Page 892: ...5 14 13 12 11 10 9 8 Reserved ERR_ADDR6 7 6 5 4 3 2 1 0 ERR_ADDR6 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR7 ECC Error Address First Field of Error 7 This field contains an 11 bit ECC er...

Page 893: ...15 14 13 12 11 10 9 8 Reserved ERR_ADDR8 7 6 5 4 3 2 1 0 ERR_ADDR8 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR9 ECC Error Address First Field of Error 9 This field contains an 11 bit ECC...

Page 894: ...4 13 12 11 10 9 8 Reserved ERR_ADDR10 7 6 5 4 3 2 1 0 ERR_ADDR10 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR11 ECC Error Address First Field of Error 11 This field contains an 11 bit ECC e...

Page 895: ...14 13 12 11 10 9 8 Reserved ERR_ADDR12 7 6 5 4 3 2 1 0 ERR_ADDR12 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR13 ECC Error Address First Field of Error 13 This field contains an 11 bit ECC...

Page 896: ...4 13 12 11 10 9 8 Reserved ERR_ADDR14 7 6 5 4 3 2 1 0 ERR_ADDR14 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR15 ECC Error Address First Field of Error 15 This field contains an 11 bit ECC e...

Page 897: ...14 13 12 11 10 9 8 Reserved ERR_ADDR16 7 6 5 4 3 2 1 0 ERR_ADDR16 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR17 ECC Error Address First Field of Error 17 This field contains an 11 bit ECC...

Page 898: ...4 13 12 11 10 9 8 Reserved ERR_ADDR18 7 6 5 4 3 2 1 0 ERR_ADDR18 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR19 ECC Error Address First Field of Error 19 This field contains an 11 bit ECC e...

Page 899: ...5 14 13 12 11 10 9 8 Reserved ERR_ADDR20 7 6 5 4 3 2 1 0 ERR_ADDR20 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR21 ECC Error Address First Field of Error 21 This field contains an 11 bit EC...

Page 900: ...14 13 12 11 10 9 8 Reserved ERR_ADDR22 7 6 5 4 3 2 1 0 ERR_ADDR22 Bits Description 31 27 Reserved Reserved 26 16 ERR_ADDR23 ECC Error Address First Field of Error 23 This field contains an 11 bit ECC...

Page 901: ...23 16 ERR_DATA2 ECC Error Data of First Field 2 This field contains an 8 bit BCH ECC error data 2 of first field If it is a correctable error please read out the error data in this field and doing bit...

Page 902: ...23 16 ERR_DATA6 ECC Error Data of First Field 6 This field contains an 8 bit BCH ECC error data 6 of first field If it is a correctable error please read out the error data in this field and doing bit...

Page 903: ...23 16 ERR_DATA10 ECC Error Data of First Field 10 This field contains an 8 bit BCH ECC error data 10 of first field If it is a correctable error please read out the error data in this field and doing...

Page 904: ...16 ERR_DATA14 ECC Error Data of First Field 14 This field contains an 8 bit BCH ECC error data 14 of first field If it is a correctable error please read out the error data in this field and doing bi...

Page 905: ...16 ERR_DATA18 ECC Error Data of First Field 18 This field contains an 8 bit BCH ECC error data 18 of first field If it is a correctable error please read out the error data in this field and doing bi...

Page 906: ...16 ERR_DATA22 ECC Error Data of First Field 22 This field contains an 8 bit BCH ECC error data 22 of first field If it is a correctable error please read out the error data in this field and doing bit...

Page 907: ...of SD SDHC SDIO The SDH controller supports SD SDHC SDIO card and cooperates with DMAC to provide a fast data transfer between system memory and cards 5 26 2 Features Supports single DMA channel Supp...

Page 908: ..._DMACTL 0 to enable DMACand SGEN SDH_DMACTL 3 to enable Scatter Gather function 2 Fill corresponding starting address of Physical Address Descriptor PAD table in SDH_DMASA 3 When bit 0 of SDH_DMASA is...

Page 909: ...2_EN SDH_CTL 4 and then CLK8_OE SDH_CTL 6 Please note that RI_EN SDH_CTL 1 and R2_EN SDH_CTL 4 can t be triggered at the same time For data part there are DI_EN SDH_CTL 2 and DO_EN SDH_CTL 3 for choos...

Page 910: ...r 0x0000_0000 SDH_GCTL SDH_BA 0x800 R W SD Host Global Control and Status Register 0x0000_0000 SDH_GINTEN SDH_BA 0x804 R W SD Host Global Interrupt Control Register 0x0000_0001 SDH_GINTSTS SDH_BA 0x80...

Page 911: ...ress 8 4 Reserved Reserved 3 SGEN Scatter gather Function Enable 0 Scatter gather function Disabled DMA will treat the starting address in SDH_DMASA as starting pointer of a single block memory 1 Scat...

Page 912: ...Address Descriptor PAD table 0 ORDER Determined to the PAD Table Fetching Is in Order or Out of Order 0 PAD table is fetched in order 1 PAD table is fetched out of order Note the bit 0 is valid in sc...

Page 913: ...SDH_DMASA 0 set as low SDH fetehced next PAD tables based on the Next Descriptor Physical Base Address of PAD table if ORDER SDH_DMASA 0 set as high PAD Table 1 System Memory ORDER 0 PAD Table 2 PAD T...

Page 914: ...e SDH_DMABCNT SDH_BA 0x40C R SD Host DMA Transfer Byte Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved BCNT 23 22 21 20 19 18 17 16 BCNT 15 14 13 12 11 10 9 8 BCNT 7 6 5 4 3 2 1 0 BCNT Bit...

Page 915: ...0 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved WEOT_IE TABORT_IE Bits Description 31 2 Reserved Reserved 1 WEOT_IE Wrong EOT End of Transfer Encountered Interrupt Enabl...

Page 916: ...iptor is encountered before DMA transfer finished that means the total sector count of all PAD is less than the sector count of FMI this bit will be set 0 No EOT encountered before DMA transfer finish...

Page 917: ...31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved SDEN GCTLRST Bits Description 31 2 Reserved Reserved 1 SDEN Secure digital Fu...

Page 918: ...H_GINTEN SDH_BA 0x804 R W SD Host Global Interrupt Control Register 0x0000_0001 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserve...

Page 919: ...15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved DTA_IF Bits Description 31 1 Reserved Reserved 0 DTA_IF DMAC READ WRITE Target Abort Interrupt Flag Read Only This bit indicates DMA received a...

Page 920: ...NWR Parameter for Block Write Operation This value indicates the NWR parameter for data block write operation in SD clock counts The actual clock cycle will be SDNWR 1 23 16 BLK_CNT Block Counts to Be...

Page 921: ...response data into DMAC s flash buffer exclude CRC 7 NOTE When operation is finished this bit will be cleared automatically so don t write 0 to this bit the controller will be abnormal 3 DO_EN Data Ou...

Page 922: ...A 0x824 R W SD Host Command Argument Register 0x0000_0000 31 30 29 28 27 26 25 24 SD_CMD_ARG 23 22 21 20 19 18 17 16 SD_CMD_ARG 15 14 13 12 11 10 9 8 SD_CMD_ARG 7 6 5 4 3 2 1 0 SD_CMD_ARG Bits Descrip...

Page 923: ...1 From SD port 1 card detection pin the pin SD1_nCD 30 CD0SRC SD Port 0 Card Detect Source Selection 0 From SD port 0 data bit 3 the pin SD0_DAT3 Host need clock to got data on pin SD0_DAT3 Please mak...

Page 924: ...inserted or removed 0 Disable 1 Enable 8 CD0_IE SD0 Card Detection Interrupt Enable Enable Disable interrupts generation of SD controller when card 0 is inserted or removed 0 Disable 1 Enable 7 2 Rese...

Page 925: ...tus of SD port 0 17 CDPS1 Card Detect Status of SD1 Read Only This bit is the card detect pin status of SD1 and it is using for card detection When there is a card inserted in or removed from SD1 soft...

Page 926: ...ost This interrupt is designed to level sensitive Before clear it turn off SDIO0_IE SDH_INTEN 10 first 0 No interrupt is issued by SDIO card 0 1 an interrupt is issued by SDIO card 0 NOTE This bit is...

Page 927: ...ring response in data in or data out CRC status error transfer When CRC error is occurred software should reset SD engine Some response ex R3 doesn t have CRC 7 information with it SD host will still...

Page 928: ...DH_BA 0x830 R SD Host Receiving Response Token Register 0 0x0000_0000 31 30 29 28 27 26 25 24 SD_RSP_TK0 23 22 21 20 19 18 17 16 SD_RSP_TK0 15 14 13 12 11 10 9 8 SD_RSP_TK0 7 6 5 4 3 2 1 0 SD_RSP_TK0...

Page 929: ...SP1 SDH_BA 0x834 R SD Host Receiving Response Token Register 1 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 SD_RSP_TK1 B...

Page 930: ...H_BA 0x838 R W SD Host Block Length Register 0x0000_01FF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved BLKLEN 7 6 5 4 3 2 1 0 BLKLEN Bits Description...

Page 931: ...1 20 19 18 17 16 TMOUT 15 14 13 12 11 10 9 8 TMOUT 7 6 5 4 3 2 1 0 TMOUT Bits Description 31 24 Reserved Reserved 23 0 TMOUT SD Response Data in Time out Value A 24 bit value specifies the time out co...

Page 932: ...erved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved PWROFF1 PWROFF0 Bits Description 31 2 Reserved Reserved 1 PWROFF1 SD Port 1 Power Disable Set this bit lo...

Page 933: ...ption decryption algorithm The DES TDES accelerator supports ECB CBC CFB OFB and CTR mode The SHA accelerator is an implementation fully compliant with the SHA 160 SHA 224 SHA 256 SHA 384 and SHA 512...

Page 934: ...0 2 Supports HMAC SHA 160 HMAC SHA 224 HMAC SHA 256 HMAC SHA 384 and HMAC SHA 512 5 27 3 Block Diagram Figure 5 27 1 Cryptographic Accelerator Block Diagram 5 27 4 Basic Configuration Before using cry...

Page 935: ...A mode Once DMA source address register destination address register and byte count register are configurated by CPU moving data from and to accelerator is done by DMA logic totally This mode can off...

Page 936: ...he chip powers up 3 Configure PRNG control register CRPT_PRNG_CTL 4 Software checks BUSY CRPT_PRNG_CTL 8 until it comes to 0 or waits for the PRNG done interrupt must enable the corresponding interrup...

Page 937: ...iven key If this property is undesirable in a particular application the ECB mode should not be used Cipher Block Chaining Mode The Cipher Block Chaining CBC mode is a confidentiality mode whose encry...

Page 938: ...CFB The Cipher Feedback CFB mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are...

Page 939: ...vice versa The OFB mode requires that the IV is a nonce i e the IV must be unique for each execution of the mode under the given key The OFB mode requires a unique IV for every message that is ever e...

Page 940: ...the forward cipher to a set of input blocks called counters to produce a sequence of output blocks that are exclusive ORed with the plaintext to produce the ciphertext and vice versa The sequence of...

Page 941: ...1 30 NUC970 TECHNICAL REFERENCE MANUAL Figure 5 27 7 Counter Mode CBC Ciphertext Stealing 1 Mode CBC CS1 The figure below illustrates the CBC CS1 Encrypt algorithm for the case that Pn is a partial bl...

Page 942: ...UAL Figure 5 27 8 CBC CS1 Encryption The figure below illustrates the CBC CS1 Decrypt algorithm for the case that Cn 1 is a partial block Figure 5 27 9 CBC CS1 Decryption CBC Ciphertext Stealing 2 Mod...

Page 943: ...ption decryption 11 Waits for the AES interrupt flag AESIF CRPT_INTSTS 0 be set 12 Read output data from DMA destination address with selected DMA byte count 13 Repeat step 9 to step 12 until all data...

Page 944: ...n_KEY3L where n is the selected channel number 4 Program initial vector to registers CRPT_TDESn_IVH and CRPT_TDESn_IVL 5 Configure TDES control register CRPT_TDES_CTL for channel selection encryption...

Page 945: ...is a specific construction for calculating a message authentication code involving a cryptographic hash function in combination with a secret cryptographic key Any cryptographic hash function such as...

Page 946: ...data input request DATINREQ CRPT_HMAC_STS 16 be set 5 Write one word of input data to CRPT_HMAC_DATIN 6 Repeat step 2 to 5 until all inut words are written into SHA engine 7 Waits for the BUSY CRPT_HM...

Page 947: ...050 R AES Engine Output Feedback Data after Cryptographic Operation 0x0000_0000 CRPT_AES_FDBCK1 CRYP_BA 0x054 R AES Engine Output Feedback Data after Cryptographic Operation 0x0000_0000 CRPT_AES_FDBCK...

Page 948: ...3 Register for Channel 1 0x0000_0000 CRPT_AES1_KEY4 CRYP_BA 0x15C R W AES Key Word 4 Register for Channel 1 0x0000_0000 CRPT_AES1_KEY5 CRYP_BA 0x160 R W AES Key Word 5 Register for Channel 1 0x0000_0...

Page 949: ...0x1DC R W AES Key Word 6 Register for Channel 3 0x0000_0000 CRPT_AES3_KEY7 CRYP_BA 0x1E0 R W AES Key Word 7 Register for Channel 3 0x0000_0000 CRPT_AES3_IV0 CRYP_BA 0x1E4 R W AES Initial Vector Word 0...

Page 950: ..._TDES1_IVH CRYP_BA 0x260 R W TDES DES Initial Vector High Word Register for Channel 1 0x0000_0000 CRPT_TDES1_IVL CRYP_BA 0x264 R W TDES DES Initial Vector Low Word Register for Channel 1 0x0000_0000 C...

Page 951: ...TDES DES Byte Count Register for Channel 3 0x0000_0000 CRPT_HMAC_CTL CRYP_BA 0x300 R W SHA HMAC Control Register 0x0000_0000 CRPT_HMAC_STS CRYP_BA 0x304 R SHA HMAC Status Flag 0x0000_0000 CRPT_HMAC_DG...

Page 952: ...UC970 TECHNICAL REFERENCE MANUAL CRPT_HMAC_SADDR CRYP_BA 0x34C R W SHA HMAC DMA Source Address Register 0x0000_0000 CRPT_HMAC_DMACNT CRYP_BA 0x350 R W SHA HMAC Byte Count Register 0x0000_0000 CRPT_HMA...

Page 953: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 953 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 27 7 Register Description Crypto Register 5 27 7 1...

Page 954: ...upt Enable Control 0 SHA HMAC interrupt Disabled 1 SHA HMAC interrupt Enabled In DMA mode an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA HMAC engine In Non...

Page 955: ...rol 0 AES error interrupt flag Disabled 1 AES error interrupt flag Enabled 0 AESIEN AES Interrupt Enable Control 0 AES interrupt Disabled 1 AES interrupt Enabled In DMA mode an interrupt will be trigg...

Page 956: ...gister This bit is cleared by writing 1 and it has no effect by writing 0 0 No SHA HMAC error 1 SHA HMAC error interrupt 24 HMACIF SHA HMAC Finish Interrupt Flag This bit is cleared by writing 1 and i...

Page 957: ...by writing 0 0 No TDES DES interrupt 1 TDES DES encryption decryption done interrupt 7 2 Reserved Reserved 1 AESEIF AES Error Flag This bit is cleared by writing 1 and it has no effect by writing 0 0...

Page 958: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 958 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL PRNG Register 5 27 7 2...

Page 959: ...USY 7 6 5 4 3 2 1 0 Reserved KEYSZ SEEDRLD START Bits Description 31 9 Reserved Reserved 8 BUSY PRNG Busy Read Only 0 PRNG engine is idle 1 Indicate that the PRNG engine is generating CRPT_PRNG_KEYx 7...

Page 960: ...G Seed Register CRPT_PRNG_SEED Register Offset R W Description Reset Value CRPT_PRNG_SEED CRYP_BA 0x00C W Seed for PRNG Undefined 31 30 29 28 27 26 25 24 SEED 23 22 21 20 19 18 17 16 SEED 15 14 13 12...

Page 961: ...18 R PRNG Generated Key2 Undefined CRPT_PRNG_KEY3 CRYP_BA 0x01C R PRNG Generated Key3 Undefined CRPT_PRNG_KEY4 CRYP_BA 0x020 R PRNG Generated Key4 Undefined CRPT_PRNG_KEY5 CRYP_BA 0x024 R PRNG Generat...

Page 962: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 962 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL AES Register 5 27 7 3...

Page 963: ...UNPRT And the key content would be cleared as well 30 26 KEYUNPRT Unprotect Key Writing 0 to CRPT_AES_CTL 31 and 10110 to CRPT_AES_CTL 30 26 is to unprotect the AES key The KEYUNPRT can be read and wr...

Page 964: ...h Cascade Mode 0 DMA cascade function Disabled 1 In DMA cascade mode software can update DMA source address register destination address register and byte count register during a cascade operation wit...

Page 965: ...than 8 words It writes 8 words to Inputbuffer 5 R8 The amount of output data in output buffer is more than 8 words It reads 8 words out 6 W4 The amount of data in Inbuffer is less than 12 words and t...

Page 966: ...engine 19 Reserved Reserved 18 OUTBUFERR AES Out Buffer Error Flag 0 No error 1 Error happens during getting the result from AES engine 17 OUTBUFFULL AES Out Buffer Full Flag 0 AES output buffer is no...

Page 967: ...d the data into the AES engine 1 AES input buffer is full Software cannot feed data to the AES engine Otherwise the flag INBUFERR will be set to 1 8 INBUFEMPTY AES Input Buffer Empty 0 There are some...

Page 968: ...Offset R W Description Reset Value CRPT_AES_DATIN CRYP_BA 0x108 R W AES Engine Data Input Port Register 0x0000_0000 31 30 29 28 27 26 25 24 DATIN 23 22 21 20 19 18 17 16 DATIN 15 14 13 12 11 10 9 8 D...

Page 969: ...R W Description Reset Value CRPT_AES_DATOUT CRYP_BA 0x10C R AES Engine Data Output Port Register 0x0000_0000 31 30 29 28 27 26 25 24 DATOUT 23 22 21 20 19 18 17 16 DATOUT 15 14 13 12 11 10 9 8 DATOUT...

Page 970: ...0x160 R W AES Key Word 5 Register for Channel 1 0x0000_0000 CRPT_AES1_KEY6 CRYP_BA 0x164 R W AES Key Word 6 Register for Channel 1 0x0000_0000 CRPT_AES1_KEY7 CRYP_BA 0x168 R W AES Key Word 7 Register...

Page 971: ...y key for AES accelerator can be 128 192 or 256 bits and four six or eight 32 bit registers are to store each security key CRPT_AESn_KEY3 CRPT_AESn_KEY2 CRPT_AESn_KEY1 CRPT_AESn_KEY0 stores the 128 bi...

Page 972: ...l 1 0x0000_0000 CRPT_AES2_IV0 CRYP_BA 0x1A8 R W AES Initial Vector Word 0 Register for Channel 2 0x0000_0000 CRPT_AES2_IV1 CRYP_BA 0x1AC R W AES Initial Vector Word 1 Register for Channel 2 0x0000_000...

Page 973: ...0 9 8 SADDR 7 6 5 4 3 2 1 0 SADDR Bits Description 31 0 SADDR AES DMA Source Address The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO The SA...

Page 974: ...5 4 3 2 1 0 DADDR Bits Description 31 0 DADDR AES DMA Destination Address The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO The DADDR keeps...

Page 975: ...Sn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode The CRPT_AESn_CNT is 32 bit and the maximum of byte count is 4G bytes CRPT_AESn_CNT can be read and written...

Page 976: ...e Output Feedback Data after Cryptographic Operation 0x0000_0000 31 30 29 28 27 26 25 24 FDBCK 23 22 21 20 19 18 17 16 FDBCK 15 14 13 12 11 10 9 8 FDBCK 7 6 5 4 3 2 1 0 FDBCK Bits Description 31 0 FDB...

Page 977: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 977 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL TDES DES Register 5 27 7 4...

Page 978: ...cleared by asserting KEYUNPRT The key content would be cleared as well 30 26 KEYUNPRT Unprotect Key Writing 0 to CRPT_TDES_CTL 31 and 10110 to CRPT_TDES_CTL 30 26 is to unprotect TDES key The KEYUNPRT...

Page 979: ...operates in Non DMA mode and get data from the port CRPT_TDES_DATIN 1 TDES_DMA engine Enabled TDES engine operates in DMA mode and data movement from to the engine is done by DMA logic 6 DMACSCAD TDE...

Page 980: ...al Publication Release Date Dec 15 2015 980 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 START TDES DES Engine Start 0 No effect 1 Start TDES DES engine The flag BUSY would be set Note The bit i...

Page 981: ...DES DES engine 19 Reserved Reserved 18 OUTBUFERR TDES DES Out Buffer Error Flag 0 No error 1 Error happens during getting test result from TDES DES engine 17 OUTBUFFULL TDES DES Output Buffer Full Fla...

Page 982: ...are cannot feed data to the TDES DES engine Otherwise the flag INBUFERR will be set to 1 8 INBUFEMPTY TDES DES in Buffer Empty 0 There are some data in input buffer waiting for the TDES DES engine to...

Page 983: ...DES1_KEY3H CRYP_BA 0x258 R W TDES Key 3 High Word Register for Channel 1 0x0000_0000 CRPT_TDES1_KEY3L CRYP_BA 0x25C R W TDES Key 3 Low Word Register for Channel 1 0x0000_0000 CRPT_TDES2_KEY1H CRYP_BA...

Page 984: ...EYH KEYL TDES DES Key High Low Word The key registers for TDES DES algorithm calculation The security key for the TDES DES accelerator is 64 bits Thus it needs two 32 bit registers to store a security...

Page 985: ...YP_BA 0x264 R W TDES DES Initial Vector Low Word Register for Channel 1 0x0000_0000 CRPT_TDES2_IVH CRYP_BA 0x2A0 R W TDES DES Initial Vector High Word Register for Channel 2 0x0000_0000 CRPT_TDES2_IVL...

Page 986: ...DDR Bits Description 31 0 SADDR TDES DES DMA Source Address The TDES DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO The CRPT_TDESn_SADDR keeps...

Page 987: ...ion 31 0 TDES_DADR TDES DES DMA Destination Address The TDES DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO The CRPT_TDESn_DADDR keeps the de...

Page 988: ...l 3 0x0000_0000 31 30 29 28 27 26 25 24 CNT 23 22 21 20 19 18 17 16 CNT 15 14 13 12 11 10 9 8 CNT 7 6 5 4 3 2 1 0 CNT Bits Description 31 0 CNT TDES DES Byte Count The CRPT_TDESn_CNT keeps the byte co...

Page 989: ...t R W Description Reset Value CRPT_TDES_DATIN CRYP_BA 0x234 R W TDES DES Engine Input data Word Register 0x0000_0000 31 30 29 28 27 26 25 24 DATIN 23 22 21 20 19 18 17 16 DATIN 15 14 13 12 11 10 9 8 D...

Page 990: ...Description Reset Value CRPT_TDES_DATOUT CRYP_BA 0x238 R TDES DES Engine Output data Word Register 0x0000_0000 31 30 29 28 27 26 25 24 DATOUT 23 22 21 20 19 18 17 16 DATOUT 15 14 13 12 11 10 9 8 DATOU...

Page 991: ...14 13 12 11 10 9 8 FDBCK 7 6 5 4 3 2 1 0 FDBCK Bits Description 31 0 FDBCK TDES DES Feedback The feedback value is 64 bits in size The TDES DES engine uses the data from CRPT_TDES_FDBCKH CRPT_TDES_FDB...

Page 992: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 992 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL SHA HMAC Register 5 27 7 5...

Page 993: ...at CPU feeds data to the accelerator will be changed from byte3 byte2 byte1 byte0 to byte0 byte1 byte2 byte3 22 OUTSWAP SHA HMAC Engine Output Data Swap 0 Keep the original order 1 The order that CPU...

Page 994: ...m to the engine is done by DMA logic 6 Reserved Reserved 5 DMALAST SHA HMAC Last Block In DMA mode this bit must be set as beginning the last DMA cascade round In Non DMA mode this bit must be set as...

Page 995: ...16 Reserved Reserved 16 DATINREQ SHA HMAC Non dMA Mode Data Input Request 0 No effect 1 Request SHA HMAC Non DMA mode data input 15 CMPSTS SHA HMAC Output Digest Compare Result with MTP Key 0 SHA HMAC...

Page 996: ...0x0000_0000 CRPT_HMAC_DGS T6 CRYP_BA 0x320 R SHA HMAC Digest Message 6 0x0000_0000 CRPT_HMAC_DGS T7 CRYP_BA 0x324 R SHA HMAC Digest Message 7 0x0000_0000 CRPT_HMAC_DGS T8 CRYP_BA 0x328 R SHA HMAC Dig...

Page 997: ...st Message Output Register For SHA 160 the digest is stored in CRPT_HMAC_DGST0 CRPT_HMAC_DGST4 For SHA 224 the digest is stored in CRPT_HMAC_DGST0 CRPT_HMAC_DGST6 For SHA 256 the digest is stored in C...

Page 998: ...7 16 KEYCNT 15 14 13 12 11 10 9 8 KEYCNT 7 6 5 4 3 2 1 0 KEYCNT Bits Description 31 0 KEYCNT SHA HMAC Key Byte Count The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA HMAC engine operates The...

Page 999: ...e CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored Based on the source address the SHA HMAC accelerator can read the plain text from system memory and do SHA...

Page 1000: ...HMAC Operation Byte Count The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA HMAC engine operating in DMA mode The CRPT_HMAC_DMACNT is 32 bit and the maximum of byte count is...

Page 1001: ...Description Reset Value CRPT_HMAC_DATIN CRYP_BA 0x354 R W SHA HMAC Engine Non DMA Mode Data Input Port Register 0x0000_0000 31 30 29 28 27 26 25 24 DATIN 23 22 21 20 19 18 17 16 DATIN 15 14 13 12 11...

Page 1002: ...tors are provided for resizing the image For the 2D rotation it can rotate left or right 45 90 or 180 degrees and also supports the flip flop mirror or up side down pictures 5 28 2 Features Support 2D...

Page 1003: ...possible raster operations ROPs The graphic engine can support several kinds of BitBLT including HostBLT Pattern BLT Color Font Expanding BLT Transparent BLT Color Font Expansion and Rectangle Fill e...

Page 1004: ...e Graphics Engine then repetitively copies it to the destination area with all ones in the pattern being expanded to a pixel of foreground color and all zeros being either expanded to a pixel of backg...

Page 1005: ...s active during BitBLT and must be loaded with appropriate value BitBLT Direction 5 28 5 9 The BitBLT direction indicates the direction in which the X Y address is stepped across the rectangle It also...

Page 1006: ...used to draw a pixel wide solid or textured line from screen coordinates x1 y1 to x2 y2 To draw a solid line the foreground color is used to specify color of the line To draw a textured line a 16 bit...

Page 1007: ...45 90 or 180 degrees and it also supports the flip flop mirror or up side down pictures Just as the rectangle clipping for BitBLTs and line clipping for Bresenham Line when a clip flag is enabled the...

Page 1008: ...r 0x0000_0000 GE2D_BGCOLR GE2D_BA 0x024 R W Graphic Engine Background Color Register 0x0000_0000 GE2D_FGCOLR GE2D_BA 0x028 R W Graphic Engine Foreground Color Register 0x0000_0000 GE2D_TRNSCOLR GE2D_B...

Page 1009: ...GE2D_BA 0x068 R W Graphic Engine HostBLT Data Port 2 Register 0x0000_0000 GE2D_HSTBLTDP3 GE2D_BA 0x06C R W Graphic Engine HostBLT Data Port 3 Register 0x0000_0000 GE2D_HSTBLTDP4 GE2D_BA 0x070 R W Grap...

Page 1010: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1010 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 28 7 Register Description...

Page 1011: ...E2D_TRG GE2D_BA 0x000 R W Graphic Engine Trigger Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved...

Page 1012: ...g Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved XYSORGSA 23 22 21 20 19 18 17 16 XYSORGSA 15 14 13 12 11 10 9 8 XYSORGSA 7 6 5 4 3 2 1 0 XYSORGSA Bits Description 31 28 Reserved Reserv...

Page 1013: ...vertical scaling factor in graphic engine The output image height will be equal to the input image height VSF_N VSF_M The value of VSF_N must be equal or less than VSF_M 15 8 TILE_X HSF_N Tile Count...

Page 1014: ...erence Pixel Coordinate Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved RRPY 23 22 21 20 19 18 17 16 RRPY 15 14 13 12 11 10 9 8 Reserved RRPX 7 6 5 4 3 2 1 0 RRPX Bits Description 31 27 Reserved...

Page 1015: ...errupt Status Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved GE2DIF Bits Description 31 1 Reserved Reser...

Page 1016: ...ttern Location Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved PATSA 23 22 21 20 19 18 17 16 PATSA 15 14 13 12 11 10 9 8 PATSA 7 6 5 4 3 2 1 0 PATSA Bits Description 31 28 Reser...

Page 1017: ...3 22 21 20 19 18 17 16 DIAGINC 15 14 13 12 11 10 9 8 Reserved AXIALINC 7 6 5 4 3 2 1 0 AXIALINC Bits Description 29 16 DIAGINC Diagonal Error Term Increment For Bresenham line draw this register speci...

Page 1018: ...Initial Error Term Pixel Count Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved INIT 23 22 21 20 19 18 17 16 INIT 15 14 13 12 11 10 9 8 Reserved LINEPC 7 6 5 4 3 2 1 0 LINEPC Bits Description 29...

Page 1019: ...5 4 3 2 1 0 SRCDT SRCDS PATDT DRAWDIR DSTDATD Bits Description 31 24 ROP ROP Raster Operation Code It supports all Microsoft 256 Raster Operation Codes Each raster operation code is an 8 bit value th...

Page 1020: ...16 ADDRMD Graphics Engine Addressing Mode 0 Linear addressing mode 1 X Y addressing mode 15 14 TRANSMD GE Transparency Mode 00 Disabled 01 Mono transparency 10 Color transparency 11 Reserved 13 MTS M...

Page 1021: ...he drawing directions for BitBLT Bresenham line and Rotate For BitBLT operation 000 Right down 001 Right down 010 Left down 011 Left down 100 Right up 101 Right up 110 Left up 111 Left up For Bresenha...

Page 1022: ...25 24 Reserved 23 22 21 20 19 18 17 16 BGCOLR 15 14 13 12 11 10 9 8 BGCOLR 7 6 5 4 3 2 1 0 BGCOLR Bits Description 31 24 Reserved Reserved 23 0 BGCOLR Graphics Engine Background Color These bits spec...

Page 1023: ...25 24 Reserved 23 22 21 20 19 18 17 16 FGCOLR 15 14 13 12 11 10 9 8 FGCOLR 7 6 5 4 3 2 1 0 FGCOLR Bits Description 31 24 Reserved Reserved 23 0 FGCOLR Graphics Engine Foreground Color These bits spec...

Page 1024: ...Reserved 23 22 21 20 19 18 17 16 TRNSCOLR 15 14 13 12 11 10 9 8 TRNSCOLR 7 6 5 4 3 2 1 0 TRNSCOLR Bits Description 31 24 Reserved Reserved 23 0 TRNSCOLR Graphics Engine Transparency Color These bits...

Page 1025: ...0x030 R W Graphic Engine Transparency Color Mask Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 TCMSK 15 14 13 12 11 10 9 8 TCMSK 7 6 5 4 3 2 1 0 TCMSK Bits Description...

Page 1026: ...ic Engine XY Mode Display Memory Origin Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved XYDORGSA 23 22 21 20 19 18 17 16 XYDORGSA 15 14 13 12 11 10 9 8 XYDORGSA 7 6 5 4 3 2 1 0...

Page 1027: ...0000 31 30 29 28 27 26 25 24 Reserved DSTPITCH 23 22 21 20 19 18 17 16 DSTPITCH 15 14 13 12 11 10 9 8 Reserved SRCPITCH 7 6 5 4 3 2 1 0 SRCPITCH Bits Description 31 29 Reserved Reserved 28 16 DSTPITCH...

Page 1028: ...22 21 20 19 18 17 16 SRCSPA 15 14 13 12 11 10 9 8 SRCSPA 7 6 5 4 3 2 1 0 SRCSPA Bits Description 31 28 Reserved Reserved 27 0 SRCSPA Source Start Pixel Address If ADDRMD GE2D_CTL 16 is low GE2D operat...

Page 1029: ...22 21 20 19 18 17 16 DSTSPA 15 14 13 12 11 10 9 8 DSTSPA 7 6 5 4 3 2 1 0 DSTSPA Bits Description 31 28 Reserved Reserved 27 0 DSTSPA Destination Start Pixel Address If ADDRMD GE2D_CTL 16 is low GE2D o...

Page 1030: ...its Description 31 27 Reserved Reserved 26 16 HEIGHT Rectangle Height If ADDRMD GE2D_CTL 16 is low GE2D operates at linear addressing mode and this field indicates the height of rectangle by byte If A...

Page 1031: ...ngine Clipping Boundary Top Left Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved CLPTOP 23 22 21 20 19 18 17 16 CLPTOP 15 14 13 12 11 10 9 8 Reserved CLPLFT 7 6 5 4 3 2 1 0 CLPLFT Bits Descripti...

Page 1032: ...e Clipping Boundary Bottom Right Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved CLPBOT 23 22 21 20 19 18 17 16 CLPBOT 15 14 13 12 11 10 9 8 Reserved CLPRGT 7 6 5 4 3 2 1 0 CLPRGT Bits Descripti...

Page 1033: ...4 PTNLNE3 23 22 21 20 19 18 17 16 PTNLNE2 15 14 13 12 11 10 9 8 PTNLNE 1 7 6 5 4 3 2 1 0 PTNLNE 0 Bits Description 31 24 PTNLNE3 Pattern Line 3 When pattern is monochrome this field is the line 3 of t...

Page 1034: ...24 PTNLNE7 23 22 21 20 19 18 17 16 PTNLNE6 15 14 13 12 11 10 9 8 PTNLNE5 7 6 5 4 3 2 1 0 PTNLNE4 Bits Description 31 24 PTNLNE7 Pattern Line 7 When pattern is monochrome this field is the line 7 of th...

Page 1035: ...0 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 WRPLNMSK 15 14 13 12 11 10 9 8 WRPLNMSK 7 6 5 4 3 2 1 0 WRPLNMSK Bits Description 31 24 Reserved Reserved 23 0 WRPLNMSK Write Plane Mask Thes...

Page 1036: ...es the 16 bit line style pattern In BitBLT mode this field indicates the alpha blending factor The bit 31 24 indicates the alpha blending factor Ks for source data while bit 23 16 indicates the alpha...

Page 1037: ...gine Pixel Depth 00 8 bit 01 16 bit 10 32 bit 11 reserved 3 BLTMD BitBLT Mode 0 BitBLT type is according to GE2D_CTL control bits 1 BitBLT type follows BLTTYP GE2D_MISCTL 2 0 setting 2 0 BLTTYP BitBLT...

Page 1038: ...E2D_BA 0x06C R W Graphic Engine HostBLT Data Port 3 Register 0x0000_0000 GE2D_HSTBLTDP4 GE2D_BA 0x070 R W Graphic Engine HostBLT Data Port 4 Register 0x0000_0000 GE2D_HSTBLTDP5 GE2D_BA 0x074 R W Graph...

Page 1039: ...for decode Support arbitrarily 1X 8X image up scaling function for encode mode Support down scaling function for encode and decode modes Thumbnail Primary Support specified window decode mode Support...

Page 1040: ...70 TECHNICAL REFERENCE MANUAL 5 29 3 Block Diagram AHB Master BIU Pre Processing Post Processing Capture IRAM 8 64 ORAM 16 32 DCT IDCT TRAM 72 15 ZRAM 64 12 2 Quant VLE AHB Master BIU Pre Processing P...

Page 1041: ...programmer needs to program all the required control registers parameters like image format width height header format quantization table scaling factor memory address etc before triggering the JPEG...

Page 1042: ...Y component only format if planar format set and packet YUYV format if packet format set Besides the standard compression the JPEG encoder integrates a pre processing unit that can scale up or scale...

Page 1043: ...owing figure specifies the encode path When the programmer turns on thumbnail encode the JPEG engine supports an option for inserting one buffer region into primary JPEG bit stream This option can be...

Page 1044: ...should be mentioned that the rotation function can only be applied only when encode YCbCr 4 2 0 source The standard JPEG bit stream format includes some headers that specify some information For exam...

Page 1045: ...he variable length decoder VLD The decoded data are parsed inverse zig zag scanned IZZ inverse quantization IQ and inverse DCT IDCT An offset value is added to the output data of IDCT to become the re...

Page 1046: ...table The programmer can choose to turn on the programmable Huffman table function or directly use the default Huffman table to decode the JPEG bitstream by setting the register bit PDHTAB JITCR 0 The...

Page 1047: ...BQC JPEG_BA 0x014 R W JPEG Encode Thumbnail Q Table Control Register 0x0000_00F4 JPRIWH JPEG_BA 0x018 R W JPEG Primary Width Height Register 0x0000_0000 JTHBWH JPEG_BA 0x01C R W JPEG Encode Thumbnail...

Page 1048: ...PEG_BA 0x0A4 R W JPEG Bit stream Frame Buffer 1 Starting Address Register 0x0000_0000 JPRI_SIZE JPEG_BA 0x0A8 R JPEG Encode Primary Image Bit stream Size Register 0x0000_0000 JTHB_SIZE JPEG_BA 0x0AC R...

Page 1049: ...JPEG_BA 0x168 R W JPEG Quantization Table 1 Element Register 10 0x0000_0000 JQTAB1ER11 JPEG_BA 0x16C R W JPEG Quantization Table 1 Element Register 11 0x0000_0000 JQTAB1ER12 JPEG_BA 0x170 R W JPEG Qua...

Page 1050: ...C970 TECHNICAL REFERENCE MANUAL JQTAB2ER13 JPEG_BA 0x1B4 R W JPEG Quantization Table 2 Element Register 13 0x0000_0000 JQTAB2ER14 JPEG_BA 0x1B8 R W JPEG Quantization Table 2 Element Register 14 0x0000...

Page 1051: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1051 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 29 7 Register Description...

Page 1052: ...filled into frame buffer by host no matter JPEG is pending or not 8 RESUMEO Resume JPEG Operation for Output On the fly Mode Write a 1 to this bit to restart JPEG from a pending state after an output...

Page 1053: ...4 2 2 2 QT_BUSY Quantization table Busy Status Read only 0 Quantization Table is ready for host access 1 Quantization Table is busy and can t be accessed 1 ENG_RST Soft Reset JPEG Engine Except JPEG C...

Page 1054: ...FIF T_HTAB T_QTAB T_DRI Bits Description 31 8 Reserved Reserved 7 P_JFIF Primary JPEG Bit stream Include JFIF Header 0 Not Include 1 Include 6 P_HTAB Primary JPEG Bit stream Include Huffman table 0 No...

Page 1055: ...70 Technical Reference Manual Publication Release Date Dec 15 2015 1055 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 T_DRI Thumbnail JPEG Bit stream Include Restart Interval 0 Not Include 1 Incl...

Page 1056: ...ut wait feature The decoding processing will be halted and an interrupt will issued while the current frame buffer is full The decoding process will be resumed and new frame buffer size and start addr...

Page 1057: ...e QTAB are defined for Y Cb and Cr header QTAB HTAB is defined in only one DQT DHT marker 6 EY_ONLY Encode Gray level Y component Only Image 0 Encode normal Y Cb Cr color image 1 Encode gray level ima...

Page 1058: ...elease Date Dec 15 2015 1058 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 PDHTAB Programmable Huffman table Function for Decode 0 Disable Use default huffman table for JPEG decode 1 Enable Allow...

Page 1059: ...6 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 P_QADJUST P_QVS Bits Description 31 8 Reserved Reserved 7 4 P_QADJUST Primary Quantization table Adjust...

Page 1060: ...6 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 T_QADJUST T_QVS Bits Description 31 8 Reserved Reserved 7 4 T_QADJUST Thumbnail Quantization table Adju...

Page 1061: ...PEG image The value is equal to the size after scaling up or scaling down Note The JPEG engine supports horizontal and vertical arbitrarily up scaling 1X 8X in planar format encode mode When the verti...

Page 1062: ...28 27 26 25 24 Reserved T_HEIGHT 23 22 21 20 19 18 17 16 T_HEIGHT 15 14 13 12 11 10 9 8 Reserved T_WIDTH 7 6 5 4 3 2 1 0 T_WIDTH Bits Description 31 29 Reserved Reserved 28 16 T_HEIGHT Thumbnail Encod...

Page 1063: ...W Description Reset Value JPRST JPEG_BA 0x020 R W JPEG Encode Primary Restart Interval Register 0x0000_0004 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Res...

Page 1064: ...Description Reset Value JTRST JPEG_BA 0x024 R W JPEG Encode Thumbnail Restart Interval Register 0x0000_0004 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Res...

Page 1065: ...reports the height of decoded JPEG image 15 0 DEC_WIDTH Decode Image Width A 16 bit value reports the width of decoded JPEG image Note 1 The value of width and height are extracted from bitstream head...

Page 1066: ...9 Reserved Reserved 28 DOW_INTE Decoding Output Wait Interrupt Enable 0 DOW_INTS JINTCR 24 high to trigger JPEG interrupt Disabled 1 DOW_INTS JINTCR 24 high to trigger JPEG interrupt Enabled 27 25 Res...

Page 1067: ...e End Wait Interrupt Status 0 No Interrupt 1 Interrupt Generated Note When write value 1 to this bit the interrupt will be clear and JPEG will resume operating from a pending state 5 IPW_INTS Input Wa...

Page 1068: ...FERENCE MANUAL 1 DER_INTS Decode Error Interrupt Status 0 No Interrupt 1 Interrupt Generated Note When write value 1 to this bit the interrupt will be clear 0 EER_INTS Encode On the fly Error Interrup...

Page 1069: ...ait Frame Buffer Size 0xFFFF_FFFF 31 30 29 28 27 26 25 24 JDOWFBS 23 22 21 20 19 18 17 16 JDOWFBS 15 14 13 12 11 10 9 8 JDOWFBS 7 6 5 4 3 2 1 0 JDOWFBS Bits Description 31 0 JDOWFBS JPEG Decoding Outp...

Page 1070: ...2 1 0 MCU_S_X Bits Description 31 26 Reserved Reserved 25 16 MCU_S_Y MCU Minimum Coded Unit Start Position Y for Window Decode Mode A 10 bit value specifies the MCU start position y of the window reg...

Page 1071: ...8 17 16 MCU_E_Y 15 14 13 12 11 10 9 8 Reserved MCU_E_X 7 6 5 4 3 2 1 0 MCU_E_X Bits Description 31 26 Reserved Reserved 25 16 MCU_E_Y MCU End Position Y for Window Decode Mode A 10 bit value specifies...

Page 1072: ...ecode Mode Control Register 2 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved WD_WIDTH 7 6 5 4 3 2 1 0 WD_WIDTH Bits Description 31 13 Rese...

Page 1073: ...down scaling factor in 4 2 0 image Ex For scaling down 1 3 in vertical direction 4 2 2 image the minimum buffer size must be 48 line 16 x 3 If down scaling in vertical direction is applied the source...

Page 1074: ...Data Output 0 Disable JPEG will continue to write the whole encoded bitstream or decoded image data into frame buffer 1 Enable JPEG can write partial encoded bitstream or decoded image data by re usin...

Page 1075: ...ol Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved 8X Reserved A_JUMP Reserved Bits Description 31 7 Rese...

Page 1076: ...ling function is not supported In packet format decode mode the image is arbitrarily down scaled 1X 16X for Y422 and Y420 1X 8X for Y444 14 PS_LPF_ON Primary Image Down scaling Low Pass Filter for Dec...

Page 1077: ...t value specifies the vertical down scaling factor The scaling factor is equal to 1 SCALY_F For example if SCALY_F 3 the image will shrink 4 times in vertical direction Note For planar format encode m...

Page 1078: ...F Bits Description 31 16 Reserved Reserved 15 TSX_ON Thumbnail Image Horizontal Down scaling for Encode 0 Disable no horizontal down scale 1 Enable 14 13 Reserved Reserved 12 8 TSCALX_F Thumbnail Imag...

Page 1079: ...16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 DBF_EN Reserved IP_BUF Reserved OP_BUF Bits Description 31 8 Reserved Reserved 7 DBF_EN Dual Buffering Control 0 Disable dual buffering 1 En...

Page 1080: ...30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 RES_SIZE 7 6 5 4 3 2 1 0 RES_SIZE Bits Description 31 16 Reserved Reserved 15 0 RES_SIZE Primary Encode Bit stream...

Page 1081: ...Primary Thumbnail Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 OFFSET_SIZE 15 14 13 12 11 10 9 8 OFFSET_SIZE 7 6 5 4 3 2 1 0 OFFSET_SIZE Bits Description 31 24 Reserve...

Page 1082: ...set Value JFSTRIDE JPEG_BA 0x078 R W JPEG Encode Bit stream Frame Stride Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 F_STRIDE 15 14 13 12 11 10 9 8 F_STRIDE 7 6 5 4 3...

Page 1083: ...29 28 27 26 25 24 Y_IADDR0 23 22 21 20 19 18 17 16 Y_IADDR0 15 14 13 12 11 10 9 8 Y_IADDR0 7 6 5 4 3 2 1 0 Y_IADDR0 Bits Description 31 0 Y_IADDR0 JPEG Y Component Frame Buffer 0 Starting Address A 3...

Page 1084: ...t Value JUADDR0 JPEG_BA 0x080 R W JPEG U Component Frame Buffer 0 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 U_IADDR0 23 22 21 20 19 18 17 16 U_IADDR0 15 14 13 12 11 10 9 8 U_IADDR0...

Page 1085: ...t Value JVADDR0 JPEG_BA 0x084 R W JPEG V Component Frame Buffer 0 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 V_IADDR0 23 22 21 20 19 18 17 16 V_IADDR0 15 14 13 12 11 10 9 8 V_IADDR0...

Page 1086: ...PEG_BA 0x088 R W JPEG Y Component or Packet Format Frame Buffer 1 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Y_IADDR1 23 22 21 20 19 18 17 16 Y_IADDR1 15 14 13 12 11 10 9 8 Y_IADDR1...

Page 1087: ...t Value JUADDR1 JPEG_BA 0x08C R W JPEG U Component Frame Buffer 1 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 U_IADDR1 23 22 21 20 19 18 17 16 U_IADDR1 15 14 13 12 11 10 9 8 U_IADDR1...

Page 1088: ...t Value JVADDR1 JPEG_BA 0x090 R W JPEG V Component Frame Buffer 1 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 V_IADDR1 23 22 21 20 19 18 17 16 V_IADDR1 15 14 13 12 11 10 9 8 V_IADDR1...

Page 1089: ...gister 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved Y_STRIDE 7 6 5 4 3 2 1 0 Y_STRIDE Bits Description 31 12 Reserved Reserved 11 0 Y_ST...

Page 1090: ...E JPEG_BA 0x098 R W JPEG U Component Frame Buffer Stride Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved U_STRIDE 7 6 5 4 3 2 1 0...

Page 1091: ...E JPEG_BA 0x09C R W JPEG V Component Frame Buffer Stride Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved V_STRIDE 7 6 5 4 3 2 1 0...

Page 1092: ...lue JIOADDR0 JPEG_BA 0x0A0 R W JPEG Bit stream Frame Buffer 0 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 IO_IADDR0 23 22 21 20 19 18 17 16 IO_IADDR0 15 14 13 12 11 10 9 8 IO_IADDR0...

Page 1093: ...lue JIOADDR1 JPEG_BA 0x0A4 R W JPEG Bit stream Frame Buffer 1 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 IO_IADDR1 23 22 21 20 19 18 17 16 IO_IADDR1 15 14 13 12 11 10 9 8 IO_IADDR1...

Page 1094: ...Description Reset Value JPRI_SIZE JPEG_BA 0x0A8 R JPEG Encode Primary Image Bit stream Size Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 PRI_SIZE 15 14 13 12 11 10 9...

Page 1095: ...escription Reset Value JTHB_SIZE JPEG_BA 0x0AC R JPEG Encode Thumbnail Bit stream Size Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 THB_...

Page 1096: ...ormat encode mode and arbitrarily down scaling in packet format decode mode This value needs to be specified only when vertical up scaling Y2 or down scaling PSX_ON is enabled Note if up scale from 12...

Page 1097: ...served 6 4 BSFIFO_HT Bit stream FIFO High threshold Control While the fullness of bit stream output FIFO is higher than the high threshold in encode mode the priority for output will become higher tha...

Page 1098: ...ode Source Image Height Register 0x0000_0FFF 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved JSRCH 7 6 5 4 3 2 1 0 JSRCH Bits Description 31 12 Reserve...

Page 1099: ..._0000 JQTAB0ER8 JPEG_BA 0x120 R W JPEG Quantization Table 0 Element Register 8 0x0000_0000 JQTAB0ER9 JPEG_BA 0x124 R W JPEG Quantization Table 0 Element Register 9 0x0000_0000 JQTAB0ER10 JPEG_BA 0x128...

Page 1100: ...PEG Quantization table 0 2 An 8 bit value specifies one element 2 6 10 58 62 of the Quantization Table 0 15 8 QTAB0_1 JPEG Quantization table 0 1 An 8 bit value specifies one element 1 5 9 57 61 of th...

Page 1101: ...000 JQTAB1ER9 JPEG_BA 0x164 R W JPEG Quantization Table 1 Element Register 9 0x0000_0000 JQTAB1ER10 JPEG_BA 0x168 R W JPEG Quantization Table 1 Element Register 10 0x0000_0000 JQTAB1ER11 JPEG_BA 0x16C...

Page 1102: ...15 1102 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 15 8 QTAB1_1 JPEG Quantization table 1 1 An 8 bit value specifies one element of the Quantization Table 1 7 0 QTAB1_0 JPEG Quantization table 1...

Page 1103: ...nt Register 8 0x0000_0000 JQTAB2ER9 JPEG_BA 0x1A4 R W JPEG Quantization Table 2 Element Register 9 0x0000_0000 JQTAB2ER10 JPEG_BA 0x1A8 R W JPEG Quantization Table 2 Element Register 10 0x0000_0000 JQ...

Page 1104: ...15 1104 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 15 8 QTAB2_1 JPEG Quantization table 2 1 An 8 bit value specifies one element of the Quantization Table 2 7 0 QTAB2_0 JPEG Quantization table 2...

Page 1105: ...both sync type and MPU type LCDM This LCD Controller is a bus master and can transfer display data from system memory SDRAM without CPU intervention 5 30 2 Features Input data format YUV422 YUV444 RGB...

Page 1106: ...the register SYS_MFP_GPAL SYS_MFP_GPAH SYS_MFP_GPDH SYS_MFP_GPGL and SYS_MFP_GPGH to know how to configure related pins as the LCD display interface function Set LCD CLK_HCLKEN 26 high to turn on cloc...

Page 1107: ...ertical direction But it only supports 2X and 4X up scaling Display Overlay Control 5 30 5 2 The Display Control unit includes timing controller and overlay controller The timing controller generates...

Page 1108: ...D color key pattern is defined in register OSD_CKEY for V U Y or B G R components according to the source color format OSD_SRC DCCS 14 12 The color key mask is also provided in registers OSD_CMASK Onl...

Page 1109: ...ors both in 8 bit and 16 bit or 9 bit and 18 bit data bus modes The related control signals for MPU interfaced LCD are defined in register DEVICE_CTRL In addition the video source color format can be...

Page 1110: ...egister 0x0000_0000 VA_FBCTRL LCM_BA 0x2C R W Video Stream Frame Buffer Control Register 0x0000_0000 VA_SCALE LCM_BA 0x30 R W Video Stream Scaling Control Register 0x0000_0000 VA_TEST LCM_BA 0x34 R W...

Page 1111: ...r 0x0000_0000 HC_BADDR LCM_BA 0x78 R W Hardware Cursor Memory Base Address Register 0x0000_0000 HC_COLOR0 LCM_BA 0x7C R W Hardware Cursor Color RAM 0 Register 0x0000_0000 HC_COLOR1 LCM_BA 0x80 R W Har...

Page 1112: ...served Reserved 29 LACE_F Interlace Mode Display Field Status Read Only 0 Current displayed field is even field 1 Current displayed field is odd field 28 VSYNC Internal Vertical Sync Status Read Only...

Page 1113: ...88 011 RGB666 100 RGB565 101 RGB444 Low 4 h0 R G B 111 RGB444 High R G B 4 h0 110 RGB332 11 Reserved Reserved 10 8 VA_SRC Video Stream Source Color Format 000 YUV422 001 YCBCR422 010 RGB888 011 RGB666...

Page 1114: ...Controller Interrupt Output Enable 0 Disable 1 Enable 3 DISP_OUT_EN Display relative Output Pins Tri state Mode 0 Output disabled output pins in tri state mode 1 Display output enable normal mode 2 O...

Page 1115: ...tput pin RS 1 command data 0 display parameter data 1 Output pin RS 0 command data 1 display parameter data 30 CM16t18 Command Mapping From 16 bit to 18 bit or 8 bit to 9 bit Data Bus Used for 18 bit...

Page 1116: ...36 colors mode 0 Data bus is 8 bit 1 Data bus is 16 bit For 262144 colors mode 0 Data bus is 8 9 bit 1 Data bus is 16 18 bit For 1677721 colors mode 0 Data bus is 8 bit 3 cycles per pixel at SWAP_YCbC...

Page 1117: ...CE_CTRL 7 5 100 and 110 Set LCD_DDA 0 will disable DDA operation 7 5 DEVICE DEVICE Setting 000 Packed YUV422 001 Packed YUV444 100 Sync based TFT LCD UNIPAC 101 Sync based TFT LCD SEIKO EPSON 110 Sync...

Page 1118: ...a bus mode 01 NTSC 10 PAL 2 1 SWAP_YcbC r share_bit DEVICE DEVICE_CT RL 7 5 000 YUV Data Output Swap for Packed YUV Mode When DEVICE DEVICE_CTRL 7 5 000 00 UYVY 01 YUYV 10 VYUY 11 YVYU 2 SWAP_YcbC r 1...

Page 1119: ...GB666 pixel data is output first the LSB 9 bit data is output secondly 1 the low byte of 16 bit RGB565 pixel data is output first the low byte data is output secondly the LSB 9 bit of 18 bit RGB666 pi...

Page 1120: ...GGGGG BBBBBB 2 fer 1pixel 11 RRRRRR GGGGGG BBBBBB 2 fer 1pixel 18 bits RRRRRRGGGGGGBBBBBB 1 fer 1pixel Data bus arrangement for different pixel for Unipac Interface LCM at 16 M colors and 8 bit data b...

Page 1121: ...BB0 pixel 0 GGGGGGGG1 pixel 1 BBBBBBBB0 pixel 0 GGGGGGGG0 pixel 0 RRRRRRRR1 pixel 1 1 5 fer 1pixel 0 00 00 RRRRRRRR0 pixel 0 GGGGGGGG0 pixel 0 BBBBBBBB1 pixel 1 GGGGGGGG0 pixel 0 BBBBBBBB0 pixel 0 RRR...

Page 1122: ...bus Gray Scale Selection Bus Interface Mode DBWORD SWAP_YCbC r Control LCD Line Data Out LCD_ODD SEL_ODD Data Bus Arrangement Denote Don t Care Bit Note 24 bits data bus 1 00 RRRRRRRRGGGGGGGGBBBBBBBB...

Page 1123: ...MPULCD_CMD LCM_BA 0x08 R W MPU Interface LCD Write Command Register 0x0000_0000 31 30 29 28 27 26 25 24 CMD_BUSY WR_RS READ Reserved 23 22 21 20 19 18 17 16 Reserved MPULCD_CMD 15 14 13 12 11 10 9 8...

Page 1124: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Reserved UNDERRUN_EN DISP_F_EN Bits Description 31 DISP_F_INT Frame Display Complete Interrupt Status Write clear When...

Page 1125: ...Technical Reference Manual Publication Release Date Dec 15 2015 1125 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 Disable 1 Enable 0 DISP_F_EN Frame Display Complete Interrupt Enable 0 Disable 1...

Page 1126: ...ach field frame including the retrace time Register Offset R W Description Reset Value CRTC_SIZE LCM_BA 0x10 R W CRTC Display Size Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved VTT 10 8 23 22...

Page 1127: ...played scan line for each field frame Register Offset R W Description Reset Value CRTC_DEND LCM_BA 0x14 R W CRTC Display Enable End Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved VDEND 10 8 23...

Page 1128: ...W Description Reset Value CRTC_HR LCM_BA 0x18 R W CRTC Internal Horizontal Retrace Timing Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved HRE 10 8 23 22 21 20 19 18 17 16 HRE 7 0 15 14 13 12 11...

Page 1129: ...so hsync s hrs would move three cycles if hrs added or substracted 1 In order to adjust hsync signal in pclk unit RGB_SHIFT shared register aids this function in LCD with 8 bits data bus mode 00 Hsync...

Page 1130: ...B_SHIFT shared register aids this function in High color TFT LCD with 8 bit data bus mode 00 Hsync will not move 01 Hsync will left move 1 pclk cycle 10 Hsync will left move 2 pclk cycle 11 Hsync will...

Page 1131: ...Value CRTC_VR LCM_BA 0x20 R W CRTC Internal Vertical Retrace Timing Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved VRE 10 8 23 22 21 20 19 18 17 16 VRE 7 0 15 14 13 12 11 10 9 8 Reserved VRS 1...

Page 1132: ...am Register Offset R W Description Reset Value VA_BADDR0 LCM_BA 0x24 R W Video Stream Frame Buffer 0 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 VA_BADDR0 31 24 23 22 21 20 19 18 17...

Page 1133: ...am Register Offset R W Description Reset Value VA_BADDR1 LCM_BA 0x28 R W Video Stream Frame Buffer 1 Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 VA_BADDR1 31 24 23 22 21 20 19 18 17...

Page 1134: ...an AHB burst cycle is issued to read or write the data in the region pointed to by the AHB pointer Register Offset R W Description Reset Value VA_FBCTRL LCM_BA 0x2C R W Video Stream Frame Buffer Cont...

Page 1135: ...VA_FF Video Stream Fetch Finish An 11 bit value specifies the number of WORD SDRAM access cycle for a horizontal scan line fetching of video data stream 15 11 Reserved Reserved 10 0 VA_STRIDE Video S...

Page 1136: ...000 31 30 29 28 27 26 25 24 Reserved VA_SCALE_V 12 8 23 22 21 20 19 18 17 16 VA_SCALE_V 7 0 15 14 13 12 11 10 9 8 XCOPY Reserved VA_SCALE_H 12 8 7 6 5 4 3 2 1 0 VA_SCALE_H 7 0 Bits Description 31 29 R...

Page 1137: ...if the BIST fails or succeeds If the value of BistFail is 2 b00 at the end the embedded SRAM pass the BIST test otherwise it is faulty 9 BistFinish The Finish indicates the end of the BIST operation W...

Page 1138: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1138 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 0 SIGN_ON Signature Analyzer 0 Disable 1 Start signature analyzer operation...

Page 1139: ...D CRTC_DEND 26 16 the Active window will be actually ended at VDEND CRTC_DEND 26 16 Register Offset R W Description Reset Value VA_WIN LCM_BA 0x38 R W Video Stream Active Window Coordinates Register 0...

Page 1140: ...f Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 VA_STUFF 23 16 15 14 13 12 11 10 9 8 VA_STUFF 15 8 7 6 5 4 3 2 1 0 VA_STUFF 7 0 Bits Description 31 24 Reserved Reserved...

Page 1141: ...YS Register Offset R W Description Reset Value OSD_WINS LCM_BA 0x40 R W OSD Window Starting Coordinates Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OSD_WYS 10 8 23 22 21 20 19 18 17 16 OSD_W...

Page 1142: ...WYS Register Offset R W Description Reset Value OSD_WINE LCM_BA 0x44 R W OSD Window Ending Coordinates Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OSD_WYE 10 8 23 22 21 20 19 18 17 16 OSD_WY...

Page 1143: ...eam Register Offset R W Description Reset Value OSD_BADDR LCM_BA 0x48 R W OSD Stream Frame Buffer Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 OSD_BADDR 31 24 23 22 21 20 19 18 17 16...

Page 1144: ...ching Register Offset R W Description Reset Value OSD_FBCTRL LCM_BA 0x4C R W OSD Stream Frame Buffer Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved OSD_FF 10 8 23 22 21 20 19 18 17 16 O...

Page 1145: ...CR0 1 0 Bits Description 31 24 Reserved Reserved 23 16 BLINK_VCNT OSD Blinking Cycle Time An 8 bit value specifies the OSD blinking cycle time unit Vsync 15 10 Reserved Reserved 9 BLI_ON OSD Blinking...

Page 1146: ...970 TECHNICAL REFERENCE MANUAL 11 Reserved 1 0 OCR0 Video OSD Overlay Control 0 When VA_EN DCCS 1 1 OSD_EN DCCS 2 1 CKEY_ON OSD_OVERLAY 8 1 Display region within OSD window color key condition un matc...

Page 1147: ...y Pattern Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 OSD_CKEY 23 16 15 14 13 12 11 10 9 8 OSD_CKEY 15 8 7 6 5 4 3 2 1 0 OSD_CKEY 7 0 Bits Description 31 24 Reserved...

Page 1148: ...erlay Color Key Mask Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 OSD_CMASK 23 16 15 14 13 12 11 10 9 8 OSD_CMASK 15 8 7 6 5 4 3 2 1 0 OSD_CMASK 7 0 Bits Description 3...

Page 1149: ...imum value of ending address OSK_SKIP1_YE is OSD_SKIP1_YS 1 Register Offset R W Description Reset Value OSD_SKIP1 LCM_BA 0x5C R W OSD Window Skip1 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved...

Page 1150: ...imum value of ending address OSK_SKIP2_YE is OSD_SKIP2_YS 1 Register Offset R W Description Reset Value OSD_SKIP2 LCM_BA 0x60 R W OSD Window Skip2 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved...

Page 1151: ...e ranging from 1 0 to 7 99999 in fractional steps There is only one mode of horizontal up scaling by duplication Register Offset R W Description Reset Value OSD_SCALE LCM_BA 0x64 R W OSD Scaling Contr...

Page 1152: ...erved 23 22 21 20 19 18 17 16 Reserved HC_TIP_Y 5 0 15 14 13 12 11 10 9 8 Reserved HC_TIP_X 5 0 7 6 5 4 3 2 1 0 Reserved HC_MODE 2 0 Bits Description 31 22 Reserved Reserved 21 16 HC_TIP_Y Y position...

Page 1153: ...26 25 24 Reserved HC_Y 10 8 23 22 21 20 19 18 17 16 HC_Y 7 0 15 14 13 12 11 10 9 8 Reserved HC_X 10 8 7 6 5 4 3 2 1 0 HC_X 7 0 Bits Description 31 27 Reserved Reserved 26 16 HC_Y Y position of hardwa...

Page 1154: ...Reference Manual Publication Release Date Dec 15 2015 1154 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL HC_TIP_X HC_TIP_Y Hardware Cursor Block width Hardware Cursor Block Height HC_TIP_X HC_TIP_...

Page 1155: ...g Register Offset R W Description Reset Value HC_WBCTRL LCM_BA 0x74 R W Hardware Cursor Window Buffer Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved HC_FF 10 8 23 22 21 20 19 18 17 16 H...

Page 1156: ...or data stream Register Offset R W Description Reset Value HC_BADDR LCM_BA 0x78 R W Hardware Cursor Memory Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 HC_BADDR 31 24 23 22 21 20 19 18 17...

Page 1157: ...ding to bpp value 0 Register Offset R W Description Reset Value HC_COLOR0 LCM_BA 0x7C R W Hardware Cursor Color RAM 0 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 HC_C...

Page 1158: ...ding to bpp value 1 Register Offset R W Description Reset Value HC_COLOR1 LCM_BA 0x80 R W Hardware Cursor Color RAM 1 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 HC_C...

Page 1159: ...ding to bpp value 2 Register Offset R W Description Reset Value HC_COLOR2 LCM_BA 0x84 R W Hardware Cursor Color RAM 2 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 HC_C...

Page 1160: ...lue HC_COLOR3 LCM_BA 0x88 R W Hardware Cursor Color RAM 3 Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 HC_COLOR3_R 15 14 13 12 11 10 9 8 HC_COLOR3_G 7 6 5 4 3 2 1 0 HC...

Page 1161: ...Supports CCIR601 YCbCr color range scale to full YUV color range Supports 4 packaging format for packet data output YUYV Y only RGB565 RGB555 Supports YUV422 planar data output Supports the CROP func...

Page 1162: ...1 4 Basic Configuration Before using Capture Sensor interface it s necessary to configure related pins as the capture function and enable CAP s clock For Capture Sensor interface related pin configura...

Page 1163: ...7 0 Planar scaling down PLNDSVNL CAP_PLNSL 31 24 PLNDSVML CAP_PLNSL 23 16 PLNDSHNL CAP_PLNSL 15 8 PLNDSHML CAP_PLNSL 7 0 PLNDSVNLH CAP_PLNSM 31 24 PLNDSVMH CAP_PLNSM 23 16 PLNDSHNH CAP_PLNSM 15 8 PLND...

Page 1164: ...ASEADDR CAP_PKTBA0 31 0 block and the center of MDYADDR CAP_MDYADDR 31 0 block is greater than MDTHR CAP_MD 20 16 the first bit will change to 1 and other bits will be different as shown in the follow...

Page 1165: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1165 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL Figure 1 5 MDSM MD 9 is set to 1 and MDBS MD 8 is set to 0...

Page 1166: ...CAP_PLNSL CAP_BA 0x2C R W Planar Scaling Vertical Horizontal Factor Register LSB 0x0000_0000 CAP_FRCTL CAP_BA 0x30 R W Scaling Frame Rate Factor Register 0x0000_0000 CAP_STRIDE CAP_BA 0x34 R W Frame O...

Page 1167: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1167 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 31 7 Register Description...

Page 1168: ...re Interface Reset 0 Capture interface reset Disabled 1 Capture interface reset Enabled 23 21 Reserved Reserved 20 UPDATE Update Register at New Frame 0 Update register at new frame Disabled 1 Update...

Page 1169: ...Manual Publication Release Date Dec 15 2015 1169 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 2 1 Reserved Reserved 0 CAPEN Image Capture Interface Enable 0 Image Capture Interface Disabled 1 Imag...

Page 1170: ...k Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in ccir 656 mode 0 Field by blank Disabled 1 Field by blank Enabled 17 13 Reserved Reserved 12 11 COLORCTL Special COLOR...

Page 1171: ...ensor input data Byte 0 1 2 3 is Y0 V0 Y1 U0 10 Sensor input data Byte 0 1 2 3 is U0 Y0 V0 Y1 11 Sensor input data Byte 0 1 2 3 is V0 Y0 U0 Y1 If INFMT CAP_PAR 0 1 RGB565 00 Sensor input data Byte 0 i...

Page 1172: ...0 CAP_MD finish interrupt Disabled 1 CAP_MD finish interrupt Enabled 19 ADDRMIEN Address Match Interrupt Enable 0 Address match interrupt Disabled 1 Address match interrupt Enabled 18 Reserved Reserve...

Page 1173: ...Release Date Dec 15 2015 1173 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL If this bit shows 1 Transfer Error occurred Write 1 to clear it 0 VINTF Video Frame End Interrupt If this bit shows 1 re...

Page 1174: ...nt Posterizing Factor Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 YCOMP 15 14 13 12 11 10 9 8 UCOMP 7 6 5 4 3 2 1 0 VCOMP Bits Description 31 24 Reserved Reserved 23...

Page 1175: ...DTHR 15 14 13 12 11 10 9 8 Reserved MDDF MDSM MDBS 7 6 5 4 3 2 1 0 Reserved MDEN Bits Description 31 21 Reserved Reserved 20 16 MDTHR Motion Detection Differential Threshold 15 12 Reserved Reserved 11...

Page 1176: ...ddress Register CAP_MDADDR Register Offset R W Description Reset Value CAP_MDADDR CAP_BA 0x14 R W Motion Detection Output Address Register 0x0000_0000 31 30 29 28 27 26 25 24 MDADDR 23 22 21 20 19 18...

Page 1177: ...Register CAP_MDYADDR Register Offset R W Description Reset Value CAP_MDYADDR CAP_BA 0x18 R W Motion Detection Temp Y Output Address Register 0x0000_0000 31 30 29 28 27 26 25 24 MDYADDR 23 22 21 20 19...

Page 1178: ...Reset Value CAP_SEPIA CAP_BA 0x1C R W Sepia Effect Control Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 UCOMP 7 6 5 4 3 2 1 0 VCOMP Bits...

Page 1179: ...eset Value CAP_CWSP CAP_BA 0x20 R W Cropping Window Starting Address Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved CWSADDRV 23 22 21 20 19 18 17 16 CWSADDRV 15 14 13 12 11 10 9 8 Reserved CWSA...

Page 1180: ...S Register Offset R W Description Reset Value CAP_CWS CAP_BA 0x24 R W Cropping Window Size Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved CWH 23 22 21 20 19 18 17 16 CWH 15 14 13 12 11 10 9 8 R...

Page 1181: ...rtical Factor M Lower 8 bit Specify the lower 8 bit of denominator part M of the vertical scaling factor The lower 8 bit will be cascaded with higher 8 bit PKDSVMH to form a 16 bit denominator M of ve...

Page 1182: ...ertical Factor M Lower 8 bit Specify the lower 8 bit of denominator part M of the vertical scaling factor The lower 8 bit will be cascaded with higher 8 bit PNDSVMH to form a 16 bit denominator M of v...

Page 1183: ...N of the vertical scaling factor Please refer to the register CAP_PKTSL to check the cooperation between these two registers 23 16 PKTSVMH Packet Scaling Vertical Factor M Higher 8 bit Specify the lo...

Page 1184: ...her 8 bit of numerator part N of the vertical scaling factor For detailed programming please refer to the register CAP_PLNSL 23 16 PLNSVMH Planar Scaling Vertical Factor M Higher 8 bit Specifies the l...

Page 1185: ...26 25 24 Reserved 23 22 21 20 19 28 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved FRN 7 6 5 4 3 2 1 0 Reserved FRM Bits Description 31 14 Reserved Reserved 13 8 FRN Scaling Frame Rate Factor N Specify...

Page 1186: ...ut Pixel Stride Width Register 0x0000_0000 31 30 29 28 27 26 25 24 Reserved PLNSTRIDE 23 22 21 20 19 28 17 16 PLNSTRIDE 15 14 13 12 11 10 9 8 Reserved PKTSTRIDE 7 6 5 4 3 2 1 0 PKTSTRIDE Bits Descript...

Page 1187: ...r 0x070D_0507 31 30 29 28 27 26 25 24 OVF Reserved PKTFTH 23 22 21 20 19 18 17 16 Reserved PLNYFTH 15 14 13 12 11 10 9 8 Reserved PLNUFTH 7 6 5 4 3 2 1 0 Reserved PLNVFTH Bits Description 31 OVF FIFO...

Page 1188: ...ter CAP_CMPADDR Register Offset R W Description Reset Value CAP_CMPADDR CAP_BA 0x40 R W Compare Memory Base Address Register 0xFFFF_FFFC 31 30 29 28 27 26 25 24 CMPADDR 23 22 21 20 19 18 17 16 CMPADDR...

Page 1189: ...mory Address Register CAP_CURADDRP Register Offset R W Description Reset Value CAP_CURADDRP CAP_BA 0x50 R Current Packet System Memory Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CURADDR 23 2...

Page 1190: ...ory Address Register CAP_CURADDRY Register Offset R W Description Reset Value CAP_CURADDRY CAP_BA 0x54 R Current Planar Y System Memory Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CURADDR 23...

Page 1191: ...ory Address Register CAP_CURADDRU Register Offset R W Description Reset Value CAP_CURADDRU CAP_BA 0x58 R Current Planar U System Memory Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CURADDR 23...

Page 1192: ...ory Address Register CAP_CURADDRV Register Offset R W Description Reset Value CAP_CURADDRV CAP_BA 0x5C R Current Planar V System Memory Address Register 0x0000_0000 31 30 29 28 27 26 25 24 CURADDR 23...

Page 1193: ...CAP_PKTBA0 Register Offset R W Description Reset Value CAP_PKTBA0 CAP_BA 0x60 R W System Memory Packet Base Address 0 Register 0x0000_0000 31 30 29 28 27 26 25 24 BASEADDR 23 22 21 20 19 18 17 16 BAS...

Page 1194: ...CAP_PKTBA1 Register Offset R W Description Reset Value CAP_PKTBA1 CAP_BA 0x64 R W System Memory Packet Base Address 1 Register 0x0000_0000 31 30 29 28 27 26 25 24 BASEADDR 23 22 21 20 19 18 17 16 BAS...

Page 1195: ...ter CAP_YBA Register Offset R W Description Reset Value CAP_YBA CAP_BA 0x80 R W System Memory Planar Y Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 BASEADDR 23 22 21 20 19 18 17 16 BASEAD...

Page 1196: ...ter CAP_UBA Register Offset R W Description Reset Value CAP_UBA CAP_BA 0x84 R W System Memory Planar U Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 BASEADDR 23 22 21 20 19 18 17 16 BASEAD...

Page 1197: ...ter CAP_VBA Register Offset R W Description Reset Value CAP_VBA CAP_BA 0x88 R W System Memory Planar V Base Address Register 0x0000_0000 31 30 29 28 27 26 25 24 BASEADDR 23 22 21 20 19 18 17 16 BASEAD...

Page 1198: ...suitable to act as touch screen controller Battery voltage detection could be easily accomplished by the SAR ADC It has keypad interrupt signal generator 5 32 2 Features Resolution 12 bit resolution...

Page 1199: ...ster ADC Control Interface APB Bus KEYPAD Resistor divider switch Bandgap Internal SAR ADC Internal SAR ADC INT_TC INT_TC AVDD33 AVDD33 VREF VREF BUF BUF 2 5V 2 5V PULLUP PULLUP XP_EN XP_EN XP XP YP Y...

Page 1200: ...4LSB 4094LSB 4095LSB 4095LSB 4096LSB 4096LSB 0000 0000 0001 0000 0000 0001 0000 0000 0010 0000 0000 0010 0000 0000 0011 0000 0000 0011 0000 0000 0100 0000 0000 0100 0000 0000 0000 0000 0000 0000 1111...

Page 1201: ...creen it could connect to lower right electrode 111 XP ADC analog input If used in 4 wire touch screen it should connect to the positive end of X axis If used in 5 wire touch screen it could connect t...

Page 1202: ...put REF_SEL should be set to 00 VREF and AGND For 4 wire 5 wire touch Screen Y axis conversion REF_SEL could be set to 01 For 4 wire 5 wire touch Screen X axis conversion REF_SEL could be set to 10 Ot...

Page 1203: ...ase make sure Res1 20K ohm and Res2 5 6 Res1 Moreover a 0 01uF cap is recommended at A_2 on board If a user doesn t need the interrupt generator please ignore the requirement for Res1 and Res2 4 wire...

Page 1204: ...om Plate Bottom Plate YP YP VSENSE VSENSE XM XM YM YM Top Plate Top Plate Figure 5 32 7 5 wire Touch Screen Connection Diagram 4 wire Pressure Measurement 5 32 5 10 To distinguish pen or finger touch...

Page 1205: ...equires knowing both the X plate and Y plate resistance measurement of X Position and Y Position and Z1 Use the following Equation to calculate the touch resistance For ADC configure register Z_EN ADC...

Page 1206: ...ure Data 0x0000_0000 ADC_DATA ADC_BA 0x28 R ADC Normal Conversion Data 0x0000_0000 ADC_VBATDATA ADC_BA 0x2C R ADC Battery Detection Data 0x0000_0000 ADC_KPDATA ADC_BA 0x30 R ADC Key Pad Data 0x0000_00...

Page 1207: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1207 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 32 7 Register Description...

Page 1208: ...Keypad Press Wake Up Enable 0 Disable key press wake up 1 Enable key press wake up 9 PEDE_EN Pen Down Event Enable 0 Disable pen down event interrupt 1 Enable pen down event interrupt 8 MST Menu Star...

Page 1209: ...ion Release Date Dec 15 2015 1209 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 1 VBG_EN ADC Internal Bandgap Power Control 0 Power down internal bandgap 1 Power on internal bandgap 0 AD_EN ADC Pow...

Page 1210: ...nd the ADC start signal period to get more sampling time for precise conversion 22 HSPEED High Speed Enable Enable ADC to high speed mode 21 DISZMAVEN Display Z Mean Average Enable Pressure Mean avera...

Page 1211: ...C clock 15 1024 ADC clock 15 11 Reserved Reserved 10 SELFT_EN Selft Test Enable Selft test function enable 9 KPC_EN Keypad Press Conversion Enable Keypad press conversion function enable 8 VBAT_EN Vol...

Page 1212: ...cal Reference Manual Publication Release Date Dec 15 2015 1212 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 1 Z_EN Press Enable Press measure function enable 0 T_EN Touch Enable Touch detection fu...

Page 1213: ...ad press up event detection interrupt enable 4 WKP_IEN Wake Up Keypad Press Interrupt Enable Wake up keypad press detection interrupt enable 3 WKT_IEN Wake Up Touch Interrupt Enable Wake up touch dete...

Page 1214: ...Reserved Reserved 13 SELFT_F Self test Conversion Finish Function menu self test conversion finish Note set by hardware and write 1 to clear this bit 12 KPC_F Keypad Press Conversion Finish Function m...

Page 1215: ...tatus indicator Note set by hardware and write 1 to clear this bit 3 KPUE_F Keypad Press Up Event Flag keypad press up event status indicator Note set by hardware and write 1 to clear this bit 2 PEDE_...

Page 1216: ...ADC_WKISR ADC_BA 0x10 R ADC Wake Up Interrupt Status Register 0x0000_0000 Bits Description 31 2 Reserved Reserved 1 WPEDE_F Wake Up Pen Down Event Flag Pen down event wake up status indicator 0 WKPE_...

Page 1217: ...3 2 1 0 ADC_XDATA Bits Description 31 28 Reserved Reserved 27 16 ADC_YDATA ADC Y Data When T_EN ADC_CONF 0 in ADC_FM register is set the touch y position will be stored in this register Note If the DI...

Page 1218: ...sure Z2 will be stored in this register Note If the DISZMAVEN ADC_CONF 21 1 both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ADC_ZSORT3 15 12 Reserved Reserved 11 0 AD...

Page 1219: ...Reset Value ADC_DATA ADC_BA 0x28 R ADC Normal Conversion Data 0x0000_0000 Bits Description 31 12 Reserved Reserved 11 0 ADC_DATA ADC Data When NAC_EN ADC_CONF 2 in ADC_FM is enable the AD converting...

Page 1220: ...ue ADC_VBATDATA ADC_BA 0x2C R ADC Battery Detection Data 0x0000_0000 Bits Description 31 12 Reserved Reserved 11 0 ADC_VBATDATA ADC Voltage Battery Data When VBAT_EN ADC_CONF 8 in ADC_FM register is e...

Page 1221: ...n Reset Value ADC_KPDATA ADC_BA 0x30 R ADC Key Pad Data 0x0000_0000 Bits Description 31 12 Reserved Reserved 11 0 ADC_KPDATA ADC Key Pad Data When KPC_EN ADC_CONF 9 in ADC_FM register is enable the ke...

Page 1222: ...1 28 Reserved Reserved 27 16 ADC_AGND ADC Self test AGND Data When SELFT_EN ADC_CONF 10 in ADC_FM register is enable the AGND self test result is store in this register 15 12 Reserved Reserved 11 0 AD...

Page 1223: ...C_XYSORT0 ADC_BA 0x1F4 R ADC Touch XY Position Mean Value Sort 0 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Y_SORT0 Y Position Sort Data 0 Y position mean average sort data 0 15 12 Res...

Page 1224: ...C_XYSORT1 ADC_BA 0x1F8 R ADC Touch XY Position Mean Value Sort 1 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Y_SORT1 Y Position Sort Data 1 Y position mean average sort data 1 15 12 Res...

Page 1225: ...C_XYSORT2 ADC_BA 0x1FC R ADC Touch XY Position Mean Value Sort 2 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Y_SORT2 Y Position Sort Data 2 Y position mean average sort data 2 15 12 Res...

Page 1226: ...C_XYSORT3 ADC_BA 0x200 R ADC Touch XY Position Mean Value Sort 3 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Y_SORT3 Y Position Sort Data 3 Y position mean average sort data 3 15 12 Res...

Page 1227: ...RT0 ADC_BA 0x204 R ADC Touch Z Pressure Mean Value Sort 0 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Z2_SORT0 Z2 Position Sort Data 0 Z2 position Mean average sort data 0 15 12 Reserve...

Page 1228: ...RT1 ADC_BA 0x208 R ADC Touch Z Pressure Mean Value Sort 1 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Z2_SORT1 Z2 Position Sort Data 1 Z2 position Mean average sort data 1 15 12 Reserve...

Page 1229: ...RT2 ADC_BA 0x20C R ADC Touch Z Pressure Mean Value Sort 2 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Z2_SORT2 Z2 Position Sort Data 2 Z2 position Mean average sort data 2 15 12 Reserve...

Page 1230: ...RT3 ADC_BA 0x210 R ADC Touch Z Pressure Mean Value Sort 3 0x0000_0000 Bits Description 31 28 Reserved Reserved 27 16 Z2_SORT3 Z2 Position Sort Data 3 Z2 position Mean average sort data 3 15 12 Reserve...

Page 1231: ...scan interrupt for chip reset If the 3 pressed keys matches with the 3 keys defined in KPI3KCONF it will generate an chip reset depend on the EN3KYRST KPI3KCONF 24 setting The interrupt is generated w...

Page 1232: ...CLOCK Prescalar ROW Counter ROW Generation 5 3 Encoder Row Column Buffer Control Three_Keys Buffers Low Power Wakeup Comparator Wakeup Register Comparator DBT 7 0 Debounce Counter Status Register KPI_...

Page 1233: ...ers The keypads actually consist of a number of switches connected in a row column arrangement as shown in Figure ROW0 ROW0 ROW1 ROW1 ROW2 ROW2 ROW3 ROW3 COL0 COL0 COL1 COL1 COL2 COL2 COL3 COL3 Figure...

Page 1234: ...er can find a 0 on any column pin is for the keypad button to be pressed that connects the row set to 0 to a row The controller knows which column is at a 0 level and which column reads 0 allowing it...

Page 1235: ...NF KPI_BA 0x00 R W Keypad Configuration 0x0000_0000 KPI3KCONF KPI_BA 0x04 R W Keypad 3 Keys Configuration 0x0000_0000 KPISTATUS KPI_BA 0x08 R Keypad Status 0x0000_0000 KPIRSTC KPI_BA 0x0C R W Keypad R...

Page 1236: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1236 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 5 33 7 Register Description...

Page 1237: ...is set by ROW x COL The ROW number can be set 2 3 4 000 Reserved 001 Keypad matrix ROW number is 2 010 Keypad matrix ROW number is 3 011 Keypad matrix ROW number is 4 Default 100 Reserved 101 Reserve...

Page 1238: ...g cycle row scan time prescale 32 xclock xCLOCK 1MHz 32KHz bouncing time last for 1ms for example if xCLOCK 1MHz debounce sampling cycle should choose 1024 xclock row scan time should chose 2048 xCLOC...

Page 1239: ...able Control 0 Disable the keypad interrupt 1 Enable the keypad interrupt 2 RKINTEN Release Key Interrupt Enable Control The keypad controller will generate an interrupt when the controller detects ke...

Page 1240: ...4 EN3KYRST Enable Three key Reset Setting this bit enable hardware reset when three key is detected 0 Three key function is disable 1 Three key function is enable 23 21 Reserved Reserved 20 19 K32R Th...

Page 1241: ...ved 19 16 RROWn Release Key Row Coordinate Show the row of the release key for example if key 2 x was released x 0 1 7 then RROW KPISTATUS 19 16 will show 0100 Note n 0 1 3 11 8 PROWn Press Key Row Co...

Page 1242: ...event C code example DWORD RKE PKE reg_read KPIKRE Reg_write KPIKRE RKE 2 KEY_INT Key Interrupt This bit indicates the key scan interrupt is active when any key press or release or wakeup Read 0 Not r...

Page 1243: ...Reset Period Controller 0x0000_0000 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 RSTC 7 0 Bits Description 31 8 Reserved Reserved 7...

Page 1244: ...F_FFFF 31 30 29 28 27 26 25 24 KEST37 KEST36 KEST35 KEST34 KEST33 KEST32 KEST31 KEST30 23 22 21 20 19 18 17 16 KEST27 KEST26 KEST25 KEST24 KEST23 KEST22 KEST21 KEST20 15 14 13 12 11 10 9 8 KEST17 KEST...

Page 1245: ...18 17 16 KPE27 KPE26 KPE25 KPE24 KPE23 KPE22 KPE21 KPE20 15 14 13 12 11 10 9 8 KPE17 KPE16 KPE15 KPE14 KPE13 KPE12 KP11 KPE10 7 6 5 4 3 2 1 0 KPE07 KPE06 KPE05 KPE04 KPE03 KPE02 KPE01 KPE00 Bits Desc...

Page 1246: ...18 17 16 KRE27 KRE26 KRE25 KRE24 KRE23 KRE22 KRE21 KRE20 15 14 13 12 11 10 9 8 KRE17 KRE16 KRE15 KRE14 KRE13 KRE12 KRE11 KRE10 7 6 5 4 3 2 1 0 KRE07 KRE06 KRE05 KRE04 KRE03 KRE02 KRE01 KRE00 Bits Des...

Page 1247: ...that is set in KPICONF 15 8 The Prescale divider counter is clocked by the divided crystal clock xCLOCK The pre scale divider number is from 1 to 256 eg If the crystal clock is 1Mhz then the xCLOCK p...

Page 1248: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1248 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL 6 PACKAGE DIMENSIONS LQFP 216L 24x24x1 4mm footprint 2 0mm 6 1...

Page 1249: ...NUC970 Technical Reference Manual Publication Release Date Dec 15 2015 1249 Revision V1 30 NUC970 TECHNICAL REFERENCE MANUAL LQFP 128L 14x14x1 4mm footprint 2 0mm 6 2...

Page 1250: ...ON HISTORY Date Revision Description 2015 5 31 1 00 Preliminary version 2015 6 25 1 10 Add new part number series NUC978YOxxY 2015 11 23 1 20 Modify NUC978YOxxY pin out including part selection guide...

Page 1251: ...secure usage includes but is not limited to equipment for surgical implementation atomic energy control instruments airplane or spaceship instruments the control or operation of dynamic brake or safet...

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