NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
NUC97
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Pulse Width Modulation (PWM)
5.12
5.12.1 Overview
This chip has one PWM controller, and it has 4 independent PWM outputs, CH0~CH3, or as 2
complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators.
Each PWM pair has one Prescaler, one clock divider, two clock selectors, two 16-bit PWM counters,
two 16-bit comparators, and one Dead-Zone generator. They are all driven by APB system clock
(PCLK) in chip. Each PWM channel can be used as a timer and issue interrupt independently.
Two channels PWM Timers in one pair share the same prescaler. The Clock divider provides each
PWM channel with 5 divided clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock
signal from clock divider which receives clock from 8-bit prescaler. The 16-bit down-counter in each
channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-
bit comparator compares PWM counter value with threshold value in register CMR (PWM_CMR[15:0])
loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM
clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is
enabled, two outputs of the corresponding PWM channel pair will be replaced by the output of Dead-
Zone generator. The Dead-Zone generator is used to control off-chip power device.
To prevent PWM driving output pin with unsteady waveform, 16-bit down-counter and 16-bit
comparator are implemented with double buffering feature. User can feel free to write data to counter
buffer register and comparator buffer register without generating glitch. When 16-bit down-counter
reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches
zero, if counter is set as periodic mode, it is reloaded automatically and start to generate next cycle.
User can set PWM counter as one-shot mode instead of periodic mode. If counter is set as one-shot
mode, counter will stop and generate one interrupt request when it reaches zero. The value of
comparator is used for pulse width modulation. The counter control logic changes the output level
when down-counter value matches the value of compare register.
5.12.2 Features
4 PWM channels with a 16-bit down counter and an interrupt each
2 complementary PWM pairs, (CH0, CH1), (CH2, CH3), with a programmable dead-zone
generator each
Internal 8-bit prescaler and a clock divider for each PWM paired channel
Independent clock source selection for each PWM channel
Internal 16-bit down counter and 16-bit comparator for each independent PWM channel
PWM down-counter supports One-shot or Periodic mode