NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
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4.
Set the SDRAM controller in initialization state. This is accomplished by writing 1 to InitState
(SDIC_CMD[0]).
5.
Set the CKE_H (SDIC_CMD[1]) to be 1 to force the CKE at high state.
6.
Apply a PRECHARGE ALL command. This is accomplished by writing 1 to PALL_CMD
(SDIC_CMD[2]). The PALL_CMD bit will auto clear after the PRECHARGE command
completed.
7.
Apply a MRS (Mode Register Set) command to EMR2 (Extended Mode Register 2). This is
accomplished by writing appropriate value to the register SDIC_EMR2 (SDRAM EXTEND
MODE Register 2).
8.
Apply a MRS (Mode Register Set) command to EMR3 (Extended Mode Register 3). This is
accomplished by writing appropriate value to the register SDIC_EMR3 (SDRAM EXTEND
MODE Register 3).
9.
Apply a MRS (Mode Register Set) command to EMR (Extended Mode Register) to enable
DLL. This is accomplished by writing appropriate value to the register SDIC_EMR (SDRAM
EXTEND MODE Register).
10. Apply a MRS (Mode Register Set) command to MR (Mode Register) with A8 high to set
DDR SDRAM in normal operation with resetting the DLL. This is accomplished by writing
appropriate value with bit [8] high to the register SDIC_MR (SDRAM MODE Register).
11. Apply a PRECHARGE ALL command. This is accomplished by writing 1 to PALL_CMD
(SDIC_CMD[2]). The PALL_CMD bit will auto clear after the PRECHARGE command
completed.
12. Apply two or more AUTOREFRESH commands. This is accomplished by writing 1 to
REF_CMD (SDIC_CMD[3]) twice or more. The REF_CMD is auto cleared after SDRAM
controller completes each CAS-BEFORE-RAS refresh command.
13. Apply a MRS (Mode Register Set) command to MR (Mode Register) with A8 low to set DDR
SDRAM in normal operation without resetting the DLL. This is accomplished by writing
appropriate value with bit [8] low to the register SDIC_MR (SDRAM MODE Register).
14. Apply a MRS (Mode Register Set) command to EMR (Extended Mode Register) to enable
OCD default state. This is accomplished by writing appropriate value with 3is accomplished
by to the register SDIC_EMR (SDRAM EXTEND MODE Register).
15. Apply a MRS (Mode Register Set) command to EMR (Extended Mode Register) to enable
OCD exit state. This is accomplished by writing appropriate value with 3is accomplished by
to the register SDIC_EMR (SDRAM EXTEND MODE Register).
16. Apply 200 dummy clocks to meet minimum latency delay between MRS and normal
operation command (ACTIVE, READ, WRITE
…). This is accomplished by inserting a period
of delay..
17. SDRAM initialization sequence completed and SDRAM controller exit initialization state and
enter normal operating mode. This is accomplished by writing 0 to both InitState
(SDIC_CMD[0]) and CKE_H (SDIC_CMD[1]).
System Memory Address and SDRAM Address Mapping
5.5.5.3
The table shown below indicates how the 32-bit system memory address be mapped to SDRAM
address. All the SDRAM devices listed below are 16-bit data bus width.
For DDR SDRAM
Type
R X C R/C BA1 BA0 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00