NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
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For example, the timer compare register (ETMRn_CMPR) value is set as 80, first. (The timer
compare register (ETMRn_CMPR) should be less than 2
24
and be greater than 1). Once the timer
counter value (ETMRn_DR value) reaches to 80, ETMR_IS (ETMRn_ISR[0] timer interrupt status)
will set to 1 and ETMR_EN (ETMRn_CTL[0] timer counter enable bit) is still kept at 1 (counting
enable continuously). Next, user clears the ETMR_IS (ETMRn_ISR[0] timer interrupt status) and
reprograms timer compare register (ETMRn_CMPR) value as 200, then ETMR_IS
(ETMRn_ISR[0] timer interrupt status) will set to 1 again when timer counter value (ETMRn_DR
value) reaches to 200. At last, user clears ETMR_IS (ETMRn_ISR[0] timer interrupt status) and
reprograms timer compare register (ETMRn_CMPR) value as 500, then ETMR_IS
(ETMRn_ISR[0] timer interrupt status) will set to 1 again when timer counter value (ETMRn_DR
value) reaches to 500. In this mode, when the timer counter value (ETMRn_DR value) continues
counting up to 2
24
-1, then recount up from 0 continuously. The timer counter value (ETMRn_DR
value) is always keeping up counting even if ETMR_IS (ETMRn_ISR[0] timer interrupt status) is 1.
Therefore, this operation mode is called as Continuous Counting mode.
TMRx_DR
= 0
Set
TMRx_CMPR
= 80
TMRx_DR = 80
and TMR_IS = 1
Clear TMR_IS
as 0 and Set
TMRx_CMPR
= 200
TMRx_DRn from 2
24
-1 to 0
TMRx_DR
= 100
TMRx_DR
= 200
TMRx_DR
= 300
TMRx_DR
= 400
TMRx_DR
= 500
TMRx_DR =
2
24
-1
TMRx_DR = 200
and TMR_IS = 1
Clear TMR_IS
as 0 and Set
TMRx_CMPR
= 500
TMRx_DR = 500
and TMR_IS = 1
Clear TMR_IS
as 0 and Set
TMRx_CMPR
= 80
Figure 5.11-3 Timer Clock Controller Diagram
Timer Counter Capture/Reset Function
5.11.5.5
In this mode, Timer will monitor the transition of external pin to save the 24-bit counter value or
reset the 24-bit counter.
If TCAP_MODE is 0, the transition on external pin is used as timer counter capture function. In
this mode, if CAP_CNT_MOD is 0, the free-counting mode, 24-bit up-counting timer will keep
counting continuously. And when the transition of external pin matches the TCAP_EDGE setting,
the value of 24-bit up-counting timer will be saved into register ETMRn_TCAP. If CAP_CNT_MOD
is 1, the trigger-counting mode, 24-bit up-counting timer will keep its value at zero. Once the
transition of external pin matches the 1
st
transition of TCAP_EDGE setting, the 24-bit up-counting
timer will start counting. And then if the transition of external pin matches the 2
nd
transition of
TCAP_EDGE setting, the 24-bit up-counting timer will stop counting. And its value will be saved
into register ETMRn_TCAP.
If TCAP_MODE is 1, the transition on external pin is used as timer counter reset function. In this
mode, once the transition of external pin matches the TCAP_EDGE setting, the 24-bit up-counting
timer will be reset.
To detect the transition of external pin, the timer circuit implements the de-bounce circuit for
external pin. Based on the result of de-bounce circuit and external pin, the rising-edge or falling-
