NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
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Revision V1.30
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The warm reset sequence is showed as follows.
1.
Set SC_RST to low by programming RSTSTS (SC_PINCTL[18]) to
‘0’.
2.
Set SC_DAT to high by programming DATSTS (SC_PINCTL[16]) to
‘1’.
3.
Set SC_RST to high by programming RSTSTS (SC_PINCTL[18]) to
‘1’.
The warm reset
sequence
can be controlled in two ways. The procedure is shown as follows.
Software Timing Control:
Set SC_PINCTL and SC_TMRCTLx (x = 0, 1, 2) to process the warm reset sequence.
SC_RST and SC_DATA pin state can be programmed by SC_PINCTL. The warm reset
sequence timing can be controlled by setting SC_TMRCTLx (x = 0, 1, 2). This
programming procedure provides user has a flexible timing setting for warm reset
sequence.
Hardware Timing Control:
Set WARSTEN (SC_ALTCTL[4]) to ‘1’ and the interface will perform the warm reset
sequence by hardware. The SC_RST to SC_DATA reception mode (T4) and SC_DATA
reception mode to SC_RST assert (T5) can be selected by programming INITSEL
(SC_ALTCTL[9:8]). This programming procedure provides user has a simple setting
for warm reset sequence.
Following is THE warm reset control sequence by hardware:
1.
Set warm reset timing by setting INITSEL (SC_ALTCTL[9:8]).
2.
Select TMR0 by setting TMRSEL (SC_CTL[14:13]) register (TMRSEL can be set to
‘01’, ‘10’, or ‘11’).
3.
Set operation mode OPMODE (SC_TMRCTL0[27:24]) to
‘0011’ and give an Answer
to Request value by setting CNT (SC_TMRCTL0[23:0]) register.
4.
SetCNTEN0 (SC_ALTCTL[5]) and WARSTEN (SC_ALTCTL[4]) to start counting.
5.
When hardware de-asserts SC_RST to high, hardware will generate an interrupt
INTIF (SC_INTSTS[8]) to CPU at the same time (INITIEN (SC_INTEN[8]) =
‘1’).
6.
If the TMR0 decrease the counter to “0” (start from SC_RST) and the card does not
response ATR before that time, hardware will generate interrupt TMR0IF
(SC_INTSTS[3]) to CPU.