NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 151 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
5.3.5 Registers Map
R: read only, W: write only, R/W: both read and write.
Register
Offset
R/W
Description
Reset Value
CLK Base Address:
CLK_BA = 0xB000_0200
CLK_PMCON
0x000 R/W
Power Management Control Register
0xFFFF_FF03
CLK_HCLKEN
0x010 R/W
AHB Devices Clock Enable Control Register
0x0000_0527
CLK_PCLKEN0
0x018 R/W
APB Devices Clock Enable Control Register 0
0x0000_0000
CLK_PCLKEN1
0x01C R/W
APB Devices Clock Enable Control Register 1
0x0000_0000
CLK_DIVCTL0
0x020 R/W
Clock Divider Control Register 0
0x0100_00XX
CLK_DIVCTL1
0x024 R/W
Clock Divider Control Register 1
0x0000_0000
CLK_DIVCTL2
0x028 R/W
Clock Divider Control Register 2
0x0000_0000
CLK_DIVCTL3
0x02C R/W
Clock Divider Control Register 3
0x0000_0000
CLK_DIVCTL4
0x030 R/W
Clock Divider Control Register 4
0x0000_0000
CLK_DIVCTL5
0x034 R/W
Clock Divider Control Register 5
0x0000_0000
CLK_DIVCTL6
0x038 R/W
Clock Divider Control Register 6
0x0000_0000
CLK_DIVCTL7
0x03C R/W
Clock Divider Control Register 7
0x0000_0000
CLK_DIVCTL8
0x040 R/W
Clock Divider Control Register 8
0x0000_0500
CLK_DIVCTL9
0x044 R/W
Clock Divider Control Register 9
0x0000_0000
CLK_APLLCON
0x060 R/W
APLL Control Register
0x1000_0015
CLK_UPLLCON
0x064 R/W
UPLL Control Register
0xX000_0015
CLK_PLLSTBC
NTR
0x080 R/W
PLL Stable Counter and Test Clock Control Register
0x0000_1800
