Nuvoton NUC970 series, Technical Reference Manual

Page: 371 / 1251

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 371 - Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
WDT Alternative Control Register (WDT_ALTCTL)
Register Offset R/W Description Reset Value
WDT_ALTCTL 0x04 R/W WDT Alternative Control Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved WTRDSEL
Bits Description
[31:2]
Reserved
Reserved.
[1:0] RSTDSEL
WDT Reset Delay Selection (Write Protect)
When WDT time-out happened, user has a time named WDT Reset Delay Period to
clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out
reset happened. User can select a suitable setting of RSTDSEL for different WDT
Reset Delay Period.
00 = WDT Reset Delay Period is 1026 * WDT_CLK.
01 = WDT Reset Delay Period is 130 * WDT_CLK.
10 = WDT Reset Delay Period is 18 * WDT_CLK.
11 = WDT Reset Delay Period is 3 * WDT_CLK.
Note1: This bit is write protected. Refer to the REGWRPROT register.
Note2: This register will be reset to 0 if WDT time-out reset happened.