NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 64 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
5.2.3 System Power Distribution
In this chip, the power distribution is divided into six segments.
Analog power from AVDD provides 3.3V voltage to analog components operation.
These analog components including POR33, 12-bit SAR-ADC, LVD and LVR.
Digital power from CORE_VDD provides 1.2V voltage to POR12, APLL, APLL, SRAM
(56 kB) and all digital logic except RTC.
Digital power from RTC_VDD provides 3.3V voltage to LXT and RTC logic.
USB PHY power from USB0_VDD, USBPLL0_VDD provides 3.3V and 1.2
respectively to USB 2.0 PHY 0, while USB1_VDD, USBPLL1_VDD provides 3.3V and
1.2 respectively to USB 2.0 PHY 1.
IO power from DDR_VDD provides 1.8V to I/O pins used to connect DDR2 SDRAM.
IO power from IO_VDD provides 3.3V to MTP memory, HXT and I/O pins (PA ~ PJ).
The following diagram shows the power distribution of the NUC970 series.
LXT
Ext. Crystal
Osc.
32.768 kHz
RTC_VDD (3.3V)
X
3
2
_
IN
X
3
2
_
O
U
T
S
Y
S
_
P
W
R
E
N
S
Y
S
_
n
W
A
K
E
U
P
RTC
with
64B Spare
Register
12-bit
SAR-ADC
Low
Voltage
Reset
Low
Voltage
Detection
POR33
AVDD (3.3V)
POR12
APLL
UPLL
SRAM
(56 kB)
Digital Logic
HXT
Ext. Crystal
Osc.
12 MHz
Normal IO Cell
DDR IO Cell
USB 2.0 PHY 0
USB 2.0 PHY 1
MTP
DDR_VDD
(1.8V)
IO_VDD (3.3V)
XT1_IN
XT1_OUT
CORE_VDD (1.2V)
U
S
B
0
_
D
P
U
S
B
0
_
D
M
U
S
B
1
_
D
P
U
S
B
1
_
D
M
U
S
B
0
_
V
D
D
(
3
.3
V
)
U
S
B
P
L
L
0
_
V
D
D
(
1
.8
V
)
U
S
B
1
_
V
D
D
(
3
.3
V
)
U
S
B
P
L
L
1
_
V
D
D
(
1
.8
V
)
Figure 5.2-1 NUC970 Series Power Distribution Diagram
