NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 530 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
I2C n Prescale Register (I2Cn_DIVIDER)
Register
Offset
R/W
Description
Reset Value
I2Cn_DIVIDER
n=0,1
0x004
R/W
I2C n Clock Prescale Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
DIVIDER[15:8]
7
6
5
4
3
2
1
0
DIVIDER[7:0]
Bits
Description
[15:0]
DIVIDER
Clock Prescale Register
It is used to prescale the SCL clock line. Due to the structure of the I
2
C interface, the core uses a
5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus
1). Change the value of the prescale register
only when the “I2C_EN” bit is cleared.
Example: pclk = 32MHz, desired SCL = 100KHz.
)
(
3
)
(
63
1
100
5
32
hex
F
dec
KHz
MHz
prescale
