NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 169 -
Revision V1.30
NUC97
0
T
E
CHNIC
A
L
RE
F
E
RE
N
CE
MA
NUA
L
Clock Divider Control Register 4 (CLK_DIVCTL4)
Register
Offset
R/W
Description
Reset Value
CLK_DIVCTL4
0x030
R/W
Clock Divider Control Register 4
0x0000_0000
31
30
29
28
27
26
25
24
UART3_N
UART3_S
UART3_SDIV
23
22
21
20
19
18
17
16
UART2_N
UART2_S
UART2_SDIV
15
14
13
12
11
10
9
8
UART1_N
UART1_S
UART1_SDIV
7
6
5
4
3
2
1
0
UART0_N
UART0_S
UART0_SDIV
Bits
Description
[31:29]
UART3_N
UART3 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART3.
The actual clock divide number is (U 1). So,
ECLKuart3 = UART3_SrcCLK / (U 1)
[28:27]
UART3_S
UART3 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART3 controller.
00 = UART3_SrcCLK is from XIN
01 = Reserved
10 = UART3_SrcCLK is from ACLKOut
11 = UART3_SrcCLK is from UCLKOut
[26:24]
UART3_SDIV
UART3 Engine Source Clock Divider
This field defines the source clock divide number for clock divider of APLL and UPLL output. This
field only takes effect while the UART3_S (CLK_DIVCTL4[28:27
]) is 2’b10 (APLL) or 2’b11
(UPLL).
If UART3_S (CLK_DIVCTL4[28:27
]) is 2’b10,
ACLKOut = APLLFout ÷ (UART 1)
If UART3_S (CLK_DIVCTL4[28:27
]) is 2’b11,
UCLKOut = UPLLFout ÷ (UART 1)
[23:21]
UART2_N
UART2 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART2.
The actual clock divide number is (U 1). So,
ECLKuart2 = UART2_SrcCLK / (U 1)