Nuvoton NUC970 series, Technical Reference Manual

Page: 224 / 1251

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 224 - Revision V1.30
NUC97
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SDRAM Controller Operation Mode Control Register (SDIC_OPMCTL)
Register Offset R/W Description Reset Value
SDIC_OPMCTL S 0x000 R/W SDRAM Controller Operation Mode Control Register 0x0003_04x6
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved RD2WR_CTL OEDelay LowFreq PreActBnk AutoPDn
15 14 13 12 11 10 9 8
Reserved RDBUFTH
7 6 5 4 3 2 1 0
Reserved SD_TYPE PchMode OPMode MCLKMode DRAM_EN Reserved
Bits Description
[31:19] Reserved Reserved.
[20] RD2WR_CTL
Read-to-write Turn Around Control
This bit is to insert one more turn around cycle between memory read and memory write
access to SDRA'M device.
0 = Default turn-around cycle is used.
1 = One more turn-around cycle is inserted between memory read and write access.
[19] OEDelay
Output Enable Delay Half MCLK
This bit control the data output enable signal. If set high, the data output enable will be turned
off half MCLK earlier.
0 = Default data output enable timing.
1 = Turn off data output enable half MCLK earlier.
[18] LowFreq
Low Frequency Mode
For low power DDR (LPDDR) SDRAM, the valid read data outputted by LPDDR SDRAM is not
ready at clock edge. If this bit is enabled, the SDRAM controller will sampled read data based
on the following timing:
If CL is 2, the read data output latency will be 2*tCK+tAC.
If CL is 3, the read data output latency will be tCK+tAC.
CL: CAS Latency.
tCK: Clock cycle time for LPDDR SDRAM.
tAC: Data output latency from clock for LPDDR SDRAM.
This bit only takes effect when the SD_TYPE is selected in DDR or DDR2 SDRAM.
0 = SDRAM controller sampled read data based on the DDR/DDR2 standard. (Default)
1 = SDRAM controller sampled read data based on the LPDDR standard.