Nova Electronics MCX514, User Manual

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NOVA electronics Inc. MCX514 -
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Automatic home search mode setting 2
Automatic home search mode setting 2 can be set by setting each bit of WR6 register as shown below and then writing automatic
home search mode setting 2 command (24h) into WR0 register. It specifies the logical level of deviation counter clear (nDCC)
output pulses and pulse width, enable/disable the timer between steps and timer time, real/logical position counter clear at the end
of an automatic home search, AND stop condition for the encoder Z-phase signal (nSTOP2) and home signal (nSTOP1).
D7 D6 D5 D4
H L
D15 D14 D13 D12 D11 D10 D9 D8
D3 D2 D1 D0
HTM0 HTM1 HTM2 HTME DCP0 DCP1 DCP2 DCPL RCLR LCLR SAND
WR6
①
The logical level of deviation counter clear (nDCC) output pulse and pulse width
For when deviation counter clear signal (nDCC) is output in each step, the user can specify the logical level and pulse width.
To specify the logical level, set D3 bit (DCPL) to 0: Hi pulse, 1: Low pulse
Hi Pulse Low Pulse
10 μ sec ～ 20msec
Fig. 2.5-12 The Logical Level of Deviation Counter Clear Output Pulse
Use 3bits, D6~4 (DCP2
～
DCP0) to set the pulse width. The settable pulse width is shown in the table below.
Table 2.5-7 The Pulse Width of Deviation Counter Clear Output
WR6/D6
DCP2
WR6/D5
DCP1
WR6/D4
DCP0
Pulse Width
(CLK=16MHz)
0 0 0
10 μsec
0 0 1
20 μsec
0 1 0
100 μsec
0 1 1
200 μsec
1 0 0 1 msec
1 0 1 2 msec
1 1 0 10 msec
1 1 1 20 msec