NOVA electronics Inc.
MCX514 -
47
－
47
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③
Detection signal of each step
Step 1 can be selected from nSTOP0, nSTOP1 and limit signals. Step 2 can be selected from either nSTOP1 or limit signals. Step
3 is fixed to nSTOP2 signal. The same signal can be set in Step 1 and Step 2.
The detection signal specification in Step 1 and Step 2 is shown in the table below.
Table 2.5-5 Detection Signal Specification in Step 1 and Step 2
Step 1
Step 2
D3 bit
S1G1
D2 bit
S1G0
Detection signal
D6 bit
S2SG
Detection signal
0
0
nSTOP0
0
nSTOP1
0
1
nSTOP1
1
Limit signal
1
0
Limit signal
1
1
―
If a limit signal is specified as a detection signal, the limit signal in the search direction specified by D1 bit (S1DR) in Step 1 or
D5 bit (S2DR) in Step 2 are selected. If the search direction is + direction, it becomes nLMTP
signal and If − direction, it becomes
nLMTM signal.
The logical level of an input signal that is detected must be set to Hi active or Low active by WR2 register. For more details of the
WR2 register, see chapter 6.6.
④
Deviation counter clear output and real/logical position counter clear setting
In Step2 and Step3, when a specified detection signal rises from inactive to active, the user can specify whether to output the
deviation counter clear signal (nDCC) or not.
0: Non- output, 1: Output
And at the end of Step 2, 3 and 4, the user can clear real/logical position counter.
0: Non- clear, 1: Clear
The specified bits for deviation counter clear signal (nDCC) output and real/logical position counter clear in each step are shown
in the table below.
Table 2.5-6 nDCC Output and Real/Logical Position Counter Clear Specified Bit in Each Step
Step 1
Step 2
Step 3
Step 4
Deviation counter clear signal
(nDCC) output
―
D7 bit
S2DC
D12 bit
S3DC
―
0: Non- output
1: Output
Real position counter clear
―
D8 bit
S2RC
D13 bit
S3RC
(
※
1)
0: Non- clear
1: Clear
Logical position counter clear
―
D9 bit
S2LC
D14 bit
S2LC
(
※
1)
(
※
1)
Real/logical position counter clear at the end of Step 4 (when Step 4 is executed), use the setting of automatic home search
mode setting 2 (24h) for whether or not to clear at the end of an automatic home search. See “■Automatic home search mode
setting 2” described as follows.
