Nova Electronics MCX514, User Manual

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NOVA electronics Inc. MCX514 -
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During continuous interpolation driving, when SC is 8, it indicates the pre-buffer stack is the upper limit.
And when SC is 7 and under, it is possible to write interpolation data for next node (parameters and
interpolation commands). When SC is 0, it indicates all the interpolation data was output and continuous
interpolation driving is finished.
6.12
Status Register 1: RR1
Each axis has status register RR1 individually. The host CPU specifies the status register of which axis should be accessed
depends on the axis of written command just before. Or the user can specify the axis by writing NOP command with axis
assignment.
Status register RR1 is used for displaying an interrupt factor. When an interrupt occurs, the bit with the interrupt factor becomes 1.
To generate an interrupt, interrupt Enable must be set for each factor in WR1 register.
D7 D6 D5 D4
H L
D15 D14 D13 D12 D11 D10 D9 D8 D3 D2 D1 D0
RR1
CMR1 CMR0 CMR3 CMR2 D-STA C-STA C-END D-END H-END TIMER SPLTP SPLTE SYNC0 SYNC1 SYNC2 SYNC3
Interrupt Factor
D3 ～ 0 CMR3 ～ 0
Indicates that an interrupt occurred when the comparison result of multi-purpose register MR3~0 with a
comparative object changed to meet the comparison condition.
Use multi-purpose register mode setting command (20h) to set the object which the user wants to compare
with MR3~0 and comparison condition.
D4 D-STA
Indicates that an interrupt occurred at the start of driving.
D5 C-STA
Indicates that an interrupt occurred when pulse output starts at constant speed area in acceleration /
deceleration driving
D6 C-END
Indicates that an interrupt occurred when pulse output was finished at constant speed area in acceleration /
deceleration driving.
D7 D-END
Indicates that an interrupt occurred when the driving was finished.
D8 H-END
Indicates that an interrupt occurred when the automatic home search was finished.
D9 TIMER
Indicates that an interrupt occurred when the timer expires.
D10 SPLTP
Indicates that an interrupt occurred at the
↑
of a pulse in each split pulse.
(When the split pulse logic is set to Hi pulse)
D11 SPLTE
Indicates that an interrupt occurred when the split pulse was finished.
D15 ～ 12 SYNC3 ～ 0
Indicates that an interrupt occurred when synchronous action SYNC3~0 was activated.
When one of the interrupt factors generates an interrupt, the bit of the register becomes 1, and the interrupt output signal (INT0N)
will become the Low level. If the host CPU reads RR1 register, the bit of RR1 will be cleared to 0 and the interrupt signal
(INT0N) will return to the non-active level.
[Note]
•
In 8-bit data bus, RR1L will be cleared by reading of RR1L register and RR1H will be cleared by reading of RR1H
register. RR1H will never be cleared by RR1L register and RR1L will never be cleared by RR1H register.
•
When in I2C serial interface bus, do not read RR1L and RR1H registers separately and be sure to read 2 bytes (RR1L,
RR1H) at one time.