NOVA electronics Inc.
MCX514 -
57
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57
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Example 3 Home search for a servo motor
In the case of the pulse input type servo driver, normally an encoder Z-phase signal is output from the driver (a servo amplifier).
To perform the home search with high position precision, a deviation counter in the driver must be cleared in the output timing of
the encoder Z-phase and a deviation counter clear signal must be input. The example of the home search connecting these signals
is shown below.
As shown in the figure below, the home signal (nSTOP1) is input through the interface circuit from the home sensor. The encoder
Z-phase input (nSTOP2) and the deviation counter clear output (nDCC) are connected to the servo driver through the interface
circuit.
nSTOP1
Home Sensor
MCX514
I/F
Circuit
Servo motor driver
nPP
nPM
nDCC
nECA
nECB
nSTOP2
nALARM
nINPOS
+
Pulse Output
Deviation Counter Clear
Encoder A- phase
Encoder B- phase
Encoder Z- phase
In- position
Alarm
Home
-
Pulse Output
Fig. 2.5-17 Connection of Example 3 Automatic Home Search
[Note]
•
The encoder Z-phase input must be connected to nSTOP2 of the IC. The line receiver or the high speed photo coupler
is appropriate to the interface circuit for a rapid response.
Table 2.5-14 Automatic Home Search Example 3 Operation
Step
Operation
Execution/
Non- execution
Detection
signal
Signal level
Search direction
Search speed
1
High-speed search
Execution
nSTOP1
Low active
-
direction
20,000pps
2
Low -speed search
Execution
-
direction
500pps
3
Z-phase search
Execution
nSTOP2
Low
-
direction
500pps
4
Offset drive
Execution
-
-
+
direction
20,000pps
The operation from Step 1 to Step 2 is the same as the operation
using a home signal (nSTOP1) described above.
When nSTOP1 input becomes Low in
Step 2, Step 2 ends and it proceeds
with Step 3. In Step 3, a home search
is performed at a speed of 500pps in
the
-
direction until nSTOP2
(Z-phase) signal detects Low level,
and if it detects Low level, operation
stops instantly. nDCC (deviation
counter clear) is output by the
↓
of
nSTOP2 input signal. In this case,
nDCC signal is set to output Hi pulses
of 100
μ
sec.
Fig. 2.5-18 Operation of Example 3 Automatic Home Search
In addition, when the nSTOP2 (Z-phase) signal becomes Low active in Step 3, the real position counter and logical position
counter should be set to clear them.
nSTOP1 (Home) Input
nSTOP2 (Z- phase) Input
nDCC Output
Step2
Step3
Step4
100
μ
sec
(Deviation Counter Clear)