NOVA electronics Inc. MCX514 -
163
－
163
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5.2
Signal Description
See chapter 5.3 for description of input/output logic. The input signals with – F – symbol indicates that an integral filter circuit is
available in the internal input column of this IC.
Signal Name
Pin No.
Input/Output
Signal Description
CLK
54
Input A
Clock: clock signal for internal synchronous loop of MCX514
The standard frequency is 16 MHz. This signal is for drive speed,
acceleration / deceleration and jerk. If the frequency setting is not 16 MHz,
the setting values of speed and acceleration / deceleration are different.
D15
～
D0
1
～
8,
11
～
18
Bi-directional
A
Data Bus (D15
～
D0): 3-state bi-direction 16-bit data bus
When CSN=Low and RDN=Low, these signals are for outputting.
Otherwise, they are high impedance inputs. If 8-bit data bus is used and
D15~D8 are not used, they should be connected to VDD or GND through
high impedance (about 10K
～
100 kΩ).
In I
2
C mode, can be used as general purpose input signals.
A3
～
A0
21
～
24
Input A
Address: address signal for the host CPU to access the write / read
registers
If 16-bit data bus is used, A3 cannot be used and should be connected to
GND. In I
2
C mode, A2
～
A0 are used as chip address setting pins.
SDA
25
Bi-directional
D
I2CSDA: SDA signal in I
2
C mode.
CSN/SCL
26
Input A
Chip Select / I
2
C SCL: input signal for selecting I/O device for MCX514
Set to the Low level for data reading and writing.
In I
2
C mode, used as SCL signal.
WRN
27
Input A
Write Strobe: its level is Low while data is being written to MCX514.
While WRN is Low, CSN and A3
～
A0 must be determined. Around when
WRN is up (↑), the levels of D15
～
D0 must be determined because the
data is latched in the write register when WRN is up (↑).
RDN
28
Input A
Read Strobe: its level is Low while data is being read from MCX514.
Set CSN to Low and RDN to Low, and while RDN is Low, the read register
data selected by A3
～
A0 address signals is output to the data bus.
RESETN
29
Input A
Reset: reset (return to the initial setting) signal for MCX514.
Setting RESETN to Low for more than 8 CLK cycles resets MCX514. This
IC must be reset by RESETN signal when the power is on.
[Note] If there is no clock input to MCX514, setting RESETN to Low
cannot reset this IC
EXPLSN
30
Input B
External Pulse: pulse input signal for single-step interpolation by external
signal. In single-step interpolation by external signal, EXPLSN down (
↓
)
starts the interpolation calculation and 1 interpolation pulse of each axis is
output. The width of EXPLSN on the Low level must be more than 4CLK.
[Note] EXPLSN does not have the filter function.
H16L8
/I2CRSTN
31
Input B
Hi=16bit, Low=8bit: data bus width selection for 16-bit / 8-bit
When set to Hi, 16-bit data bus is selected for processing the 16-bit data
reading / writing in IC; when set to Low, 8-bit data bus (D7~D0) is active
for data reading / writing.
In I
2
C mode, used as I
2
C Reset. Setting Low resets the I
2
C control
section
inside of the IC.
BUSMOD
32
Input B
Bus Mode: Selects CPU bus mode. When set to Hi, it is in 16bit / 8bit
parallel bus mode, and when set to Low, it is in I
2
C serial bus mode.
INT0N
33
Output B
Interrupt: outputs an interrupt signal to the host CPU. If any interrupt factor
except interpolation pre-buffer generates an interrupt, INT0N becomes
Low level. When an interrupt is released, it will return to the Hi-Z level.
INT1N
34
Output B
Interrupt: outputs an interrupt signal to the host CPU. If interrupt factor by
interpolation pre-buffer generates an interrupt, INT1N becomes Low level.
When an interrupt is released, it will return to the Hi-Z level.
