NOVA electronics Inc. MCX514 -
255
－
255
－
10.2.5 General Purpose Input / Output Signals (nPIO7
～
0)
The figure shown at the lower left hand side illustrates the delay time when nPIO7
～
0 input signals are read through RR4, 5
registers. The IC built-in filter is disabled.
The figure shown at the lower right hand side illustrates the delay time when writing nPIO7
～
0 output signals data into WR4, 5
registers.
Input Signal
RDN
D15
～
0
tDI
PIO7
～
0
tDO
WRN
D15
～
0
Symbol
Item
Min.
Max.
Unit
tDI
Input Signal
→
Data Delay Time
17
nS
tDO
WRN
↑→
Data Setup Time
23
nS
10.2.6 Split Pulse
The delay time from the rising edge of the drive pulse that starts the split pulse to when the split pulse becomes Hi (Split pulse is
positive logic).
When with starting pulse, only the first split pulse is output together with the drive pulse. The second or later split pulses are
output with 1 CLK delay from the drive pulse.
When without starting pulse, all the split pulses are output with 1 CLK delay from the drive pulse.
■
When with starting pulse is enabled in split pulse mode setting
This is, when with starting pulse is enabled in split pulse mode setting, the delay time from the rising edge of the drive pulse that
starts the split pulse to when the split pulse becomes Hi.
tDS1 is the delay time of the first split pulse. tDS2 indicates the delay time of the second or later split pulses. The second or later
split pulses are output with 1 CLK delay.
t
DS1
nPP,nPM
nSPLTP
・・・
t
DS2
t
DS2
・・・
・・・
Symbol
Item
Min.
Max.
Unit
tDS1
nPP, nPM
↑
→
nSPLTP
↑
Delay Time
20
nS
tDS2
nPP, nPM
↑
→
nSPLTP
↑
Delay Time
tCYC +20
nS
tCYC is a cycle of CLK.
■
When without starting pulse is enabled in split pulse mode setting
This is, when without starting pulse is enabled in split pulse mode setting, the delay time from the rising edge of the drive pulse
that starts the split pulse to when the split pulse becomes Hi.
nPP,nPM
nSPLTP
t
DS
CLK
t
DS
Symbol
Item
Min.
Max.
Unit
tDS
nPP, nPM
↑
→
nSPLTP
↑
Delay Time
tCYC +20
nS
tCYC is a cycle of CLK.
