NOVA electronics Inc. MCX514 -
136
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136
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(9) Check writable of next data
D12
～
D15 bits (HSTC0
～
3) of RR0 register are assigned to the value of the stack counter in 8 stages of pre-buffer, and it displays
the accumulation amount of the buffer. When the value of 4 bits is 0, it indicates an empty state, and when it is 8, it indicates a full
state and cannot write segment data anymore. When interpolation driving command is written, the stack counter is counted up by 1
and when driving currently being output is finished, the stack counter is counted down by 1.
D11 bit (CNEXT ) of RR0 register notifies the writable state of next data for continuous interpolation. After interpolation driving
starts, CNEXT bit becomes 1 while the stack counter of pre-buffer is from 1 to 7. And during 1 of this bit, the host CPU
determines that it is possible to write next data.
(10) Write the n segment data and interpolation command
It writes the data after the 9th segment during interpolation driving. The data is the same as the 1st to 8th segments described in
(4) and (5). After writing interpolation driving command, it will return to (7).
3.7.2 Continuous Interpolation by Using Interrupt
Continuous interpolation can be performed by using interrupt. When pre-buffer has free space, INT1N signal (pin number: 34)
becomes Low active and notifies the writable state of next segment data to the host CPU.
There are 2 kinds of the interruption timing that notifies the free space.
■
Interpolation interrupt setting
The interruption that notifies the free space can be set by 2 bits D14, D15 of interpolation mode setting command (2Ah).
D7
D6
D5
D4
H
L
D15
D14
D13
D12
D11
D10
D9
D8
D3
D2
D1
D0
WR6
INTA
INTB
Interpolation interrupt
When D14 bit (INTA)is set to 1, and when the stack counter of pre-buffer changes from 4 to 3, INT1N signal becomes Low active.
It notifies that about half of 8 stages of pre-buffer is empty. This is suitable for when continuous interpolation driving is performed
relatively slowly.
When D14 bit (INTA)is set to 1, and when the stack counter of pre-buffer changes from 8 to 7, INT1N signal becomes Low active.
It notifies that one is free in pre-buffer. This is suitable for when continuous interpolation driving is performed at high speed.
■
Interrupt processing
When an interrupt is generated by INT1N signal, the host CPU writes the necessary next segment data in interrupt processing
routine. The data is the same as the 1st to 8th segments described in (4) and (5). At the end of one segment data, interpolation
driving command must be written. The user can write while checking the value of the stack counter by D15
～
12 bits (HSTC3
～
0)
of RR0 register.
■
Clear Interrupt signal (INT1N)
INT1N signal is cleared automatically by writing the nextinterpolation driving command and then returns to hi-Z. Or it can be
cleared by the following operation.
・
Write interpolation interrupt clear command (6Fh)
・
Continuous interpolation driving is finished.
