CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2 Details of CP0 Registers
3.2.1 Index register (0)
The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The
most-significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction.
The Index register also specifies the TLB entry affected by TLB read (TLBR) or TLB write index (TLBWI)
instructions.
The contents of the Index register are undefined after a reset so that it must be initialized by software.
Figure 3-1. Index Register
31
P
0
Index
30
5
4
0
P:
Indicates whether probing is successful or not. It is set to 1 if the latest TLBP instruction fails. It is
cleared to 0 when the TLBP instruction is successful.
Index:
Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
3.2.2 Random register (1)
The Random register is a read-only register. The low-order 5 bits are used in referencing a TLB entry. This
register is decremented each time an instruction is executed. The values that can be set in the register are as
follows:
•
The lower bound is the content of the Wired register.
•
The upper bound is 31.
The Random register specifies the entry in the TLB that is affected by the TLBWR instruction. The register is
readable to verify proper operation of the processor.
The Random register is set to the value of the upper bound upon Cold Reset. This register is also set to the upper
bound when the Wired register is written. Figure 3-2 shows the format of the Random register.
Figure 3-2. Random Register
31
0
Random
5
4
0
Random:
TLB random index
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
