User’s Manual U14272EJ3V0UM
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CHAPTER 3 CP0 REGISTERS
3.1 Coprocessor 0 (CP0)
The Coprocessor 0 (CP0), which is also called as System Control Coprocessor, is implemented as an integral part
of the CPU, and supports memory management, address translation, exception handling, and operation mode
control.
Memory management, address translation, and operation mode control are provided by a block called memory
management unit (MMU). The MMU contains a 32-entry TLB (translation lookaside buffer) that is used when
translating virtual addresses to physical addresses.
The CP0 has registers shown in Table 3-1 that are used to set various modes for memory management and
exception handling and to indicate statuses of the processor. Each CP0 register has a unique number that is used
as an operand to specify a CP0 register to be accessed.
Caution When accessing the CP0 registers, some instructions require consideration of the interval time
until the next instruction is executed, because there is a delay from when the contents of the
CP0 register change to when this change is reflected in the CPU operation. This time lag is
called a CP0 hazard. For details, refer to CHAPTER 23 COPROCESSOR 0 HAZARDS.
For details about functions of the CP0, refer to V
R
4100 Series Architecture User’s Manual.
