CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2.3 EntryLo0 (2) and EntryLo1 (3) registers
The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages
and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible.
They are used to access the built-in TLB. When a TLB read/write operation is carried out, the EntryLo0 and EntryLo1
registers hold the contents of the low-order 32 bits of TLB entries at even and odd addresses, respectively.
The contents of these registers are undefined after a reset so that they must be initialized by software.
Figure 3-3. EntryLo0 and EntryLo1 Registers
(a) 32-bit mode
(b) 64-bit mode
31
28 27
6
5
3
2
1
0
PFN
C
D
V
G
0
EntryLo0
31
28 27
6
5
3
2
1
0
PFN
C
D
V
G
0
EntryLo1
63
28 27
6
5
3
2
1
0
PFN
C
D
V
G
0
EntryLo0
63
28 27
6
5
3
2
1
0
PFN
C
D
V
G
0
EntryLo1
PFN:
Page frame number; high-order bits of the physical address.
C:
Specifies the TLB page attribute (see Table 3-2).
D:
Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writable. This bit is actually
a write-protect bit that software can use to prevent alteration of data.
V:
Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid
exception (TLBL or TLBS) occurs.
G:
Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID during
TLB lookup.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page. When the
cache is used, whether the page attribute is “cached” or “uncached” is selected by algorithm.
Table 3-2 lists the page attributes selected according to the value in the C bits.
