CHAPTER 1 INTRODUCTION
User’s Manual U14272EJ3V0UM
35
1.3.17 Wake-up events
The V
R
4181 supports 4 power management modes: Fullspeed, Standby, Suspend, and Hibernate. Of these
modes, Hibernate is the lowest power mode and results in the powering off of all system components including the
2.5 V logic in the V
R
4181. The V
R
4181 3.3 V logic, which includes RTC, PMU, and non-volatile registers, remain
powered during the Hibernate mode, as does the system DRAM. Software can configure the V
R
4181 waking up from
the Hibernate mode and returning to Fullspeed mode due to any one of the following events:
•
Activation of the DCD1# pin
•
Activation of the POWER pin
•
RTC alarm
•
Activation of one of the GPIO(15:0) pins
•
Activation of the CF_BUSY# pin (CompactFlash interrupt request (IREQ))
Remark
Different from the V
R
4111
TM
or the V
R
4121
TM
, the V
R
4181 will wake up after RTC reset without these
wake-up events.
1.4 V
R
4110 CPU Core
Figure 1-2 shows the internal block diagram of the V
R
4110 CPU core.
In addition to the conventional high-performance integer operation units, this CPU core has the full-associative
format translation lookaside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs (odd and even)
for one entry. Moreover, it also includes instruction cache, data cache, and bus interface.
Figure 1-2. V
R
4110 CPU Core Internal Block Diagram
TLB
Virtual address bus
Internal data bus
Bus
interface
Data
cache
(4 KB)
Instruction
cache
(4 KB)
Clock
generator
CP0
CPU
Control(o)
Control(i)
Address/Data(o)
Address/Data(i)
Internal clock
