CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2.12 Cause register (13)
The 32-bit read/write Cause register holds the cause of the most recent exception. A 5-bit exception code
indicates one of the causes (see Table 3-4). Other bits hold the detailed information of the specific exception. All
bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only; IP1 and IP0 bits are used for
software interrupts.
Figure 3-14. Cause Register
8
27
16 15
6
7
2
1
0
31 30 29 28
BD
0
CE
0
IP(7:0)
0
ExcCode
0
BD:
Indicates whether the most recent exception occurred in the branch delay slot (1
→
In delay slot, 0
→
Normal).
CE:
Indicates the coprocessor number in which a Coprocessor Unusable exception occurred.
This field will remain undefined for as long as no exception occurs.
IP:
Indicates whether an interrupt is pending (1
→
Interrupt pending, 0
→
No interrupt pending).
IP7:
A timer interrupt.
IP(6:2):
Ordinary interrupts (Int(4:0)
Note
). However, Int(4:3)
Note
never occurs in the V
R
4181.
IP(1:0):
Software interrupts. Only these bits cause an interrupt exception, when they are set
to 1 by means of software.
Note
Int(4:0) are internal signals of the V
R
4110 CPU core. For details about connection to
the on-chip peripheral units, refer to CHAPTER 9 INTERRUPT CONTROL UNIT
(ICU).
ExcCode: Exception code field (refer to Table 3-4 for details).
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
