NEC VR4181 mPD30181 User Manual Download Page 202

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CHAPTER 10 POWER MANAGEMENT UNIT (PMU)

User’s Manual U14272EJ3V0UM

202

10.6.2 Entering Hibernate mode (SDRAM)

<1> Copy contents of all 2.5 V registers (i.e. DRAM type and configuration, ROM type and configuration, etc.)

that must be preserved during Hibernate mode into the general-purpose registers, MISCREG(0:15), in the

GIU or into external memory.

Remark

3.3 V peripheral units: PMU, GIU, LED, and RTC

2.5 V peripheral units: all peripherals except PMU, GIU, LED, and RTC

<2> Stop operations of the DMA controller and LCD controller.

<3> Copy the codes for the Hibernate mode (<4> through <12> below) beginning at a 16-byte boundary into

the cache by using a Fill operation of CACHE instruction, and jump to the cached codes.

<4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge.

<5> Set the BCURFCNTREG register in the MBA Host Bridge to a value that determines refresh interval to

maximum to prevent an interruption of a Hibernate mode sequence.

<6> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the

BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific

time period (i.e. 0x3FFF

TClock burst refresh interval required by DRAM).

<7> Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst

refresh. Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self-refresh

mode.

<8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller puts the

DRAM into self-refresh mode.

<9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory

controller.

<10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched.

<11> Clear the SUSPEND bit in the DRAMHIBCTL register to 0 after waiting for about 2

<12> Execute a HIBERNATE instruction.

<13> Stop applying 2.5 V power supply when the MPOWER signal becomes low level.

Caution When entering Hibernate mode, set the BEV bit of the Status register in the CP0 of the CPU core

to 1 to make sure that the vector of the exception handler points the ROM area.

Summary of Contents for VR4181 mPD30181

Page 1: ...processor Hardware NEC Electronics Corporation 2000 MIPS Technologies Inc 1998 Printed in Japan Document No U14272EJ3V0UM00 3rd edition Date Published November 2002 NS CP K User s Manual µ µ µ µPD30181 查询UPD30181GM 66 8ED供应商 ...

Page 2: ...User s Manual U14272EJ3V0UM 2 MEMO ...

Page 3: ...Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZAT...

Page 4: ...iability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure f...

Page 5: ...1 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 Fax 6250 3583 J02 11 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Vélizy Villacoublay France Tel 01 30 67 58 00 Fax...

Page 6: ...SDIR and SYSEN and addition of description in Note in 2 2 1 System bus interface signals p 58 Addition of description for IRDIN RxD2 in 2 2 10 IrDA interface signals p 60 Addition and modification in 2 3 Pin Status in Specific Status pp 63 to 66 Addition of 2 4 Recommended Connection of Unused Pins and I O Circuit Types and 2 5 Pin I O Circuits pp 67 to 90 Addition of CHAPTER 3 CP0 REGISTERS p 95 ...

Page 7: ...RQREG 0x0A00 0662 p 156 Modification of description and addition of Caution in 8 1 Overview p 157 Addition of Caution in Figure 8 1 SCK and SI SO Relationship pp 157 158 Addition and modification of descriptions in 8 2 2 SCK phase and CSI transfer timing p 159 Modification of description in 8 2 3 1 Burst mode pp 161 162 Addition of Remarks and description in 8 3 1 CSIMODE 0x0B00 0900 p 171 Additio...

Page 8: ...4 3 4 PIUSTBLREG 0x0B00 0128 p 289 Addition of description in 14 3 6 PIUASCNREG 0x0B00 0130 p 290 Modification of description in Table 14 4 PIUASCNREG Bit Manipulation and States p 291 Addition of description in 14 3 7 PIUAMSKREG 0x0B00 0132 p 292 Modification of values at reset for bits 2 to 0 in 14 3 8 PIUCIVLREG 0x0B00 013E p 295 Modification of description in Table 14 7 Mask Clear During Scan ...

Page 9: ... Is Used p 356 Addition of function for bit 2 in 18 2 3 LEDCNTREG 0x0B00 0248 p 357 Modification of description in 18 2 4 LEDASTCREG 0x0B00 024A p 359 Modification of figure in 18 3 Operation Flow p 360 Addition of Caution in 19 1 General p 361 Modification of description in Table 19 1 SIU1 Registers pp 362 364 376 Modification of values at reset in 19 3 1 through 19 3 3 19 3 5 and 19 3 12 p 365 A...

Page 10: ...on of description in 21 3 4 Frame buffer memory and FIFO p 420 Addition of Remark in 21 4 11 LCDCFGREG0 0x0A00 0414 p 428 Addition of Remark in 21 4 22 CPINDCTREG 0x0A00 047E p 429 Addition of Caution in 21 4 23 CPALDATREG 0x0A00 0480 p 433 Addition of Caution in Table 23 1 Coprocessor 0 Hazards pp 436 to 438 Addition of APPENDIX A RESTRICTIONS ON VR4181 pp 439 to 444 Addition of APPENDIX B INDEX ...

Page 11: ...is manual It is assumed that the reader of this manual has general knowledge in the fields of electric engineering logic circuits microcomputers and SDRAMs To learn about the overall functions of the VR4181 Read this manual in sequential order To learn about instruction sets Read VR4100 Series Architecture User s Manual that is separately available To learn about electrical specifications Refer to...

Page 12: ...ame Document number VR4181 Hardware User s Manual This manual µPD30181 VR4181 Data Sheet U14273E VR4100 Series Architecture User s Manual U15509E VR Series TM Programming Guide Application Note U10710E The related documents indicated here may include preliminary version However preliminary versions are not marked as such ...

Page 13: ...U 33 1 3 14 General purpose I O 33 1 3 15 Programmable chip selects 34 1 3 16 LCD interface 34 1 3 17 Wake up events 35 1 4 VR4110 CPU Core 35 1 4 1 CPU registers 37 1 4 2 CPU instruction set overview 38 1 4 3 Data formats and addressing 40 1 4 4 CP0 registers 43 1 4 5 Floating point unit FPU 44 1 4 6 Memory management unit 44 1 4 7 Cache 44 1 4 8 Instruction pipeline 44 1 4 9 Power modes 45 1 4 1...

Page 14: ... 2 5 PageMask register 5 72 3 2 6 Wired register 6 73 3 2 7 BadVAddr register 8 74 3 2 8 Count register 9 74 3 2 9 EntryHi register 10 75 3 2 10 Compare register 11 76 3 2 11 Status register 12 76 3 2 12 Cause register 13 79 3 2 13 Exception Program Counter EPC register 14 81 3 2 14 Processor Revision Identifier PRId register 15 82 3 2 15 Config register 16 83 3 2 16 Load Linked Address LLAddr reg...

Page 15: ...ace 109 6 2 Bus Control Registers 110 6 2 1 BCUCNTREG1 0x0A00 0000 111 6 2 2 CMUCLKMSK 0x0A00 0004 112 6 2 3 BCUSPEEDREG 0x0A00 000C 113 6 2 4 BCURFCNTREG 0x0A00 0010 115 6 2 5 REVIDREG 0x0A00 0014 116 6 2 6 CLKSPEEDREG 0x0A00 0018 117 6 3 ROM Interface 118 6 3 1 External ROM devices memory mapping 118 6 3 2 Connection to external ROM x 16 devices 119 6 3 3 Example of ROM connection 120 6 3 4 Exte...

Page 16: ...FGREG 0x0A00 0660 152 7 2 11 DMAITRQREG 0x0A00 0662 153 7 2 12 DMACTLREG 0x0A00 0664 154 7 2 13 DMAITMKREG 0x0A00 0666 155 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 156 8 1 Overview 156 8 2 Operation of CSI 156 8 2 1 Transmit receive operations 156 8 2 2 SCK phase and CSI transfer timing 157 8 2 3 CSI transfer types 159 8 2 4 Transmit and receive FIFOs 160 8 3 CSI Registers 160 8 3 1 CSIMODE 0x0...

Page 17: ...10 4 3 BATTINH shutdown 193 10 5 Power on Control 194 10 5 1 Activation via Power Switch interrupt request 195 10 5 2 Activation via CompactFlash interrupt request 196 10 5 3 Activation via GPIO activation interrupt request 197 10 5 4 Activation via DCD interrupt request 198 10 5 5 Activation via ElapsedTime RTC alarm interrupt request 200 10 6 DRAM Interface Control 201 10 6 1 Entering Hibernate ...

Page 18: ...IT GIU 236 13 1 Overview 236 13 1 1 GPIO pins and alternate functions 236 13 1 2 I O direction control 238 13 1 3 General purpose registers 238 13 2 Alternate Functions Overview 238 13 2 1 Clocked serial interface CSI 238 13 2 2 Serial interface channels 1 and 2 239 13 2 3 LCD interface 241 13 2 4 Programmable chip selects 242 13 2 5 16 bit bus cycles 242 13 2 6 General purpose input output 242 13...

Page 19: ...x0B00 0124 284 14 3 3 PIUSIVLREG 0x0B00 0126 285 14 3 4 PIUSTBLREG 0x0B00 0128 286 14 3 5 PIUCMDREG 0x0B00 012A 287 14 3 6 PIUASCNREG 0x0B00 0130 289 14 3 7 PIUAMSKREG 0x0B00 0132 291 14 3 8 PIUCIVLREG 0x0B00 013E 292 14 3 9 PIUPBnmREG 0x0B00 02A0 to 0x0B00 02AE 0x0B00 02BC to 0x0B00 02BE 293 14 3 10 PIUABnREG 0x0B00 02B0 to 0x0B00 02B6 294 14 4 State Transition Flow 295 14 5 Relationships among T...

Page 20: ...B00 0180 to 0x0B00 018E 322 16 3 2 KIUSCANREP 0x0B00 0190 323 16 3 3 KIUSCANS 0x0B00 0192 324 16 3 4 KIUWKS 0x0B00 0194 325 16 3 5 KIUWKI 0x0B00 0196 326 16 3 6 KIUINT 0x0B00 0198 327 CHAPTER 17 COMPACTFLASH CONTROLLER ECU 328 17 1 General 328 17 2 Register Set Summary 328 17 3 ECU Control Registers 331 17 3 1 INTSTATREG 0x0B00 08F8 331 17 3 2 INTMSKREG 0x0B00 08FA 332 17 3 3 CFG_REG_1 0x0B00 08FE...

Page 21: ...LED 353 18 1 General 353 18 2 Register Set 353 18 2 1 LEDHTSREG 0x0B00 0240 354 18 2 2 LEDLTSREG 0x0B00 0242 355 18 2 3 LEDCNTREG 0x0B00 0248 356 18 2 4 LEDASTCREG 0x0B00 024A 357 18 2 5 LEDINTREG 0x0B00 024C 358 18 3 Operation Flow 359 CHAPTER 19 SERIAL INTERFACE UNIT 1 SIU1 360 19 1 General 360 19 2 Clock Control Logic 360 19 3 Register Set 361 19 3 1 SIURB_1 0x0C00 0010 LCR7 0 Read 362 19 3 2 S...

Page 22: ...x0C00 000A 396 20 3 16 SIUACTMSK_2 0x0C00 000C 397 20 3 17 SIUACTTMR_2 0x0C00 000E 398 CHAPTER 21 LCD CONTROLLER 399 21 1 Overview 399 21 1 1 LCD interface 399 21 2 LCD Module Features 400 21 3 LCD Controller Specification 402 21 3 1 Panel configuration and interface 402 21 3 2 Controller clocks 405 21 3 3 Palette 406 21 3 4 Frame buffer memory and FIFO 406 21 3 5 Panel power ON OFF sequence 407 2...

Page 23: ...1 4 18 FHENDREG 0x0A00 0426 424 21 4 19 PWRCONREG1 0x0A00 0430 425 21 4 20 PWRCONREG2 0x0A00 0432 426 21 4 21 LCDIMSKREG 0x0A00 0434 427 21 4 22 CPINDCTREG 0x0A00 047E 428 21 4 23 CPALDATREG 0x0A0 0480 429 CHAPTER 22 PLL PASSIVE COMPONENTS 430 CHAPTER 23 COPROCESSOR 0 HAZARDS 431 APPENDIX A RESTRICTIONS ON VR4181 436 A 1 RSTSW During HALTimer Operation 436 A 2 RSTSW in Hibernate Mode 437 APPENDIX ...

Page 24: ...3 5 PageMask Register 72 3 6 Positions Indicated by the Wired Register 73 3 7 Wired Register 73 3 8 BadVAddr Register 74 3 9 Count Register 74 3 10 EntryHi Register 75 3 11 Compare Register 76 3 12 Status Register 76 3 13 Status Register Diagnostic Status Field 77 3 14 Cause Register 79 3 15 EPC Register When MIPS16 ISA Is Disabled 81 3 16 EPC Register When MIPS16 ISA Is Enabled 82 3 17 PRId Regis...

Page 25: ... 6 8 SDRAM Configuration 130 8 1 SCK and SI SO Relationship 157 9 1 Outline of Interrupt Control 172 10 1 Transition of VR4181 Power Mode 189 10 2 EDO DRAM Signals on RSTSW Reset SDRAM Bit 0 192 10 3 Activation via Power Switch Interrupt Request BATTINH H 195 10 4 Activation via Power Switch Interrupt Request BATTINH L 195 10 5 Activation via CompactFlash Interrupt Request BATTINH H 196 10 6 Activ...

Page 26: ...Logic 333 17 2 Mapping of CompactFlash Memory Space 350 17 3 Mapping of CompactFlash I O Space 351 19 1 SIU1 Block Diagram 360 20 1 SIU2 Block Diagram 379 21 1 LCD Controller Block Diagram 401 21 2 View Rectangle and Horizontal Vertical Blank 402 21 3 Position of Load Clock LOCLK 403 21 4 Position of Frame Clock FLM 404 21 5 Monochrome Panel 408 21 6 Color Panel in 8 Bit Data Bus 409 21 7 Load Clo...

Page 27: ...ption Code Field 80 4 1 VR4181 Physical Address Space 93 4 2 ROM Address Map 93 4 3 Internal I O Space 1 94 4 4 Internal I O Space 2 94 4 5 MBA Bus I O Space 95 4 6 DRAM Address Map 95 6 1 Bus Control Registers 110 6 2 VR4181 EDO DRAM Capacity 129 6 3 Memory Controller Registers 131 6 4 ISA Bridge Registers 137 7 1 DCU Registers 144 8 1 CSI Registers 160 9 1 ICU Registers 173 10 1 Overview of Powe...

Page 28: ...ata Buffers 294 14 7 Mask Clear During Scan Sequencer Operation 295 15 1 AIU Registers 302 15 2 AIU Interrupt Registers 302 16 1 Settings of Keyboard Scan Mode 318 16 2 KIU Registers 321 16 3 KIU Interrupt Registers 321 17 1 ECU Control Registers 328 17 2 ECU Registers 329 18 1 LED Registers 353 19 1 SIU1 Registers 361 19 2 Correspondence between Baud Rates and Divisors 365 19 3 Interrupt Function...

Page 29: ...n 32 bit mode is available Optimized 5 stage pipeline On chip instruction and data caches with 4 KB each in size Write back cache for reducing store operation that use the system bus 32 bit physical address space and 40 bit virtual address space and 32 double entry TLB Instruction set MIPS III with the FPU LL and SC instructions left out and MIPS16 Supports MADD16 and DMADD16 instructions for exec...

Page 30: ...Figure 1 1 Internal Block Diagram LCD Panel 32 768 kHz 18 432 MHz EDO DRAM SDRAM ROM Flash memory LCD controller Clock generator VR4110 CPU core MBATM Host Bridge ISA bridge PMU PIU SIU1 SIU2 IR module RS 232 C driver GIU LED LED VR4181 ICU RTC Speaker Microphone Touch panel Battery monitor CompactFlash card Bus control Memory controller ECU DCU Buf Buf AIU D A CSI KIU A D DSU Keyboard 8 x 8 ISA b...

Page 31: ...s supported only when the internal LCD controller has been disabled or the LCD panel has been powered off 1 3 2 Bus interface The VR4181 incorporates single bus architecture All external memory and I O devices are connected to the same 22 bit address bus and 16 bit data bus These external address and data bus are together called the system bus When the external bus operates at a very high speed th...

Page 32: ...eal time clock RTC which allows time keeping based on the 32 768 kHz clock as a source The RTC operates as long as the VR4181 remains powered 1 3 7 Audio output D A converter The VR4181 provides a 1 channel 10 bit D A converter for generating audio output 1 3 8 Touch panel interface and audio input A D converter The VR4181 provides an 8 channel 10 bit A D converter for interfacing to a touch panel...

Page 33: ...16 pins that can cause the system s waking up from a low power mode if enabled by software The other pins have no functions other than those listed below The remaining 16 bits of general purpose I O GPIO 15 0 are allocated to pins by default Each of these pins can be configured to support a particular interface such as CSI secondary serial interface RS 232 C programmable chip selects or color LCD ...

Page 34: ...bpp mode 16 colors and 8 bpp mode 256 colors The LCD controller includes a 256 entry x 18 bit color pallet In 8 bpp color modes the pallet is used to select 256 colors out of possible 262 144 colors The LCD controller supports LCD panels of up to 320 x 320 pixels Typical LCD panel horizontal vertical resolutions are as follows Table 1 4 LCD Panel Resolutions in Pixels TYP Horizontal resolution Ver...

Page 35: ...ivation of one of the GPIO 15 0 pins Activation of the CF_BUSY pin CompactFlash interrupt request IREQ Remark Different from the VR4111 TM or the VR4121 TM the VR4181 will wake up after RTC reset without these wake up events 1 4 VR4110 CPU Core Figure 1 2 shows the internal block diagram of the VR4110 CPU core In addition to the conventional high performance integer operation units this CPU core h...

Page 36: ...s direct mapping virtual index physical tag and writeback Its capacity is 4 KB 5 CPU bus interface The CPU bus interface controls data transmission reception between the VR4110 core and the MBA Host Bridge This interface consists of two 32 bit multiplexed address data buses one is for input and another is for output clock signal and control signals such as interrupt requests 6 Clock generator The ...

Page 37: ... This register can be used for other instructions However be careful that use of the register by a link instruction will not coincide with use of the register for other operations The register group is provided within the CP0 to process exceptions and to manage addresses CPU registers can operate as either 32 bit or 64 bit registers depending on the VR4181 processor mode of operation The operation...

Page 38: ...eneral purpose registers They are all immediate I type instructions since the only addressing mode supported is base register plus 16 bit signed immediate offset b Computational instructions perform arithmetic logical shift and multiply and divide operations on values in registers They include R type in which both the operands and the result are stored in registers and I type in which one operand ...

Page 39: ...pe I8_MOVR32 type I8_MOV32R type I64 type RI64 type JAL JALX type immediate 0 10 11 op immediate 0 11 15 15 rx 10 8 7 op funct 0 11 15 rx 10 8 7 ry 5 4 RRI immediate 0 11 15 rx 10 8 7 ry 5 4 RRR F 0 11 15 rx 10 8 7 ry 5 4 5 4 rz 2 1 RRI A F 0 11 15 rx 10 8 7 ry immediate 3 SHIFT F 0 11 15 rx 10 8 7 ry Shamt 2 1 I8 immediate 0 11 15 funct 10 8 7 I8 r32 4 0 0 11 15 funct 10 8 7 ry I8 r32 2 0 funct r...

Page 40: ... field of the next instruction They are RR and I types When extending the immediate field of the next instruction by using the Extend instruction one cycle is needed for executing the Extend instruction and another cycle is needed for executing the next instruction 1 4 3 Data formats and addressing The VR4181 uses the following four data formats Doubleword 64 bits Word 32 bits Halfword 16 bits Byt...

Page 41: ... 15 8 7 0 12 8 4 0 Word address High order address Low order address b Doubleword data 23 15 7 22 14 6 21 13 5 20 12 4 16 8 0 Doubleword address High order address Low order address 19 11 3 18 10 2 17 9 1 16 8 0 63 0 32 31 16 15 8 7 Word Halfword Byte Remarks 1 The lowest byte is the lowest address 2 The address of word data is specified by the lowest byte s address ...

Page 42: ...e used to load and store data that are not aligned on 4 byte word or 8 byte doubleword boundaries Word access LWL LWR SWL SWR Doubleword access LDL LDR SDL SDR These instructions are used in pairs of L and R Accessing unaligned data requires one additional instruction cycle 1 PCycle over that required for accessing aligned data Figure 1 7 shows the access of an unaligned word that has byte address...

Page 43: ...re Exception processing Timer compare value 12 Status Exception processing Status indication 13 Cause Exception processing Cause of last exception 14 EPC Exception processing Exception Program Counter 15 PRId Memory management Processor revision identifier 16 Config Memory management Configuration memory system modes specification 17 LLAddr Note1 Memory management Physical address for self diagnos...

Page 44: ...esses and data addresses so that it is called as joint TLB JTLB The page size can be configured on a per entry basis to map a page size of 1 KB to 256 KB in power of four A CP0 register stores the size of the page to be mapped and that size is entered into the TLB when a new entry is written Thus operating systems can provide special purpose maps for example a typical frame buffer can be memory ma...

Page 45: ...e During Suspend mode the pipeline clock PClock in the CPU core is held at high level The VR4181 also stops supplying TClock and PCLK to peripheral units While in this mode the register and cache contents are retained Contents of DRAM can also be retained by putting DRAM into self refresh mode During Suspend mode the processor returns to Fullspeed mode if any of power on factors or some of interru...

Page 46: ...110 core does not support floating point instructions since it has no Floating Point Unit FPU The VR4110 core does not have the LL bit to perform synchronization of multiprocessing Therefore it does not support instructions that manipulate the LL bit LL LLD SC SCD The CP0 hazards of the VR4110 core are equally or less stringent than those of the VR4000 For more information about each instruction r...

Page 47: ...ly with this clock TClock internal This is an operation clock for internal MBA bus and is supplied to the internal MBA modules memory controller LCD controller and DMA controller This clock is generated from PClock and its frequency is 1 1 1 2 or 1 3 of the PClock frequency it is determined by internal register setting It is set to 1 2 by default PCLK internal This clock is supplied to the interna...

Page 48: ...void an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as GND Do not ground the capacitor to a ground pattern through which a high current flows D...

Page 49: ... 2 Note 1 b There is another signal line crossing c A high fluctuating current flows near a signal line Large current d A current flows over the ground line of the oscillator The potentials of points A B and C change A B C VDD e A signal is fetched Note 2 Note 1 Note 2 Note 1 Note 1 Note 2 Notes1 CLKX2 RTCX2 2 CLKX1 RTCX1 3 GND_OSC Note 3 Note 3 Note 3 Note 3 Note 3 ...

Page 50: ...OGIC VDD_LOGIC ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 GND_IO VDD_IO ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DTR1 GPIO30 CLKSEL2 DSR1 GPIO31 POWER RSTSW RTCRST POWERON MPOWER BATTINH BATTINT VDD_LOGIC GND_LOGIC CF_AEN SCANIN0 CF_DIR SCANIN1 CF_DEN SCANIN2 CF_VCCEN SCANIN3 CF_I...

Page 51: ... bit Bus Sizing IORD I O Read IORDY I O Ready IOWR I O Write IRDIN IrDA Data Input IRDOUT IrDA Data Output LCAS Lower Column Address Strobe LCDCS Chip Select for LCD LDQM Lower Byte Enable for SDRAM LEDOUT LED Output LOCLK Load Clock for LCD M LCD Modulation Clock MEMCS16 Memory 16 bit Bus Sizing MEMRD Memory Read MEMWR Memory Write MIPS16EN MIPS16 Enable MPOWER Main Power PCS 1 0 Programmable Chi...

Page 52: ...his signal as active when system bus controller is ready to be accessed by the VR4181 when configured as IORDY IOCS16 GPIO19 I O Bus sizing request input for system bus I O or general purpose I O Set this signal as active when system bus I O accesses data in 16 bit width if configured as IOCS16 UBE GPIO20 M I O System bus upper byte enable output general purpose input or LCD modulation output Duri...

Page 53: ...RAM operating clock CLKEN Output SDRAM clock enable output CKE ROMCS3 Output ROM chip select output for bank 3 ROMCS2 GPIO24 I O ROM chip select output for bank 2 or general purpose I O ROMCS1 GPIO23 I O ROM chip select output for bank 1 or general purpose I O ROMCS0 GPIO22 I O ROM chip select output for bank 0 or general purpose I O MEMRD Output Memory read signal for ROM and system bus MEMWR Out...

Page 54: ... operation output LCD first line clock output FPD 7 4 GPIO 15 12 Note Output See 2 2 11 General purpose I O signals in this section FPD 3 0 Note Output LCD screen data VPLCD VPGPIO1 Output LCD logic power control This signal may be defined as a general purpose output when an external LCD controller is used VPBIAS VPGPIO0 Output LCD bias power control This signal may be defined as a general purpose...

Page 55: ...al is inactive during Hibernate mode During this signal being inactive turn off the 2 5 V power supply 2 2 4 Battery monitor interface signals Signal name I O Description of function BATTINH BATTINT Input The function of this pin differs depending on the state of the MPOWER pin When MPOWER 0 BATTINH signal Enables or disables activation on power application 1 Enable activation 0 Disable activation...

Page 56: ...CompactFlash output enable or keyboard scan data output CF_IOW SCANOUT5 Output CompactFlash I O write strobe output or keyboard scan data output CF_IOR SCANOUT4 Output CompactFlash I O read strobe output or keyboard scan data output CF_STSCHG SCANOUT3 I O CompactFlash status changed input or keyboard scan data output CF_CE 2 1 SCANOUT 2 1 Output CompactFlash card enable outputs or keyboard scan da...

Page 57: ...end input or general purpose I O DCD1 GPIO29 I O Serial channel 1 data carrier detect input or general purpose I O DTR1 GPIO30 CLKSEL2 I O The function of this pin differs depending on the operating status During RTC reset input This signal is used to set CPU core operation clock frequency Note During normal operation input output Serial channel 1 data terminal ready output or general purpose I O ...

Page 58: ...O or LCD screen data output GPIO12 FPD4 I O General purpose I O or LCD screen data output GPIO11 PCS1 I O General purpose I O or programmable chip select 1 GPIO10 FRM SYSCLK I O General purpose I O serial frame input for clocked serial interface or external bus system clock output GPIO9 CTS2 I O General purpose I O or serial channel 2 clear to send output GPIO8 DSR2 I O General purpose I O or seri...

Page 59: ...in becomes the maximum value for the A D and D A interface signals GND_AD 3 3 V Ground dedicated for the A D and D A converters The voltage applied to this pin becomes the minimum value for the A D and D A interface signals VDD_OSC 3 3 V Power supply dedicated for the oscillator GND_OSC 3 3 V Ground dedicated for the oscillator VDD_LOGIC 2 5 V Ordinary power supply of 2 5 V GND_LOGIC 2 5 V Ordinar...

Page 60: ... 1 Note 1 Hi Z Note 3 IOWR GPIO17 Hi Z Hi Z 1 Note 1 Hi Z Note 3 IORDY GPIO18 Hi Z Hi Z Note 1 Note 3 IOCS16 GPIO19 Hi Z Hi Z Note 1 Note 3 UBE GPIO20 M Hi Z Hi Z 1 Note 1 0 Hi Z Note 3 0 RESET GPIO21 Hi Z Hi Z Note 1 0 Note 3 ROMCS 2 0 GPIO 24 22 Hi Z Hi Z 1 Note 1 Hi Z Note 3 ROMCS3 Hi Z Hi Z 1 1 Hi Z SHCLK LCDCS Hi Z 0 0 1 0 1 0 Hi Z LOCLK MEMCS16 Hi Z 0 0 0 0 FLM MIPS16EN Note 4 0 0 0 0 FPD 3 ...

Page 61: ...CANOUT 2 1 Hi Z Hi Z Hi Z Note 1 Note 2 Hi Z CF_BUSY SCANOUT0 Hi Z Hi Z Hi Z Note 1 Note 1 Hi Z CF_REG SCANIN7 Hi Z Note 1 Note 1 Note 2 Note 1 CF_RESET SCANIN6 Hi Z Note 1 Note 1 Note 3 Note 1 CF_WAIT SCANIN5 Note 1 Note 1 CF_IOIS16 SCANIN4 Note 1 Note 1 CF_VCCEN SCANIN3 Hi Z Note 1 Note 1 Note 4 Note 1 CF_DEN SCANIN2 Hi Z Note 1 Note 1 1 Note 1 CF_DIR SCANIN1 Hi Z Note 1 Note 1 1 Note 1 CF_AEN S...

Page 62: ...e 2 Note 1 GPIO 13 12 FPD 5 4 Hi Z Hi Z Note 1 0 Note 2 Note 1 GPIO11 PCS1 Hi Z Hi Z Hi Z 1 Note 1 1 Note 2 Hi Z GPIO10 FRM SYSCLK Hi Z Hi Z Hi Z Note 1 0 Note 2 Note 1 Hi Z GPIO9 CTS2 Hi Z Hi Z Note 1 Note 2 Note 1 GPIO8 DSR2 Hi Z Hi Z Note 1 Note 2 Note 1 GPIO7 DTR2 Hi Z Hi Z Note 1 Note 2 Note 1 GPIO6 RTS2 Hi Z Hi Z Note 1 Note 2 Note 1 GPIO5 DCD2 Hi Z Hi Z Note 1 Note 2 Note 1 GPIO4 Hi Z Hi Z ...

Page 63: ...nnect to VDD_IO or GND_IO via resistor A IOCS16 GPIO19 Connect to VDD_IO or GND_IO via resistor A UBE GPIO20 M Connect to VDD_IO or GND_IO via resistor A RESET GPIO21 Connect to VDD_IO or GND_IO via resistor A ROMCS 2 0 GPIO 24 22 Connect to VDD_IO or GND_IO via resistor A ROMCS3 A SHCLK LCDCS Leave open A LOCLK MEMCS16 Leave open A FLM MIPS16EN Connect to VDD_IO or GND_IO via resistor A FPD 3 0 L...

Page 64: ...26 CLKSEL0 Connect to VDD_IO or GND_IO via resistor A RTS1 GPIO27 CLKSEL1 Connect to VDD_IO or GND_IO via resistor A CTS1 GPIO28 Connect to VDD_IO or GND_IO via resistor A DCD1 GPIO29 Connect to VDD_IO or GND_IO via resistor A DTR1 GPIO30 CLKSEL2 Connect to VDD_IO or GND_IO via resistor A DSR1 GPIO31 Connect to VDD_IO or GND_IO via resistor A IRDIN RxD2 Connect to VDD_IO or GND_IO via resistor A I...

Page 65: ...nded Connection When Not Used I O Circuit Type GPIO3 PCS0 Connect to VDD_IO or GND_IO via resistor A GPIO2 SCK Connect to VDD_IO or GND_IO via resistor A GPIO1 SO Connect to VDD_IO or GND_IO via resistor A GPIO0 SI Connect to VDD_IO or GND_IO via resistor A LEDOUT Leave open A ...

Page 66: ...ircuits Output disable Input enable Data Output disable Data Input enable Analog output voltage OUT Output disable Data Vref Vref Vref VDD P ch N ch IN OUT VDD P ch N ch P ch N ch IN OUT VDD P ch N ch N ch P ch IN N ch P ch N ch IN OUT Type A Type C Type D Type E Type B ...

Page 67: ...ical addresses The CP0 has registers shown in Table 3 1 that are used to set various modes for memory management and exception handling and to indicate statuses of the processor Each CP0 register has a unique number that is used as an operand to specify a CP0 register to be accessed Caution When accessing the CP0 registers some instructions require consideration of the interval time until the next...

Page 68: ... of last exception 14 EPC Exception processing Exception Program Counter 15 PRId Memory management Processor revision identifier 16 Config Memory management Configuration memory system modes specification 17 LLAddr Note1 Memory management Physical address for self diagnostics 18 WatchLo Exception processing Memory reference trap address low bits 19 WatchHi Exception processing Memory reference tra...

Page 69: ...that is a target of the TLBR or TLBWI instruction 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read 3 2 2 Random register 1 The Random register is a read only register The low order 5 bits are used in referencing a TLB entry This register is decremented each time an instruction is executed The values that can be set in the register are as follows The lower bo...

Page 70: ... 0 EntryLo1 63 28 27 6 5 3 2 1 0 PFN C D V G 0 EntryLo0 63 28 27 6 5 3 2 1 0 PFN C D V G 0 EntryLo1 PFN Page frame number high order bits of the physical address C Specifies the TLB page attribute see Table 3 2 D Dirty If this bit is set to 1 the page is marked as dirty and therefore writable This bit is actually a write protect bit that software can use to prevent alteration of data V Valid If th...

Page 71: ...ore useful for a software TLB exception handler Figure 3 4 Context Register a 32 bit mode b 64 bit mode 0 24 24 25 31 4 3 PTEBase BadVPN2 0 0 25 63 4 3 PTEBase BadVPN2 0 PTEBase The PTEBase field is a base address of the PTE entry table BadVPN2 This field holds the value VPN2 obtained by halving the virtual page number of the most recent virtual address for which translation failed 0 Reserved for ...

Page 72: ...dress translation The contents of the PageMask register are undefined after a reset so that it must be initialized by software Figure 3 5 PageMask Register 31 19 18 11 10 0 MASK 0 0 MASK Page comparison mask which determines the virtual page size for the corresponding entry 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read Table 3 3 lists the mask pattern for...

Page 73: ...es can be overwritten by both instructions Figure 3 6 Positions Indicated by the Wired Register 31 Value in the Wired register 0 Range specified by the Random register Range of Wired entries TLB The Wired register is set to 0 upon Cold Reset Writing this register also sets the Random register to the value of its upper bound see 3 2 2 Random register 1 Figure 3 7 Wired Register 31 5 4 0 0 Wired Wir...

Page 74: ...ssing error occurred or for which address translation failed 3 2 8 Count register 9 The read write Count register acts as a timer It is incremented in synchronization with the MasterOut clock 1 8 1 12 or 1 16 frequencies of the PClock regardless of whether instructions are being executed retired or any forward progress is actually made through the pipeline This register is a free running type When...

Page 75: ...ked with the ASID of the TLB entry as the ASID of the virtual address during address translation The EntryHi register is accessed by the TLBP TLBWR TLBWI and TLBR instructions The contents of the EntryHi register are undefined after a reset so that it must be initialized by software Figure 3 10 EntryHi Register 31 11 10 8 7 0 a 32 bit mode b 64 bit mode VPN2 0 ASID 63 62 61 11 10 40 39 8 7 0 Fill ...

Page 76: ...egister that contains the operating mode interrupt enabling and the diagnostic states of the processor Figure 3 12 Status Register 1 2 29 28 27 26 25 24 16 15 8 7 6 5 3 2 1 0 31 0 CU0 0 RE DS IM UX KSU ERL IE KX SX EXL 4 CU0 Enables disables the use of the coprocessor 1 Enabled 0 Disabled CP0 can be used in Kernel mode at all times RE Enables disables reversing of the endian setting in User mode 0...

Page 77: ...gister Diagnostic Status Field 16 17 18 19 20 21 22 23 24 0 BEV TS SR 0 CH CE DE BEV Specifies the base address of a TLB Refill exception vector and common exception vector 0 Normal 1 Bootstrap TS Occurs the TLB to be shut down read only 0 Not shut down 1 Shut down This bit is used to avoid any problems that may occur when multiple TLB entries match the same virtual address After the TLB has been ...

Page 78: ... 64 bit opcodes and translation of 64 bit addresses 64 bit operation for User Kernel and Supervisor modes can be set independently 64 bit addressing for Kernel mode is enabled when KX bit 1 64 bit operations are always valid in Kernel mode If this bit is set an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address space 64 bit addressing and operations are enabled for Superv...

Page 79: ... In delay slot 0 Normal CE Indicates the coprocessor number in which a Coprocessor Unusable exception occurred This field will remain undefined for as long as no exception occurs IP Indicates whether an interrupt is pending 1 Interrupt pending 0 No interrupt pending IP7 A timer interrupt IP 6 2 Ordinary interrupts Int 4 0 Note However Int 4 3 Note never occurs in the VR4181 IP 1 0 Software interru...

Page 80: ...ction exception 11 CpU Coprocessor Unusable exception 12 Ov Integer Overflow exception 13 Tr Trap exception 14 to 22 Reserved for future use 23 WATCH Watch exception 24 to 31 Reserved for future use The VR4181 has eight interrupt request sources IP7 to IP0 They are used for the purpose as follows For the detailed description of interrupts of the CPU core refer to VR4100 Series Architecture User s ...

Page 81: ...on and ISA mode at which an exception occurs Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception occurs when the instruction associated with the exception is in a branch delay slot of the jump instruction and the BD bit in the Cause register is set to 1 When the 16 bit instruction is executed either of the following addresses is contained in t...

Page 82: ...ifier PRId register contains information identifying the implementation and revision level of the CPU and CP0 Figure 3 17 PRId Register 31 16 15 8 7 0 0 Imp Rev Imp CPU core processor ID number 0x0C for the VR4181 Rev CPU core processor revision number 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read The processor revision number is stored as a value in the ...

Page 83: ...ware Caution Be sure to set the EP field and the AD bit to 0 If they are set with any other values the processor may behave unexpectedly Figure 3 18 Config Register 1 2 31 30 28 27 24 23 22 21 2019 18 17 16 15 14 13 12 11 9 8 6 5 3 2 0 0 EC EP AD 0 M16 0 1 0 BE 10 CS IC DC 0 K0 EC System clock ratio read only 0 Processor clock frequency divided by 2 1 Processor clock frequency divided by 3 2 Proce...

Page 84: ...dress LLAddr register 17 The read write Load Linked Address LLAddr register is not used with the VR4181 processor except for diagnostic purpose and serves no function during normal operation The LLAddr register is implemented just for compatibility between the VR4181 and VR4000 or VR4400 The contents of the LLAddr register are undefined after a reset Figure 3 19 LLAddr Register 31 0 PAddr PAddr 32...

Page 85: ... so that they must be initialized by software Figure 3 20 WatchLo Register 3 2 1 0 31 PAddr0 0 R W PAddr0 Specifies physical address bits 31 to 3 R Specifies detection of watch address references when load instructions are executed 1 Detect 0 Not detect W Specifies detection of watch address references when store instructions are executed 1 Detect 0 Not detect 0 Reserved for future use Write 0 in ...

Page 86: ...ng system use The operating system sets the PTEBase field in the register as needed Figure 3 22 XContext Register 32 0 35 34 33 63 4 3 PTEBase R BadVPN2 0 PTEBase Base address of the PTE entry table R Space type 00 User 01 Supervisor 11 Kernel The setting of this field matches virtual address bits 63 and 62 BadVPN2 The value VPN2 obtained by halving the virtual page number of the most recent virtu...

Page 87: ... Register 0 8 7 31 0 Diagnostic Diagnostic 8 bit self diagnostic field 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read 3 2 20 Cache Error register 27 The Cache Error register is a readable writable register This register is defined to maintain software compatibility with the VR4100 and is not used in hardware because the VR4181 has no parity Figure 3 24 Cac...

Page 88: ...with data cache V D W 0 31 10 9 8 0 PTagLo b When used with instruction cache V 0 PTagLo Specifies physical address bits 31 to 10 V Valid bit D Dirty bit However this bit is defined only for the compatibility with the VR4000 Series processors and does not indicate the status of cache memory in spite of its readability and writability This bit cannot change the status of cache memory W Writeback bi...

Page 89: ...contained in the ErrorEPC register during a 32 bit instruction execution Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot and the BD bit in the Cause...

Page 90: ...8 ErrorEPC Register When MIPS16 ISA Is Enabled a 32 bit mode 1 0 31 ErrorEPC ErIM ErrorEPC Bits 31 to 1 of virtual restart address after Cold reset Soft reset or NMI exception ErIM ISA mode at which an error exception occurs 1 MIPS16 ISA 0 MIPS III ISA b 64 bit mode 1 0 63 ErrorEPC ErIM ErrorEPC Bits 63 to 1 of virtual restart address after Cold reset Soft reset or NMI exception ErIM ISA mode at w...

Page 91: ...B is accessed through the CP0 registers Note that the virtual address space includes areas that are translated to physical addresses without using a TLB and areas where the use of cache memory can be selected The VR4181 has three operating modes User Supervisor and Kernel the manner in which memory addresses are mapped depends on these operating modes In addition the VR4181 supports the 32 bit and...

Page 92: ...xFFFF FFFF Mirror image of 0x0000 0000 to 0x1FFF FFFF area ROM space including a boot ROM External system bus memory space ISA memory Internal ISA I O space 1 Internal ISA I O space 2 RFU DRAM space MBA bus I O space RFU 0x1800 0000 0x17FF FFFF 0x0C00 0000 0x0BFF FFFF 0x0B00 0000 0x0AFF FFFF 0x0D00 0000 0x0CFF FFFF 0x0A00 0000 0x09FF FFFF 0x0400 0000 0x03FF FFFF 0x0000 0000 0x1000 0000 0x0FFF FFFF...

Page 93: ...M 0x03FF FFFF to 0x0000 0000 DRAM SDRAM space 64 M 4 2 1 ROM space The ROM space mapping differs depending on the capacity of the ROM being used The ROM capacity is set via the ROMs 1 0 bits in the BCUCNTREG1 register The physical addresses of the ROM space are listed below Table 4 2 ROM Address Map Physical address When using 32 Mbit ROM When using 64 Mbit ROM 0x1FFF FFFF to 0x1FC0 0000 Bank 3 RO...

Page 94: ...2D0 Reserved for future use 0x0B00 02CF to 0x0B00 02C0 ISA Bridge 0x0B00 02BF to 0x0B00 02A0 PIU 2 0x0B00 029F to 0x0B00 0280 Reserved for future use 0x0B00 027F to 0x0B00 0260 A D test 0x0B00 025F to 0x0B00 0240 LED 0x0B00 023F to 0x0B00 01E0 Reserved for future use 0x0B00 01DF to 0x0B00 01C0 RTC 2 0x0B00 01BF to 0x0B00 01A0 Reserved for future use 0x0B00 019F to 0x0B00 0180 KIU 0x0B00 017F to 0x...

Page 95: ...80 ICU 1 0x0A00 007F to 0x0A00 0050 Reserved for future use 0x0A00 004F to 0x0A00 0020 DCU 1 0x0A00 001F to 0x0A00 0000 MBA Host Bridge 4 2 4 DRAM space The DRAM space differs depending on the capacity of the DRAM being used The DRAM capacity is set via the B1Config 1 0 bits in the MEMCFG_REG register The physical addresses of the DRAM space are listed below Table 4 6 DRAM Address Map Physical add...

Page 96: ...initialization sequence during each mode that can be selected by the user A detailed description of the operation during and after a reset and its relationships to the power modes are also provided in CHAPTER 10 POWER MANAGEMENT UNIT PMU Remark that follows signal names indicates active low 5 1 Reset Function There are five ways to reset the VR4181 Each is summarized below ...

Page 97: ...completely initializes the processor s internal state Since the DRAM is not switched to self refresh mode the contents of DRAM after an RTC reset are not at all guaranteed After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset exception vectors in the ROM space Since only part of the internal status is reset when a re...

Page 98: ...o CHAPTER 10 POWER MANAGEMENT UNIT PMU After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset exception vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the VR4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Figure 5 2 RSTSW ...

Page 99: ...an s Switch reset are not at all guaranteed After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the VR4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Figure 5 3 Deadman s S...

Page 100: ...ly part of the internal status is reset when a reset occurs in the VR4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Cauiton The VR4181 does not set the DRAM to self refresh mode at the transition to Hibernate mode from Fullspeed mode To preserve DRAM data software must set the DRAM to self refresh mode For details refer to CHAPTER 10 POWER MANAGEMEN...

Page 101: ...egins to access the reset vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the VR4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Caution The VR4181 does not sets the DRAM to self refresh mode by HALTimer shutdown Therefore the contents of DRAM after a HALTimer shutdown are not at all guaranteed Figure 5 ...

Page 102: ...pin check is completed then the VR4181 is not activated If the BATTINH BATTINT pin s state is high the POWERON pin is deasserted and the MPOWER pin is asserted three RTC clocks after the BATTINH BATTINT pin check is completed then the VR4181 is activated Figure 5 6 shows a timing chart of VR4181 activation and Figure 5 7 shows a timing chart of when activation fails due to the BATTINH BATTINT pin ...

Page 103: ...3 Figure 5 7 VR4181 Activation Sequence When Activation Is NG Reset Internal ColdReset Internal MPOWER Output BATTINH BATTINT Input RTC Internal 32 768 kHz CPU not activated PLL Internal Check BATTINH BATTINT pin POWERON Output H Detection of activation factor L L L ...

Page 104: ...ig register are set to 0 and bits 22 to 3 to 0x04800 the other bits are undefined The values of the other registers are undefined Once power to the processor is established the ColdReset internal and the Reset internal signals are asserted and a Cold Reset is started After approximately 2 ms assertion the ColdReset signal is deasserted synchronously with the rising edge of MasterOut internal Then ...

Page 105: ...ared to 0 Any interrupts generated on the SysAD bus are cleared NMI is cleared The Config register is initialized A Soft Reset is started by assertion of the Reset signal and is completed at the deassertion of the Reset signal synchronized with the rising edge of MasterOut In general data in the CPU core is preserved for debugging purpose Upon reset the CPU core becomes bus master and drives the S...

Page 106: ...eral units 1 HALTimer Set the HALTIMERRST bit of the PMUCNTREG register in the PMU to 1 within 4 seconds after clearing the RTC reset or RSTSW reset This resets the HALTimer 2 Memory controller Before accessing the DRAM space be sure to initialize the registers in the memory controller Especially when SDRAM is used initialize SDRAM by executing the procedure described in 6 5 2 MEMCFG_REG 0x0A00 03...

Page 107: ...NITIALIZATION INTERFACE User s Manual U14272EJ3V0UM 107 5 4 3 Returning from power mode For initialization after the VR4181 has returned from the Hibernate mode or Suspend mode refer to 10 6 DRAM Interface Control ...

Page 108: ... resources The MBA Host Bridge can decode the entire physical address space to start appropriate bus accesses such as MBA requests MBA ISA protocols or external ROM accesses through the peripheral bus It also has functions as a host bridge to implement proper cycle timings and bus transaction protocols Figure 6 1 VR4181 Internal Bus Structure MBA Bus ISA Bridge Internal ISA Peripherals MBA Periphe...

Page 109: ...ds to the above addresses only upon a CPU access For any other addresses the Host Bridge initiates an MBA cycle to access an appropriate resources 6 1 2 MBA modules address space 1 Memory controller Physical address Type Device 0x03FF FFFF to 0x0000 0000 Memory range DRAM 0x0A00 03FF to 0x0A00 0300 I O range Control registers The MBA memory controller is selected when the above address ranges are ...

Page 110: ...s External ROM accesses and supply of clocks to several internal units are controlled by the bus control registers listed below Table 6 1 Bus Control Registers Physical address R W Register symbol Function 0x0A00 0000 R W BCUCNTREG1 BCU control register 1 0x0A00 0004 R W CMUCLKMSK Clock mask register 0x0A00 000C R W BCUSPEEDREG BCU access time parameters register 0x0A00 0010 R W BCURFCNTREG BCU re...

Page 111: ...r all banks Write strobe can be generated when this bit is set to 1 0 Disabled 1 Enabled 3 Reserved 0 is returned when read 2 1 Rtype 1 0 ROM type for all banks 00 Ordinary ROM 01 Flash memory 10 Page ROM 11 Reserved 0 RSTOUT RESET output control This bit does not affect GPIO21 RESET pin s state when this pin is not defined as RESET output 0 RESET is active low level 1 RESET is inactive high level...

Page 112: ...CLK Supply Mask Clocked Serial Interface CSI peripheral clock PCLK 0 Mask 1 Supply 5 MSKAIUPCLK Supply Mask Audio Interface AIU peripheral clock PCLK 0 Mask 1 Supply 4 MSKPIUPCLK Supply Mask Touch Panel Interface PIU peripheral clock PCLK 0 Mask 1 Supply 3 MSKADUPCLK Supply Mask A D converter and D A converter peripheral clock PCLK 0 Mask 1 Supply 2 MSKSIU18M Supply Mask Serial Interface 1 and 2 S...

Page 113: ... 3 5 TClock 011 4 5 TClock 100 5 5 TClock 101 6 5 TClock 110 7 5 TClock 111 8 5 TClock 11 to 4 Reserved 0 is returned when read 3 to 0 WROMA 3 0 ROM access speed 0000 1 5 TClock 0001 2 5 TClock 0010 3 5 TClock 0011 4 5 TClock 0100 5 5 TClock 0101 6 5 TClock 0110 7 5 TClock 0111 8 5 TClock 1000 9 5 TClock 1001 10 5 TClock 1010 11 5 TClock 1011 12 5 TClock 1100 13 5 TClock 1101 14 5 TClock 1110 15 5...

Page 114: ...lid Valid b PageROM cycle WROMA 3 0 ADD 2 0 output TClock internal ADD 21 3 output DATA 15 0 read ROMCS 3 0 output WPROM 2 0 Valid Valid Valid Valid Valid Remarks1 ROMCS 2 0 signals are alternated with general purpose I O signals and are defined as general purpose inputs after RTC reset Set GPMD2REG and GPMD3REG registers in the GIU to use them as ROMCS 2 0 2 A circle in the figure indicates the s...

Page 115: ...e is obtained by following expression Refresh rate BRF 13 0 x TClock period For example to select a 15 6 µs refresh rate with a 50 MHz TClock BRF 13 0 15600 ns 20 ns 0x30C Remarks1 When the IORDY signal does not become high level though the DRAM refresh rate has elapsed during the external ISA memory or I O cycles a DRAM refresh cycle may be lost 2 Refresh timing is generated from detecting match ...

Page 116: ...Read only This register is used to indicate the revision of the VR4181 The relationship between the values and the revision of the VR4181 is as follows VR4181 Revision RID 3 0 MJREV 3 0 MINREV 3 0 1 0 0x0 0x0 0x0 1 1 0x0 0x0 0x1 1 2 0x0 0x0 0x2 1 3 0x0 0x0 0x2 Even if the CPU core or the peripheral unit has been changed there is no guarantee that REVIDREG register will be reflected or that the cha...

Page 117: ... the CPU core operating clock PClock frequency The following expression is used to calculate the PClock and TClock frequency 1 CPU core clock PClock PClock 18 432 MHz CLKSP 4 0 x 64 2 Peripheral clock TClock DIV 2 4 Ratio Mode 111 TClock PClock 1 Div1 mode 011 TClock PClock 2 Div2 mode 101 TClock PClock 3 Div3 mode Others Reserved Remark PClock frequency is decided by CLKSEL 2 0 pin statuses durin...

Page 118: ...ng Physical address 32 Mbit ROM 64 Mbit ROM 0x1FFF FFFF to 0x1FC0 0000 Bank 3 ROMCS3 Bank 3 ROMCS3 0x1FBF FFFF to 0x1F80 0000 Bank 2 ROMCS2 0x1F7F FFFF to 0x1F40 0000 Bank 1 ROMCS1 Bank 2 ROMCS2 0x1F3F FFFF to 0x1F00 0000 Bank 0 ROMCS0 0x1EFF FFFF to 0x1E80 0000 Reserved Bank 1 ROMCS1 0x1E7F FFFF to 0x1E00 0000 Reserved Bank 0 ROMCS0 Bank 3 contains boot vector and has a dedicated pin for chip sel...

Page 119: ...Mbits x 16 VR4181 pin CPU core physical address line VR4181 pin CPU core physical address A21 ADD21 adr22 A20 ADD20 adr21 ADD20 adr21 A19 ADD19 adr20 ADD19 adr20 A18 ADD18 adr19 ADD18 adr19 A17 ADD17 adr18 ADD17 adr18 A16 ADD16 adr17 ADD16 adr17 A15 ADD15 adr16 ADD15 adr16 A14 ADD14 adr15 ADD14 adr15 A13 ADD13 adr14 ADD13 adr14 A12 ADD12 adr13 ADD12 adr13 A11 ADD11 adr12 ADD11 adr12 A10 ADD10 adr1...

Page 120: ... A 20 0 D 15 0 A 20 0 ROMCS0 ROM Bank1 ROM Bank0 ADD 20 0 ROMCS2 ROMCS1 DATA 15 0 ROM Bank3 ROM Bank2 ROMCS3 A 20 0 A 20 0 D 15 0 D 15 0 D 15 0 2 64 Mbit ordinary ROM A 21 0 D 15 0 A 21 0 ROMCS0 ROM Bank1 ROM Bank0 ADD 21 0 ROMCS2 ROMCS1 DATA 15 0 ROM Bank3 ROM Bank2 ROMCS3 A 21 0 A 21 0 D 15 0 D 15 0 D 15 0 ...

Page 121: ... number when using a PageROM is 8 halfwords i e 128 bits 1 word 32 bits CE CE CE CE A 1 1 DW W A 19 2 ROMCS0 A 19 2 D 15 0 A 19 2 Page ROM Bank1 Page ROM Bank0 ADD 20 3 ROMCS2 ROMCS1 DATA 15 0 Page ROM Bank3 Page ROM Bank2 ROMCS3 A 19 2 A 1 1 D 15 0 D 15 0 D 15 0 A 1 1 A 1 1 DW W DW W DW W ADD 2 0 ...

Page 122: ... number when using a PageROM is 8 halfwords i e 128 bits 1 word 32 bits CE CE CE CE A 1 1 DW W A 20 2 ROMCS0 A 20 2 D 15 0 A 20 2 Page ROM Bank1 Page ROM Bank0 ADD 21 3 ROMCS2 ROMCS1 DATA 15 0 Page ROM Bank3 Page ROM Bank2 ROMCS3 A 20 2 A 1 1 D 15 0 D 15 0 D 15 0 A 1 1 A 1 1 DW W DW W DW W ADD 2 0 ...

Page 123: ... 20 1 Flash memory Bank1 Flash memory Bank0 ADD 19 0 DATA 15 0 Flash memory Bank3 Flash memory Bank2 A 20 1 CE0 D 15 0 D 15 0 D 15 0 OE WE CE0 OE WE CE0 OE WE CE1 CE2 CE1 CE2 CE1 CE2 CE1 RDY BSY Flash ReadyNote ADD20 Note There is no corresponding pin in the VR4181 Use one of the GPIO pins for this function Remark Use one of the GPIO pins in the VR4181 to control ON OFF of VPP program erase supply...

Page 124: ...Bank1 Flash memory Bank0 ADD 21 0 ROMCS2 ROMCS1 DATA 15 0 Flash memory Bank3 Flash memory Bank2 ROMCS3 A 21 0 CE0 D 15 0 D 15 0 D 15 0 OE WE CE0 OE WE CE0 OE WE CE1 CE2 CE1 CE2 CE1 CE2 CE1 STS Flash StatusNote Note There is no corresponding pin in the VR4181 Using one of the GPIO pins for this function Remark Using one of the GPIO pins in the VR4181 to control ON OFF of VPP program erase supply vo...

Page 125: ...al ROM cycles depending on the settings in the bus control register and bus speed control register 1 Ordinary ROM read cycle Figure 6 3 Ordinary ROM Read Cycle WROMA 3 0 0101 TClock internal ADD 21 0 output MEMRD output DATA 15 0 read ROMCS 3 0 output WROMA 3 0 Valid Valid Remark A circle in the figure indicates the sampling timing ...

Page 126: ... WPROM 2 0 001 Adr0 TClock internal ADD 21 0 output MEMRD output DATA 15 0 read ROMCS 3 0 output WROMA 3 0 L WPROM 2 0 Adr1 Adr2 Adr3 Adr4 Adr5 Adr6 Adr7 Data1 Data4 Data3 Data2 Data6 Data5 Data7 Data0 WPROM 2 0 WPROM 2 0 WPROM 2 0 WPROM 2 0 WPROM 2 0 WPROM 2 0 Remark A circle in the figure indicates the sampling timing ...

Page 127: ...lock internal ADD 21 0 output MEMRD output DATA 15 0 read ROMCS 3 0 output WROMA 3 0 Valid Valid Remark A circle in the figure indicates the sampling timing 4 Flash memory write cycle Figure 6 6 Flash Memory Write Cycle Rtype 1 0 01 WROMA 3 0 0100 TClock internal ADD 21 0 output MEMWR output DATA 15 0 write ROMCS 3 0 output WROMA 3 0 Valid Valid ...

Page 128: ... MEMWR WE RAS0 UCAS ADD 12 0 DATA 15 0 VR4181 EDO DRAM Bank0 A 12 0 D 15 0 RAS RAS1 OE LCAS UCAS LCAS OE Figure 6 7 illustrates an example when connecting devices of 4 Mbits x 16 Addresses when connecting devices of 16 Mbits or 64 Mbits are mapped as follows DRAM bank Physical address 16 Mbits Physical address 64 Mbits Bank 0 0x001F FFFF to 0x0000 0000 0x007F FFFF to 0x0000 0000 Bank 1 0x003F FFFF...

Page 129: ...2 MB 16 Mbits 16 Mbits 4 MB 64 Mbits 0 8 MB 16 Mbits 64 Mbits 10 MB 64 Mbits 16 Mbits 10 MB 64 Mbits 64 Mbits 16 MB 6 4 3 EDO DRAM timing parameters The following table shows examples of EDO DRAM timing parameters when using EDO DRAMs with access time of 60 ns These parameters are set in EDOMCYTREG register TClock frequency RAS to CAS delay CAS pulse width CAS precharge RAS precharge RAS pulse wid...

Page 130: ... Bank1 MEMWR WE SDCLK SDRAS ADD 13 0 CLKEN VR4181 SDRAM Bank0 A 13 0 CKE CLK SDCS1 CAS RAS CAS Figure 6 8 illustrates an example when connecting devices of 4 Mbits x 16 Remark The SDRAMs supported by the VR4181 are as follows Capacity Configuration Address pins Bank address 16 Mbits 512 Kbits x 16 x 2 banks A 10 0 A11 64 Mbits 2 Mbits x 16 x 2 banks A 12 0 A13 64 Mbits 1 Mbits x 16 x 4 banks A 11 ...

Page 131: ... mode 6 5 1 EDOMCYTREG 0x0A00 0300 1 2 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved SrefRpre2 SrefRpre1 SrefRpre0 Caspre1 Caspre0 R W R R R R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Rcasdly1 Rcasdly0 Tcas1 Tcas0 Trp1 Trp0 Tras1 Tras0 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 13 Reserved 0 is returned when read 12 t...

Page 132: ...AS precharge time 00 1 TClock 01 2 TClock 10 3 TClock 11 4 TClock 1 0 Tras 1 0 RAS pulse width 00 2 TClock 01 3 TClock 10 5 TClock 11 6 TClock This register is used to set EDO DRAM timing parameters Software must set these parameters suitable before using DRAM Remark Do not set Tcas 1 2 TClock and Caspre 1 TClock or Tcas 1 TClock and Caspre 1 2 TClock at the same time ...

Page 133: ...turned when read 11 10 B1Config 1 0 Bank 1 capacity 00 Bank 1 is not installed 01 16 Mbits 10 64 Mbits 11 Reserved 9 Reserved 0 is returned when read 8 Bstreftype Burst refresh type This bit determines the number of CBR burst refresh cycles executed before entering and exiting self refresh mode 0 8 rows refreshed 1 All rows refreshed 7 BstRefr Burst refresh enable This bit enables or disables burs...

Page 134: ...r the VR4181 restores from the Hibernate mode An initialization of SDRAMs must be executed until the VR4181 issues the first CBR auto refresh cycle Remark During the 64 Mbit SDRAM mode register write A13 of the address bus is at high level On the other hand during the 16 Mbit SDRAM mode register write A13 is at low level In order to initialize 64 Mbit SDRAM correctly software must execute the foll...

Page 135: ...to 0 8 7 TE Ven 1 2 These two bits define a JEDEC test cycle and vendor specific cycles These bits should be always written to 00 6 to 4 LTMode 2 0 CAS latency mode Note 010 2 clocks 011 3 clocks Others Reserved 3 WT Wrap type for the burst cycles This bit should be always written to 0 0 Sequential default 2 to 0 BL 2 0 Burst length These bits should be always written to 111 111 Full page When WT ...

Page 136: ...0 3 SDCLK for 25 MHz SDCLK 01 5 SDCLK for 66 50 or 33 MHz SDCLK Others Prohibited 5 4 TRC 1 0 TRC in clock cycles 00 4 SDCLK for 25 MHz SDCLK 01 7 SDCLK for 66 50 or 33 MHz SDCLK Others Prohibited 3 2 TRP 1 0 TRP in clock cycles 00 1 SDCLK for 25 MHz SDCLK 01 Prohibited 10 3 SDCLK for 66 50 or 33 MHz SDCLK 11 Prohibited 1 0 TRCD 1 0 TRCD in clock cycles 00 1 SDCLK for 25 MHz SDCLK 01 2 SDCLK for 6...

Page 137: ...the external ISA bus UBE IOCS16 IORDY IOWR and IORD share the pins with GPIO 20 16 as well as MEMCS16 with LOCLK To use these pins as an external ISA bus interface make settings in the GIU in advance 6 7 ISA Bridge Register Set The following registers provide configuration and control of the ISA Bridge Table 6 4 ISA Bridge Registers Physical address R W Register symbol Function 0x0B00 02C0 R W ISA...

Page 138: ...served Reserved Reserved Reserved PCLKDIV1 PCLKDIV0 R W R R R R R R R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 2 Reserved 0 is returned when read 1 0 PCLKDIV 1 0 PCLK peripheral clock divisor rate selection These bits select the operating frequency of PCLK 00 TClock 8 01 TClock 4 10 TClock 2 11 TClock 1 This register is used to set the PCLK divisor rate PCL...

Page 139: ...R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDLE R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 1 Reserved 0 is returned when read 0 IDLE ISA Bridge status 0 ISA Bridge is busy 1 ISA Bridge is idle This register shows the ISA Bridge operation status...

Page 140: ...fter finishing an external ISA cycle and obtains results of the read Normally set 1 to this bit 9 INTRESULT Internal ISA result cycle enable 0 Disabled The MBA bus arbiter waits until an internal ISA read is finished 1 Enabled The MBA bus arbiter issues a result cycle to the ISA bridge after finishing an internal ISA cycle and obtains results of the read Normally set 1 to this bit 8 EXBUFFEN Exter...

Page 141: ...urned when read 1 0 SCLKDIV 1 0 SYSCLK external ISA bus clock divisor rate selection 00 PCLK 2 01 PCLK 3 10 PCLK 6 11 PCLK 8 This register is used to set the external ISA configurations SYSCLK is an operation clock for the external ISA bus and is output only when an external ISA cycle is generated ...

Page 142: ...alid DMA data Software may configure any of the DMA channels to operate in one of two modes auto stop or auto load When a channel is configured to operate in auto stop mode the DCU terminates DMA transfers after the number of transfers specified by the record length register and automatically resets the DMA mask bit for that channel Once the mask bit is automatically reset the DCU ignores all subs...

Page 143: ...t memory read from DRAM and stores the read data into the temporary storage register The DCU then transfers data from this register to the target I O device For a 16 bit device such as the Speaker channel the DCU performs two I O writes to the D A converter for each memory read During DMA transfers all DCU registers are write protected if valid data is present in the temporary storage registers Be...

Page 144: ... R W SPKRSRC2REG1 Speaker source 2 address register 1 0x0A00 002E R W SPKRSRC2REG2 Speaker source 2 address register 2 0x0A00 0040 R W DMARSTREG DMA reset register 0x0A00 0046 R W AIUDMAMSKREG Audio DMA mask register 0x0A00 0600 to 0x0A00 0654 R W Reserved Write 0 when write 0 is returned after a read 0x0A00 0658 R W MICRCLENREG Microphone record length register 0x0A00 065A R W SPKRCLENREG Speaker...

Page 145: ...me Function 15 to 0 MD1A 15 0 Lower 16 bits A 15 0 of DMA destination 1 address for Microphone 2 MICDEST1REG2 0x0A00 0022 Bit 15 14 13 12 11 10 9 8 Name MD1A31 MD1A30 MD1A29 MD1A28 MD1A27 MD1A26 MD1A25 MD1A24 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name MD1A23 MD1A22 MD1A21 MD1A20 MD1A19 MD1A18 MD1A17 MD1A16 R W R W R W R W R W R W R W R W R W At reset 0 0 ...

Page 146: ...e Function 15 to 0 MD2A 15 0 Lower 16 bits A 15 0 of DMA destination 2 address for Microphone 2 MICDEST2REG2 0x0A00 0026 Bit 15 14 13 12 11 10 9 8 Name MD2A31 MD2A30 MD2A29 MD2A28 MD2A27 MD2A26 MD2A25 MD2A24 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name MD2A23 MD2A22 MD2A21 MD2A20 MD2A19 MD2A18 MD2A17 MD2A16 R W R W R W R W R W R W R W R W R W At reset 0 0 0...

Page 147: ... 0 Bit Name Function 15 to 0 SS1A 15 0 Lower 16 bits A 15 0 of DMA source 1 address for Speaker 2 SPKRSRC1REG2 0x0A00 002A Bit 15 14 13 12 11 10 9 8 Name SS1A31 SS1A30 SS1A29 SS1A28 SS1A27 SS1A26 SS1A25 SS1A24 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name SS1A23 SS1A22 SS1A21 SS1A20 SS1A9 SS1A18 SS1A17 SS1A16 R W R W R W R W R W R W R W R W R W At reset 0 0 ...

Page 148: ...0 Bit Name Function 15 to 0 SS2A 15 0 Lower 16 bits A 15 0 of DMA source 2 address for Speaker 2 SPKRSRC2REG2 0x0A00 002E Bit 15 14 13 12 11 10 9 8 Name SS2A31 SS2A30 SS2A29 SS2A28 SS2A27 SS2A26 SS2A25 SS2A24 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name SS2A23 SS2A22 SS2A21 SS2A20 SS2A9 SS2A18 SS2A17 SS2A16 R W R W R W R W R W R W R W R W R W At reset 0 0 0...

Page 149: ...mmediately terminated and the DCU enters in the reset state While DMARST bit is 0 all DMA requests become pending until this bit is set to 1 7 2 6 AIUDMAMSKREG 0x0A00 0046 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R R R R R R At reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved MICMSK SPKMSK Reser...

Page 150: ...st be written to zero This register defines the number of 16 bit words to be transferred during DMA operation in the Microphone channel 7 2 8 SPKRCLENREG 0x0A00 065A Bit 15 14 13 12 11 10 9 8 Name SPKRL15 SPKRL14 SPKRL13 SPKRL12 SPKRL11 SPKRL10 SPKRL9 SPKRL8 R W R W R W R W R W R W R W R W R W At reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 Name SPKRL7 SPKRL6 SPKRL5 SPKRL4 SPKRL3 SPKRL2 SPKRL1 SPKRL0...

Page 151: ...3 MicDsize 1 0 Indicates Microphone channel data size 01 16 bits Values other than above do not appear 12 MicSrctype Indicates Microphone channel source address type 1 I O 0 does not appear 11 MicDestype Indicates Microphone channel destination address type 0 Memory 1 does not appear 10 9 Reserved 0 is returned after a read 8 MicLoad DMA auto stop auto load mode setting for Microphone channel 0 Au...

Page 152: ...0 is returned after a read 6 5 SpkDsize 1 0 Indicates Speaker channel data size 01 16 bits Values other than above do not appear 4 SpkSrctype Indicates Speaker channel source address type 0 Memory 1 does not appear 3 SpkDestype Indicates Speaker channel destination address type 1 I O 0 does not appear 2 1 Reserved 0 is returned after a read 0 SpkLoad DMA auto stop auto load mode setting for Speake...

Page 153: ...peaker channel end of process EOP interrupt status 0 None 1 Speaker channel EOP interrupt pending The interrupt request is cleared when this bit is written to 1 4 MicEOP Microphone channel EOP interrupt status 0 None 1 Microphone channel EOP interrupt pending The interrupt request is cleared when this bit is written to 1 3 Reserved 0 is returned after a read 2 1 Reserved Write 0 when write 0 is re...

Page 154: ...eserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Bit Name Function 15 14 SpkCNT 1 0 Speaker channel source address count control 00 Increment 01 Decrement Others Reserved 13 12 MicCNT 1 0 Microphone channel destination address count control 00 Increment 01 Decrement Others Reserved 11 to 8 Reserved 0 is returned aft...

Page 155: ...erved Reserved SpkEOPMsk MicEOPMsk Reserved Reserved Reserved Reserved R W R R R W R W R R W R W R At reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 6 Reserved 0 is returned after a read 5 SpkEOPMsk Speaker channel end of process EOP interrupt mask 0 Disable 1 Enable 4 MicEOPMsk Microphone channel EOP interrupt mask 0 Disable 1 Enable 3 Reserved 0 is returned after a read 2 1 Reserved Write 0 when ...

Page 156: ...rol input In one mode FRM determines data direction transmit or receive In the other mode FRM enables low level or inhibits high level transmissions GPIO2 SCK Serial clock input Maximum frequency 1 6 MHz GPIO1 SO Serial data output GPIO0 SI Serial data input Caution No clock is supplied to the CSI in the initial state When using the CSI set the MSKCSUPCLK bit of the CMUCLKMSK register in the MBA H...

Page 157: ... D4 D3 D2 D1 b When CKMD bit 1 SCK input when CKPOL 0 SCK input when CKPOL 1 SO output SI input Undefined D7 D6 D0 D5 D4 D3 D2 D1 Caution When the CKMD bit is set to 1 the next byte data is output during the latter half of the cycle for the eighth bit of a transmit data This figure illustrates CSI cycles when the FRM input is disabled FRMEN bit 0 or configured to provide direction control FRMEN bi...

Page 158: ...er must output the first data bit before the first falling edge of SCK The VR4181 samples receive data synchronizing with the falling edge of SCK Therefore the external master must output data synchronizing with the rising edge of SCK 3 When CKMD bit 1 and CKPOL bit 0 Transmission The first transmit data bit is output synchronized with the first rising edge of SCK The second transmit data bit and ...

Page 159: ...d compared to the corresponding burst length value transmit and or receive If the number of bits transferred is equal to the burst length the CSI shift register is halted If the transfer is a reception the contents of the shift register will be copied to the receive FIFO a Receive Burst End interrupt request will be generated if unmasked and additional activities on the SCK input will be ignored I...

Page 160: ...rs when the transmit shift register attempts to load a value from the FIFO which has not been updated by the CPU core 1 Overrun underrun errors When an overrun error occurs the receive FIFO logic generates an overrun interrupt request if unmasked and overwrites the next location in the FIFO with the contents of the receive shift register When an underrun error occurs the transmit FIFO logic genera...

Page 161: ...set by FRMMD bit 14 TXEN CSI transmit enable 0 Disable 1 Enable Remark When using the transmit function only communication must be performed with the RXEN bit 0 and the RXCLR bit 1 13 TXBMD CSI transmit burst mode 0 Continuous mode 1 Burst mode 12 TXCLR CSI transmit buffer clear 0 Enable transmit shift register and FIFO 1 Reset transmit shift register and FIFO 11 Reserved 0 is returned after read ...

Page 162: ...cter data is valid prior to the 1st transition of SCK 1 Character data is valid at the 1st transition of SCK 4 to 1 Reserved 0 is returned after read 0 LSBMSB Transmit receive mode bit ordering 0 Bit 7 is the first bit transmitted or received MSB mode 1 Bit 0 is the first bit transmitted or received LSB mode Note The TXCLR and RXCLR bits must be cleared after changing the CKPOL or CKMD bit The CKP...

Page 163: ... 0 0 0 0 Bit Name Function 15 to 0 RXD 15 0 CSI receive data CSI data received on the SI pin is read through these data bits 8 3 3 CSITXDATA 0x0B00 0904 Bit 15 14 13 12 11 10 9 8 Name TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 R W R W R W R W R...

Page 164: ...are free in transmit FIFO 10 4 or more words are free in transmit FIFO 11 Reserved 13 to 11 Reserved 0 is returned after read 10 TXFIFOF CSI transmit FIFO full status This bit is set to 1 when the transmit FIFO contains no free space 0 Transmit FIFO not full 1 Transmit FIFO full 9 TXFIFOE CSI transmit FIFO empty status This bit is set to 1 when the transmit FIFO reaches to the empty level defined ...

Page 165: ...ter read 2 RXFIFOF CSI receive FIFO full status This bit is set to 1 when the receive FIFO reaches to the full level defined by RFIFOT bits 0 Receive FIFO not full 1 Receive FIFO full 1 RXFIFOE CSI receive FIFO empty status This bit is set to 1 when the receive FIFO contains no valid data 0 Receive FIFO not empty 1 Receive FIFO empty 0 RXBUSY CSI receive shift register status 0 Idle 1 Character re...

Page 166: ...s returned after read 11 MUNDRN Mask of transmit FIFO underrun interrupt requests 0 Unmasked 1 Masked 10 MTXBEND Mask of Transmit Burst End interrupt requests 0 Unmasked 1 Masked 9 MTXFIFOE Mask of Transmit FIFO Empty interrupt requests 0 Unmasked 1 Masked 8 MTXBUSY Mask of Transmit Shift Register Busy interrupt requests 0 Unmasked 1 Masked 7 to 4 Reserved 0 is returned after read 3 MOVRRN Mask of...

Page 167: ...me Function 15 to 12 Reserved 0 is returned after read 11 URNINT Transmit FIFO Underrun interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 10 TXBEINT Transmit Burst End interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 9 TXFEINT Transmit FIFO Empty interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 8 TXBS...

Page 168: ...rst End interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 1 RXFFINT Receive FIFO Full interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 0 RXBSYINT Receive Shift Register Busy interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 ...

Page 169: ...ets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name TXBLN7 TXBLN6 TXBLN5 TXBLN4 TXBLN3 TXBLN2 TXBLN1 TXBLN0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 0 TXBLN 15 0 Transmit burst length These bits determine the number of bits transmitted during one burst cycle 0x0000 Reserved 0x0001 1 bit 0x0002 2 bits 0x00FD 253 bits 0x00FE 254 bits 0x...

Page 170: ...esets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name RXBLN7 RXBLN6 RXBLN5 RXBLN4 RXBLN3 RXBLN2 RXBLN1 RXBLN0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 0 RXBLN 15 0 Receive burst length These bits determine the number of bits received during one burst cycle 0x0000 Reserved 0x0001 1 bit 0x0002 2 bits 0x00FD 253 bits 0x00FE 254 bits 0x00...

Page 171: ...egister of Level 2 xxxINTREG is set to 1 The interrupt indication register is ANDed bit wise with the corresponding interrupt mask register of Level 2 MxxxINTREG If the occurred interrupt request is enabled set to 1 in the mask register the interrupt request is notified to the interrupt indication register of Level 1 SYSINTREG and the corresponding bit is set to 1 At this time the interrupt reques...

Page 172: ...UINTREG MAIUINTREG AIUINTREG dmaint Dual Stage Synchronizer Int2 Int1 NMI Int0 MSYSINT1REG MSYSINT2REG battint powerint rtclong2int rtclong1int csuint SYSINT1REG SYSINT2REG lcdint ledint AND OR MKIUINTREG KIUINTREG Dual Stage Synchronizer SOFTINTREG Selector AND OR AND TClock MasterClock 3 5 AND 10 10 4 4 Level 2 registers and signals from peripheral units Level 1 registers 8 3 3 3 3 6 6 ...

Page 173: ...W NMIREG NMI register 0x0A00 009A R W SOFTINTREG Software interrupt register 0x0A00 0200 R SYSINT2REG Level 1 system register 2 0x0A00 0206 R W MSYSINT2REG Level 1 mask system register 2 0x0B00 0082 R PIUINTREG Level 2 PIU register 0x0B00 0084 R AIUINTREG Level 2 AIU register 0x0B00 0086 R W KIUINTREG Level 2 KIU register 0x0B00 008E R W MPIUINTREG Level 2 mask PIU register 0x0B00 0090 W MAIUINTRE...

Page 174: ...R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 14 Reserved 0 is returned when read 13 DOZEPIUINTR PIU interrupt request during Suspend mode 0 Not occurred 1 Occurred 12 Reserved 0 is returned when read 11 SOFTINTR Software interrupt request 0 Not occurred 1 Occurred 10 Reserved 0 is returned when read 9 SIUINTR SIU interrupt request 0 Not occurred 1 Oc...

Page 175: ...erved 0 is returned when read 3 ETIMERINTR ElapsedTime interrupt request 0 Not occurred 1 Occurred 2 RTCL1INTR RTCLong1 interrupt request 0 Not occurred 1 Occurred 1 POWERINTR Power switch interrupt request 0 Not occurred 1 Occurred 0 BATINTR Battery low interrupt request 0 Not occurred 1 Occurred This register indicates level 1 interrupt requests status ...

Page 176: ... MPOWER INTR MBATINTR R W R W R W R W R R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 14 Reserved 0 is returned when read 13 MDOZEPIUINTR Enables PIU interrupt during Suspend mode 0 Disable 1 Enable 12 Reserved 0 is returned when read 11 MSOFTINTR Enables software interrupt 0 Disable 1 Enable 10 Reserved 0 is returned when read 9 MSIUINTR Enables SIU inte...

Page 177: ...le 4 Reserved 0 is returned when read 3 METIMERINTR Enables ElapsedTime interrupt 0 Disable 1 Enable 2 MRTCL1INTR Enables RTCLong1 interrupt 0 Disable 1 Enable 1 MPOWERINTR Enables Power switch interrupt 0 Disable 1 Enable 0 MBATINTR Enables battery low interrupt 0 Disable 1 Enable This register is used to enable disable level 1 interrupts ...

Page 178: ...s 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved NMIORINT R W R R R R R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 1 Reserved 0 is returned when read 0 NMIORINT Battery low interrupt request routing 0 NMI 1 Int0 This register is used to set the interrupt request signal used to notify the VR4110 CPU co...

Page 179: ... 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SOFTINTR R W R R R R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 1 Reserved 0 is returned when read 0 SOFTINTR Set clear a software interrupt request This bit is a write only bit Software interrupt request pending status is reported in the SYSINT1REG 0x0A000080 0 C...

Page 180: ...R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 7 Reserved 0 is returned when read 6 LCDINTR LCD interrupt request 0 Not occurred 1 Occurred 5 DMAINTR DMA interrupt request 0 Not occurred 1 Occurred 4 Reserved 0 is returned when read 3 CSUINTR CSI interrupt request 0 Not occurred 1 Occurred 2 ECUINTR CompactFlash interrupt request 0 Not occurred 1 Occurred 1 L...

Page 181: ... R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 7 Reserved 0 is returned when read 6 MLCDINTR Enables LCD interrupt 0 Disable 1 Enable 5 MDMAINTR Enables DMA interrupt 0 Disable 1 Enable 4 Reserved Write 0 when write 0 is returned when read 3 MCSUINTR Enables CSI interrupt 0 Disable 1 Enable 2 MECUINTR Enables CompactFlash interrupt 0 Disabl...

Page 182: ...ADADPINTR PIU AD Port Scan interrupt request This interrupt request occurs when a valid data is obtained during an A D port scan 0 Not occurred 1 Occurred 4 PADPAGE1INTR PIU data buffer page 1 interrupt request This interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer 0 Not occurred 1 Occurred 3 PADPAGE0INTR PIU data buffer page 0 interrupt request This inte...

Page 183: ...interrupt request received data is lost This interrupt request occurs if a valid data exists in the MIDATREG register when data is received from the A D converter 0 Not occurred 1 Occurred 8 INTMST Audio input microphone receive completion interrupt request This interrupt request occurs when a 10 bit converted data from the A D converter is received 0 Not occurred 1 Occurred 7 to 2 Reserved 0 is r...

Page 184: ...Keyboard Data Lost interrupt request This interrupt request occurs if the KIUDAT0 register is updated with the next key data prior to being read by the CPU core 0 Not occurred 1 Occurred This bit is cleared by writing 1 1 KDATRDY Keyboard Data Ready interrupt request This interrupt request occurs when a set of scanning is completed and all the KIUDAT registers are updated 0 Not occurred 1 Occurred...

Page 185: ...ST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 7 Reserved 0 is returned when read 6 PADCMDINTR Enables PIU command scan interrupt 0 Disable 1 Enable 5 PADADPINTR Enables PIU A D Port Scan interrupt 0 Disable 1 Enable 4 PADPAGE1INTR Enables PIU data buffer page 1 interrupt 0 Disable 1 Enable 3 PADPAGE0INTR Enables PIU data buffer page 0 interrupt 0 Disable 1 Enable 2 PADDLO...

Page 186: ...W W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 10 Reserved Write 0 when write 9 INTMIDLE Enables audio input microphone idle interrupt received data is lost 0 Disable 1 Enable 8 INTMST Enables audio input microphone receive completion interrupt 0 Disable 1 Enable 7 to 2 Reserved Write 0 when write 1 INTSIDLE Enables audio output speaker idle interrupt mute 0 Disabl...

Page 187: ... 0 0 Bit Name Function 15 to 3 Reserved 0 is returned when read 2 MSKKDATLOST Enables Keyboard Data Lost interrupt 0 Disable 1 Enable This bit may be used to temporarily mask the Keyboard Data Lost interrupt request and does not affect Keyboard Data Lost event detection 1 MSKKDATRDY Enables Keyboard Data Ready interrupt 0 Disable 1 Enable This bit may be used to temporarily mask the Keyboard Data ...

Page 188: ...er Mode This section describes the VR4181 power modes in detail The VR4181 supports the following four power modes Fullspeed mode Standby mode Suspend mode Hibernate mode 10 2 1 Power mode and state transition The VR4181 transits from Fullspeed mode to Standby mode Suspend mode or Hibernate mode by executing a STANBY SUSPEND or HIBERNATE instruction respectively An RTC reset is always valid in eve...

Page 189: ...POWER Assertion and then deassertion of RSTSW Interrupt request such as ElapsedTime timer Key press DCD1 SIU1 RTCLong1 Pen touch CF_BUSY RTCLong2 GPIO 15 0 BATTINTR 5 HIBERNATE instruction After transition DRAM self refresh Deassertion of MPOWER 6 Assertion of POWER Interrupt request such as ElapsedTime timer GPIO 15 0 DCD1 CF_BUSY 7 Assertion of RTCRST After transition Deassertion of MPOWER 8 Ass...

Page 190: ...e operation stops To restore to Fullspeed mode generate an interrupt request of any kind When the processor restores to Fullspeed mode from Standby mode it starts a program execution from the General exception vector 0xBFC0 0380 when BEV 0 or 0x8000 0180 when BEV 1 3 Suspend mode The pipeline clock PClock of the CPU core and the internal bus clocks TClock and PCLK are fixed to high level PLL timer...

Page 191: ...Reset exception vector 0xBFC0 0000 10 3 Reset Control The operations of the RTC peripheral units and CPU core and PMUINTREG register bit settings during a reset are listed below Table 10 2 Operations During Reset Reset type RTC GIU Peripheral units CPU core PMUINTREG bits RTC reset Reset Reset Cold Reset RTCRST 1 RSTSW reset 1 Active Reset Cold Reset RSTSW 1 SDRAM 0 RSTSW reset 2 Active Active Col...

Page 192: ... and PMU Then the PMU resets Cold Reset the CPU core In addition DMSRST bit in the PMUINTREG register is set to 1 After the CPU core is restarted DMSRST bit must be checked and cleared to 0 by software 10 3 4 Preserving DRAM data on RSTSW reset 1 Preserving EDO DRAM data When an RSTSW reset takes place the PMU activates the CAS RAS pins to generate a CBR self refresh request to EDO DRAM Remark The...

Page 193: ... seconds after the CPU core is activated or the RSTSW reset is canceled the PMU resets all peripheral units except for RTC and PMU Then the PMU resets Cold Reset the CPU core In addition TIMOUTRST bit in PMUINTREG register is set to 1 After the CPU core is restarted TIMOUTRST bit must be checked and cleared to 0 by software 10 4 2 Software shutdown When the HIBERNATE instruction is executed the PM...

Page 194: ...CRST When MPOWER signal is at low level Hibernate mode or during CPU core activation to stop supplying voltage to the 2 5 V power supply systems is recommended to reduce leak current This means that this power supply can be 0 V while the MPOWER signal is inactive The following operation will not be affected by supplying voltage of 2 3 V or more to this power supply within the period from when the ...

Page 195: ...set sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software Remark Activation via Power Switch interrupt request never sets the POWERSWINTR bit in the PMUINTREG register to 1 Figure 10 3 Activatio...

Page 196: ... PMU cancels peripheral unit reset and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software Figure 10 5 Activation via CompactFlash Interrupt Request BATTINH H BATTINH BAT...

Page 197: ...If the BATTINH signal is at high level the PMU cancels the peripheral unit reset and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software The CPU core sets 1 to the GPWAKE...

Page 198: ...indicate whether a DCD interrupt has occurred but instead reflects the current status of the DCD1 pin Cautions1 The PMU cannot recognize changes in the DCD1 signal while the POWER signal is asserted If the DCD1 state when the POWER signal is asserted is different from that when the POWER signal is deasserted the change in the DCD1 signal is detected only after the POWER signal is deasserted Howeve...

Page 199: ...gure 10 9 Activation via DCD Interrupt Request BATTINH H BATTINH BATTINT Input MPOWER Output POWERON Output DCD1 Input RTC Internal H Figure 10 10 Activation via DCD Interrupt Request BATTINH L BATTINH BATTINT Input MPOWER Output L L POWERON Output DCD1 Input RTC Internal ...

Page 200: ...he Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software Caution The ElapsedTime interrupt is ignored while the POWERON signal is active After the POWERON signal becomes inactive the ...

Page 201: ...CLKMSK register in the MBA Host Bridge 5 If DRAM can accept mixed use of burst and distributive CBR refresh set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR refresh cycles for a specific time period i e 0x3FFF TClock period burst refresh interval required by DRAM 6 Set 0x3FF to the BCURFCNTREG register in the MBA Host...

Page 202: ...es are needed set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR auto refresh cycles for a specific time period i e 0x3FFF TClock period burst refresh interval required by DRAM 7 Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst refresh Then set SUSPEND bit in the DRAMHIBC...

Page 203: ... register until it is set to 1 7 Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in the general purpose registers MISCREG 0 15 which retain values during Hibernate mode in the GIU or in external memory Remark Software must wait until the OK_STOP_CLK bit in the DRAMHIBCTL register is set to 1 before reinitializing the memory controller register...

Page 204: ...ndary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes These codes can be executed on ROM 6 Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in the general purpose registers MISCREG 0 15 which retain values during Hibernate mode in the GIU or in external memory 7 Clear the DRAM_EN bit in the DRAMHIBCTL ...

Page 205: ...FFF TClock period burst refresh interval required by DRAM 6 Set 0x3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to maximum to prevent an interruption of a Suspend mode sequence 7 Set the SUSPEND bit in the DRAMHIBCTL register to 1 If the BstRefr bit of the MEMCFG_REG register in the memory controller to 1 the memory controller performs a burst refresh cycl...

Page 206: ...ery 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR auto refresh cycles for a specific time period i e 0x3FFF TClock period burst refresh interval required by DRAM 7 Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst refresh Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self refresh mode 8 Poll th...

Page 207: ...BCURFCNTREG register in the MBA Host Bridge Then execute CBR refresh cycles for a specific time period i e 0x3FFF TClock period burst refresh interval required by DRAM 8 Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used 10 6 8 Exiting Suspend mode SDRAM 1 Generate a wake up event from Suspend mode s...

Page 208: ...0 4 PMU Registers Physical address R W Register symbol Function 0x0B00 00A0 R W PMUINTREG PMU interrupt status register 0x0B00 00A2 R W PMUCNTREG PMU control register 0x0B00 00A8 R W PMUWAITREG PMU wait counter register 0x0B00 00AC R W PMUDIVREG PMU Div mode register 0x0B00 00B2 R W DRAMHIBCTL DRAM Hibernate mode control register ...

Page 209: ...ted 11 CF_INT CompactFlash interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted 10 DCDST DCD1 pin state 1 High level inactive 0 Low level active 9 RTCINTR ElapsedTime RTC alarm interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cle...

Page 210: ...after the CPU core is restarted 1 BATTINTR Battery low detection during normal operation Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted 0 POWERSWINTR Power Switch interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is rest...

Page 211: ...T 0 0 0 0 0 0 0 0 Other resets Note 0 0 0 0 0 0 0 Bit Name Function 15 to 8 Reserved 0 is returned when read 7 STANDBY Standby mode setting This setting is performed only for software and does not affect hardware in any way 1 Standby mode 0 Normal mode 6 Reserved Write 0 when write 0 is returned when read 5 Selfrfresh Self refresh status 1 Completed 0 Not completed 4 Suspend Suspend mode status al...

Page 212: ...ify that the HALTIMERRST bit is 0 before reset the HALTimer When this bit is 1 the HALTimer is not reset even if write 1 to this bit In this case write 0 to this bit first then write 1 after more than 6 RTC clock cycles This register is used to set CPU core shutdown and overall system operations management The HALTIMERRST bit must be reset within about four seconds after activation Resetting of th...

Page 213: ...eturned when read 13 to 0 WCOUNT 13 0 Activation wait time timer count value Activation wait time WCOUNT 13 0 x 1 32 768 ms Note Holds the value before reset This register is used to set the activation wait time when the CPU core is activated This register is set to 0x2C00 i e 343 75 ms activation wait time after RTC reset Therefore the 343 75 ms wait time is always inserted as an activation wait ...

Page 214: ...de mode 111 RFU 110 RFU 101 RFU 100 RFU 011 DIV3 mode 010 DIV2 mode 001 DIV1 mode 000 Default mode DIV2 Note Holds the value before reset This register is used to set CPU core s Div mode The Div mode setting determines the division rate of the TClock in relation to the pipeline clock PClock frequency Since the contents of this register are cleared to 0 during an RTC reset the Div mode setting alwa...

Page 215: ... 0 0 0 Undefined 0 0 0 0 Other resets 0 0 0 Undefined Note Note Note Note Bit Name Function 15 to 5 Reserved 0 is returned when read 4 Reserved An undefined value is returned when read 3 OK_STOP_CLK Ready to stop clocks 1 Ready DRAM is in self refresh mode 0 Not ready MEMC is busy to do burst refresh 2 STOP_CLK Clock supply for MEMC 1 Stop 0 Supply 1 SUSPEND Self refresh request This bit is for so...

Page 216: ... times 11 2 Register Set The RTC registers are listed below Table 11 1 RTC Registers Physical address R W Register symbol Function 0x0B00 00C0 R W ETIMELREG ElapsedTime L register 0x0B00 00C2 R W ETIMEMREG ElapsedTime M register 0x0B00 00C4 R W ETIMEHREG ElapsedTime H register 0x0B00 00C8 R W ECMPLREG ElapsedTime compare L register 0x0B00 00CA R W ECMPMREG ElapsedTime compare M register 0x0B00 00C...

Page 217: ...her resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 ETIME 15 0 ElapsedTime timer bits 15 to 0 Note Continues counting 2 ETIMEMREG 0x0B00 00C2 Bit 15 14 13 12 11 10 9 8 Name ETIME31 ETIME30 ETIME29 ETIME28 ETIME27 ETIME26 ETIME25 ETIME24 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name E...

Page 218: ...mer bits 47 to 32 Note Continues counting These registers indicate the ElapsedTime timer s value They count up by a 32 768 kHz clock cycle and when a match occurs with the ElapsedTime compare registers an alarm ElapsedTime interrupt occurs and the counting continues A write operation is valid once values have been written to all registers ETIMELREG ETIMEMREG and ETIMEHREG These registers have no b...

Page 219: ...Note Note Note Note Bit Name Function 15 to 0 ECMP 15 0 Value to be compared with ElapsedTime timer bits 15 to 0 Note Holds the value before reset 2 ECMPMREG 0x0B00 00CA Bit 15 14 13 12 11 10 9 8 Name ECMP31 ECMP30 ECMP29 ECMP28 ECMP27 ECMP26 ECMP25 ECMP24 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name ECMP23...

Page 220: ...R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 ECMP 47 32 Value to be compared with ElapsedTime timer bits 47 to 32 Note Holds the value before reset Use these registers to set the values to be compared with values in the ElapsedTime registers A write operation is valid once values have been written to all r...

Page 221: ...R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name RTCL1P7 RTCL1P6 RTCL1P5 RTCL1P4 RTCL1P3 RTCL1P2 RTCL1P1 RTCL1P0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 RTCL1P 15 0 Bits 15 to 0 for RTCLong1 timer count cycle Note Hold...

Page 222: ...e Bit Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 RTCL1P 23 16 Bits 23 to 16 for RTCLong1 timer count cycle Note Holds the value before reset Use these registers to set the RTCLong1 timer count cycle The RTCLong1 timer begins its countdown at the value written to these registers A write operation is valid once values have been written to both registers RTCL1LREG and RTCL1HREG Whe...

Page 223: ...C11 RTCL1C10 RTCL1C9 RTCL1C8 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name RTCL1C7 RTCL1C6 RTCL1C5 RTCL1C4 RTCL1C3 RTCL1C2 RTCL1C1 RTCL1C0 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 RTCL1C 15 0 RTCLong1 timer bits 15 to 0 Note Continues counting ...

Page 224: ...Note Bit Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 RTCL1C 23 16 RTCLong1 timer bits 23 to 16 Note Continues counting These registers indicate the RTCLong1 timer s values It counts down by a 32 768 kHz clock cycle and begins counting at the value set to the RTCLong1 registers An RTCLong1 interrupt occurs when the timer value reaches 0x00 0001 at which point the timer returns to ...

Page 225: ...R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name RTCL2P7 RTCL2P6 RTCL2P5 RTCL2P4 RTCL2P3 RTCL2P2 RTCL2P1 RTCL2P0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 RTCL2P 15 0 Bits 15 to 0 for RTCLong2 timer count cycle Note Hold...

Page 226: ...e Bit Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 RTCL2P 23 16 Bits 23 to 16 for RTCLong2 timer count cycle Note Holds the value before reset Use these registers to set the RTCLong2 timer count cycle The RTCLong2 timer begins its countdown at the value written to these registers A write operation is valid once values have been written to both registers RTCL2LREG and RTCL2HREG Whe...

Page 227: ...C11 RTCL2C10 RTCL2C9 RTCL2C8 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name RTCL2C7 RTCL2C6 RTCL2C5 RTCL2C4 RTCL2C3 RTCL2C2 RTCL2C1 RTCL2C0 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 RTCL2C 15 0 RTCLong2 timer bits 15 to 0 Note Continues counting ...

Page 228: ...Note Bit Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 RTCL2C 23 16 RTCLong2 timer bits 23 to 16 Note Continues counting These registers indicate the RTCLong2 timer s values It counts down by a 32 768 kHz clock cycle and begins counting at the value set to the RTCLong2 registers An RTCLong2 interrupt occurs when the timer value reaches 0x00 0001 at which point the timer returns to ...

Page 229: ...d Reserved RTCINTR2 RTCINTR1 RTCINTR0 R W R R R R R R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 Note Note Note Bit Name Function 15 to 3 Reserved 0 is returned when read 2 RTCINTR2 RTCLong2 interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal 1 RTCINTR1 RTCLong1 interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal 0 RTCINTR0 ElapsedTime interrupt reque...

Page 230: ... allows terminating runaway states that may occur due to software in earlier phase to minimize data loss 12 2 Register Set The DSU registers are listed below Table 12 1 DSU Registers Physical address R W Register symbol Function 0x0B00 00E0 R W DSUCNTREG DSU control register 0x0B00 00E2 R W DSUSETREG DSU cycle setting register 0x0B00 00E4 W DSUCLRREG DSU clear register 0x0B00 00E6 R W DSUTIMREG DS...

Page 231: ... R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved DSWEN R W R R R R R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 1 Reserved 0 is returned when read 0 DSWEN Deadman s Switch function enable 1 Enabled 0 Disabled This register is used to enable use of the Deadman s...

Page 232: ... RTCRST 0 0 0 0 0 0 0 1 Other resets 0 0 0 0 0 0 0 1 Bit Name Function 15 to 4 Reserved 0 is returned when read 3 to 0 DEDTIME 3 0 Deadman s Switch cycle setting 1111 15 seconds 1110 14 seconds 0010 2 seconds 0001 1 second 0000 Setting prohibited This register is used to set the cycle for Deadman s Switch function The Deadman s Switch cycle can be set in 1 second units in a range from 1 to 15 seco...

Page 233: ...d Reserved DSWCLR R W R R R R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 1 Reserved 0 is returned when read 0 DSWCLR Deadman s Switch timer clear 1 Clear stops timer 0 Timer counting The Deadman s Switch timer is cleared by setting the DSWCLR bit in this register to 1 The VR4181 automatically enters in a Cold Reset status if 1 is not written to this registe...

Page 234: ... 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved CRTTIME3 CRTTIME2 CRTTIME1 CRTTIME0 R W R R R R R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 4 Reserved 0 is returned when read 3 to 0 CRTTIME 3 0 Current Deadman s Switch timer value elapsed time 1111 15 seconds 1110 14 seconds 0010 2 seconds 0001 1 second 0000 Setting prohibited This re...

Page 235: ...2 Enable the DSU Register DSUCNTREG address 0x0B00 00E0 data 0x0001 3 Clear the timer within the time period specified in step 1 above Cancel the clearance of the timer to start another counting Register DSUCLRREG address 0x0B00 00E4 data 0x0001 timer clear Register DSUCLRREG address 0x0B00 00E4 data 0x0000 timer operation start For normal use repeat step 3 To obtain the current elapsed time read ...

Page 236: ... up inputs The assignment of interface signals to particular GPIO pins is shown in the following table Table 13 1 Alternate Functions of GPIO 15 0 Pins GPIO pin Alternate signal 1 Alternate signal 2 Definition GPIO15 FPD7 CD2 Color LCD data bit output or Card Detect 2 input GPIO14 FPD6 CD1 Color LCD data bit output or Card Detect 1 input GPIO13 FPD5 Color LCD data bit output GPIO12 FPD4 Color LCD ...

Page 237: ...tput GPIO29 DCD1 SIU1 DCD input GPIO28 CTS1 SIU1 CTS input GPIO27 RTS1 SIU1 RTS output GPIO26 TxD1 SIU1 transmit data output GPIO25 RxD1 SIU1 receive data input GPIO24 ROMCS2 ROM chip select for bank 2 GPIO23 ROMCS1 ROM chip select for bank 1 GPIO22 ROMCS0 ROM chip select for bank 0 GPIO21 RESET External ISA reset GPIO20 Note UBE M External ISA upper byte enable or LCD modulation output GPIO19 IOC...

Page 238: ...te mode these registers can be used by system software to save the state of selected registers located in the 2 5 V block prior to entering Hibernate mode Once the VR4181 has resumed from Hibernate mode system software can then restore the state of those 2 5 V registers from the general purpose registers The general purpose registers are located in the address range of 0x0B00 0330 to 0x0B00 034F 1...

Page 239: ... 1 based on the settings in the GPIO Mode registers and bit 15 LOOPBK1 of the GPSICTL register address 0x0B00 031A for additional information see 13 3 14 GPSICTL 0x0B00 031A When GPIO pins have been assigned to provide the serial interface channel 1 inputs RxD1 DTR1 RTS1 and DCD1 the GIU simply passes the signals driven on the GPIO pins to the corresponding serial interface channel 1 inputs Otherw...

Page 240: ... GIU drives inputs to the serial interface channel 2 based on the settings in the GPIO Mode registers and bit 7 LOOPBK2 of the GPSICTL register address 0x0B00 031A for additional information see 13 3 14 GPSICTL 0x0B00 031A When GPIO pins have been assigned to provide the serial interface channel 2 inputs DTR2 RTS2 and DCD2 the GIU simply passes the signals driven on the GPIO pins to the correspond...

Page 241: ...er pins are redefined to support the external LCD controller interface Table 13 9 External LCD Controller Interface Signals LCD pin External LCD controller interface signal Type SHCLK LCDCS Output LOCLK MEMCS16 Input VPLCD General purpose output VPGPIO1 Output VPBIAS General purpose output VPGPIO0 Output The LCDCS output is generated by the address decode logic in the GIU The address range can be ...

Page 242: ...one of the programmable chip selects has been defined as I O mapped and 16 bit data width the gpiocs16_l output is asserted while the I O cycle address is within the range specified for the programmable chip select When the IOCS16 GPIO19 pin has been configured as IOCS16 the gpiocs16_l output follows the state of the IOCS16 signal The gpmemcs16_l output is controlled by a programmable chip select ...

Page 243: ...requests input to the GPIO pin The interrupt status register GPINTSTAT allows software to determine the source of the GPIO interrupt request The functions of the enable mask polarity and type bits are shown in the following figure Figure 13 1 GPIO 15 0 Interrupt Request Detecting Logic Enable bit GPIO input Polarity bit Type bit Mask bit Other GPIO interrupt requests GPIOINTR MUX VDD Level trigger...

Page 244: ...rrupt type low register 0x0B00 0314 R W GPINTSTAT GPIO interrupt status register 0x0B00 0316 R W GPHIBSTH GPIO Hibernate pin status high register 0x0B00 0318 R W GPHIBSTL GPIO Hibernate pin status low register 0x0B00 031A R W GPSICTL GPIO serial interface control register 0x0B00 031C R W KEYEN Keyboard scan pin enable register 0x0B00 0320 R W PCS0STRA Programmable chip select 0 start address regis...

Page 245: ... MISCREG1 0x0B00 0334 R W MISCREG2 0x0B00 0336 R W MISCREG3 0x0B00 0338 R W MISCREG4 0x0B00 033A R W MISCREG5 0x0B00 033C R W MISCREG6 0x0B00 033E R W MISCREG7 0x0B00 0340 R W MISCREG8 0x0B00 0342 R W MISCREG9 0x0B00 0344 R W MISCREG10 0x0B00 0346 R W MISCREG11 0x0B00 0348 R W MISCREG12 0x0B00 034A R W MISCREG13 0x0B00 034C R W MISCREG14 0x0B00 034E R W MISCREG15 General purpose register ...

Page 246: ...O7 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU2 DTR2 output 13 12 GP6MD 1 0 These bits control direction and function of the GPIO6 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU2 RTS2 output 11 10 GP5MD 1 0 These bits control direction and function of the GPIO5 pin as follows 00 General purpose input 01 SIU2 DCD2 input 10 General...

Page 247: ...eral purpose input 01 CSI SCK input 10 General purpose output 11 RFU 3 2 GP1MD 1 0 These bits control direction and function of the GPIO1 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 CSI SO output 1 0 GP0MD 1 0 These bits control direction and function of the GPIO0 pin as follows 00 General purpose input 01 CSI SI input 10 General purpose output 11 RFU ...

Page 248: ...MD 1 0 These bits control direction and function of the GPIO14 pin as follows 00 General purpose input 01 CD1 input 10 General purpose output 11 Color LCD FPD6 output 11 10 GP13MD 1 0 These bits control direction and function of the GPIO13 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 Color LCD FPD5 output 9 8 GP12MD 1 0 These bits control direction and function of th...

Page 249: ...urpose input 01 CSI FRM input 10 General purpose output 11 SYSCLK output 3 2 GP9MD 1 0 These bits control direction and function of the GPIO9 pin as follows 00 General purpose input 01 SIU2 CTS2 input 10 General purpose output 11 RFU 1 0 GP8MD 1 0 These bits control direction and function of the GPIO8 pin as follows 00 General purpose input 01 SIU2 DSR2 input 10 General purpose output 11 RFU ...

Page 250: ...follows 00 General purpose input 01 RFU 10 General purpose output 11 ROMCS1 output 13 12 GP22MD 1 0 These bits control direction and function of the GPIO22 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 ROMCS0 output 11 10 GP21MD 1 0 These bits control direction and function of the GPIO21 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 RESET...

Page 251: ...eneral purpose input 01 IORDY input 10 General purpose output 11 RFU 3 2 GP17MD 1 0 These bits control direction and function of the GPIO17 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 IOWR output 1 0 GP16MD 1 0 These bits control direction and function of the GPIO16 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 IORD output ...

Page 252: ...the GPIO31 pin as follows 00 General purpose input 01 SIU1 DSR1 input 10 General purpose output 11 RFU 13 12 GP30MD 1 0 These bits control direction and function of the GPIO30 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU1 DTR1 output 11 10 GP29MD 1 0 These bits control direction and function of the GPIO29 pin as follows 00 General purpose input 01 SIU1 DCD1 input...

Page 253: ... purpose input 01 RFU 10 General purpose output 11 SIU1 TxD1 output 3 2 GP25MD 1 0 These bits control direction and function of the GPIO25 pin as follows 00 General purpose input 01 SIU1 RxD1 input 10 General purpose output 11 RFU 1 0 GP24MD 1 0 These bits control direction and function of the GPIO24 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 ROMCS2 output ...

Page 254: ...R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 GPDAT 31 16 General purpose data There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is configured as a general purpose input the value of the pin can be read from this register When the pin is defined as a general purpose output the va...

Page 255: ...R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 GPDAT 15 0 General purpose data There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is configured as a general purpose input the value of the pin can be read from this register When the pin is defined as a general purpose output the value w...

Page 256: ...R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 GIEN 15 0 GPIO interrupt enable There is a one to one correspondence between these bits and GPIO pins When one of the GPIO 15 0 pins is defined as a general purpose input the corresponding bit in this register enables interrupts for that pin as follows 0 Interrupt disabled 1 In...

Page 257: ...R W R W RTCRST 1 1 1 1 1 1 1 1 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 GIMSK 15 0 GPIO interrupt mask There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is defined as a general purpose input and interrupts is enabled on that pin the interrupt can be temporarily masked by setting the corresponding bit in this register as foll...

Page 258: ...gered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 13 12 I14TYP 1 0 These bits define the type of interrupt generated when the GPIO14 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 11 10 I13TYP 1 0 These bits define the type of inte...

Page 259: ...se input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 3 2 I9TYP 1 0 These bits define the type of interrupt generated when the GPIO9 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggere...

Page 260: ...d interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 13 12 I6TYP 1 0 These bits define the type of interrupt generated when the GPIO6 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 11 10 I5TYP 1 0 These bits define the type of interrupt g...

Page 261: ... input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 3 2 I1TYP 1 0 These bits define the type of interrupt generated when the GPIO1 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered ...

Page 262: ...tween these bits and GPIO pins When a GPIO pin is defined as a general purpose input these bits reflect the interrupt request status as follows 0 No Interrupt request pending 1 Interrupt request pending Note Holds the value before reset Interrupt request pending status is reflected regardless of the setting of the interrupt mask bits Therefore the status of an interrupt request can be returned as ...

Page 263: ...Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 GPHST 31 16 GPIO Hibernate pin state control There is a one to one correspondence between these bits and GPIO pins These bits determine the state of GPIO 31 16 pins during Hibernate mode as follows 0 Output pin is in high impedance Input pin is ignored during Hibernate mode 1 Output pin remains actively driven Input pin is monitored...

Page 264: ... W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15 to 0 GPHST 15 0 GPIO Hibernate pin state control There is a one to one correspondence between these bits and GPIO pins These bits determine the state of GPIO 15 0 pins during Hibernate mode as follows 0 Output pin is in high impedance Input pin is ignored during Hibernate mode 1 Output pin r...

Page 265: ...to the line status input signals as follows DTR1 output from serial interface drives the DSR1 input to serial interface RTS1 output from serial interface drives the CTS1 input to serial interface 14 to 12 Reserved 0 is returned when read 11 REGRXD1 RxD1 data When a GPIO pin has not been enabled to provide RxD1 the RxD1 input to the serial interface channel 1 is driven with the value of this bit 10...

Page 266: ...al interface RTS2 output from serial interface drives the CTS2 input to serial interface 6 to 3 Reserved 0 is returned when read 2 REGCTS2 CTS2 data When the LOOPBK2 bit is reset to 0 and a GPIO pin has not been enabled to provide CTS2 the CTS2 input to the serial interface channel 2 is driven with the value of this bit 1 REGDSR2 DSR2 data When the LOOPBK2 bit is reset to 0 and a GPIO pin has not ...

Page 267: ...he CompactFlash interface to be redefined to support the keyboard scan interface 0 CompactFlash interface enabled 1 Keyboard scan interface enabled 14 to 8 Reserved 0 is returned when read 7 CFHIBEN CompactFlash interface enable during Hibernate mode 0 Disable 1 Enable 6 to 0 Reserved 0 is returned when read Note Holds the value before reset The GIU only provides an internal output signal keysel w...

Page 268: ... chip select 0 start address These bits determine the starting address for the memory or I O chip select Note Holds the value before reset 13 3 17 PCS0STPA 0x0B00 0322 Bit 15 14 13 12 11 10 9 8 Name PCS0STPA 15 PCS0STPA 14 PCS0STPA 13 PCS0STPA 12 PCS0STPA 11 PCS0STPA 10 PCS0STPA 9 PCS0STPA 8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note ...

Page 269: ... 0 0 Other resets Note1 Note1 Note1 Note1 Note1 Note1 Note1 Note1 Bit Name Function 15 to 12 Reserved 0 is returned when read 11 to 0 PCS0HIA 27 16 Programmable chip select 0 high address A programmable chip select 0 will be generated when all of the following conditions have been met The system address bits A 15 0 are equal to or greater than PCS0STRA 15 0 and equal to or less than PCS0STPA 15 0 ...

Page 270: ... chip select 1 start address These bits determine the starting address for the memory or I O chip select Note Holds the value before reset 13 3 20 PCS1STPA 0x0B00 0328 Bit 15 14 13 12 11 10 9 8 Name PCS1STPA 15 PCS1STPA 14 PCS1STPA 13 PCS1STPA 12 PCS1STPA 11 PCS1STPA 10 PCS1STPA 9 PCS1STPA 8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note ...

Page 271: ... 0 0 Other resets Note1 Note1 Note1 Note1 Note1 Note1 Note1 Note1 Bit Name Function 15 to 12 Reserved 0 is returned when read 11 to 0 PCS1HIA 27 16 Programmable chip select 1 high address A programmable chip select 1 will be generated when all of the following conditions have been met The system address bits A 15 0 are equal to or greater than PCS1STRA 15 0 and equal to or less than PCS1STPA 15 0 ...

Page 272: ... generated unless MEMCS16 or IOCS16 is asserted 1 Defined as a 16 bit device During accesses to the address range specified for PCS1 16 bit cycles will be generated 5 4 PCS1MD 1 0 Programmable chip select 1 mode 00 Disabled 01 Qualified also with I O or memory read strobe 10 Qualified also with I O or memory write strobe 11 Based on address decode only 3 PCS0MIOB Programmable chip select 0 target ...

Page 273: ... 1 Controlled by external LCD controller SHCLK LCDCS LOCLK MEMCS16 VPLCD driven by the GPVPLCD bit of this register VPBIAS driven by the GPVPBIAS bit of this register 6 to 4 Reserved 0 is returned when read 3 2 LCDCS 1 0 External LCD controller frame buffer address select These bits determine the address range that will cause the LCDCS signal to be asserted 00 0x130A 0000 to 0x130A FFFF 64KB PC AT...

Page 274: ...0x0B00 033E MISCREG15 0x0B00 034E Bit 15 14 13 12 11 10 9 8 Name MISCnD15 MISCnD14 MISCnD13 MISCnD12 MISCnD11 MISCnD10 MISCnD9 MISCnD8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit 7 6 5 4 3 2 1 0 Name MISCnD7 MISCnD6 MISCnD5 MISCnD4 MISCnD3 MISCnD2 MISCnD1 MISCnD0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other...

Page 275: ...an be directly connected to touch panel with four pin resistance layers on chip touch panel driver Interface for on chip A D converter Voltage detection at three general purpose A D ports and one audio input port Operation of A D converter based on various settings and control of voltage applied to touch panel Sampling of X coordinate and Y coordinate data Variable coordinate data sampling interva...

Page 276: ... resistance between the two edges of the resistance layers is about 1 kΩ When a voltage is applied to both edges of the Y axis resistance layer the voltage VY1 and VY2 in the figure below is measures at the X axis resistance layer s pins to determine the Y coordinate Similarly when a voltage is applied to both edges of the X axis resistance layer the voltage VX1 and VX2 in the figure below is meas...

Page 277: ...in 3 V a Y coordinate detection b X coordinate detection TPY0 pin 0 V TPY0 pin TPX1 pin 3 V TPX0 pin 0 V VX2 TPY0 pin TPX0 pin VY2 TPY1 pin 0 V TPY0 pin 3 V Figure 14 3 Internal Block Diagram of PIU VR4181 Scan sequencer Touch panel interface controller A D converter General purpose A D ports Audio input port PIU PIU registers Internal bus controller Internal bus Touch panel ...

Page 278: ...he scan sequencer is used for PIU state management Touch panel interface controller The touch panel interface controller is used to control the touch panel 14 2 Scan Sequencer State Transition Figure 14 4 Scan Sequencer State Transition Diagram Disable Reset 1 PIUPWR 1 PIUSEQEN 1 ADPSSTART 1 PIUSEQEN 1 PADATSTART 1 Release PADATSTOP 1 PIUPWR 0 ADPSSTART 1 timeout PIUSEQEN 1 PADSCANSTART 1 PIUSEQEN...

Page 279: ... TPX 1 0 TPY 1 0 and the selection of an input port TPX 1 0 TPY 1 0 AUDIOIN ADIN 2 0 to the A D converter Use PIUCMDREG register to make the touch panel pin setting and to select the input port WaitPenTouch state This is a standby state in which the PIU waits for a touch panel s touch status When the PIU detects a touch panel s touch status a touch panel contact status change interrupt request occ...

Page 280: ... register 0x0B00 02A6 R W PIUPB03REG PIU page 0 buffer 3 register 0x0B00 02A8 R W PIUPB10REG PIU page 1 buffer 0 register 0x0B00 02AA R W PIUPB11REG PIU page 1 buffer 1 register 0x0B00 02AC R W PIUPB12REG PIU page 1 buffer 2 register 0x0B00 02AE R W PIUPB13REG PIU page 1 buffer 3 register 0x0B00 02B0 R W PIUAB0REG PIU A D scan buffer 0 register 0x0B00 02B2 R W PIUAB1REG PIU A D scan buffer 1 regis...

Page 281: ...0 0 0 Bit Name Function 15 14 Reserved 0 is returned when read 13 PENSTC Touch release status when touch panel contact state changes 1 Touch 0 Release 12 to 10 PADSTATE 2 0 Scan sequencer status 111 CMDScan 110 Interval 101 DataScan 100 WaitPenTouch 011 RFU 010 ADPScan 001 Standby 000 Disable 9 PADATSTOP Sequencer auto stop setting during touch panel release status 1 Auto stop after sampling data ...

Page 282: ...reset Once the PADRST bit is set to 1 it is automatically cleared to 0 after four TClock cycles 1 Reset 0 Do not reset This register is used to make various settings for the PIU The PENSTC bit indicates the touch panel contact status at the time when the PENCHGINTR bit of the PIUINTREG register is set to 1 This bit s state remains as it is until the PENCHGINTR bit is cleared to 0 Also when the PEN...

Page 283: ...Scan PADRST Note1 0 1 Disable Disable Disable PIUPWR 0 1 1 0 PIUSEQEN 0 1 1 0 Standby Standby Standby PADATSTART 0 1 1 0 PADATSTOP 0 1 1 0 PADSCANSTART 0 1 1 0 PADSCANSTOP 0 1 Standby Note4 Standby Note4 Standby Note4 1 0 Notes 1 After 1 is written the bit is automatically cleared to 0 four TClock cycles later 2 State transition occurs during touch status 3 State transition occurs when the PIUSEQE...

Page 284: ... written 1 Occurred 0 Not occurred 5 PADADPINTR PIU A D port scan interrupt request This interrupt request occurs when a set of valid data is obtained during an A D port scan Cleared to 0 when 1 is written 1 Occurred 0 Not occurred 4 PADPAGE1INTR PIU data buffer page 1 interrupt request This interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer Cleared to 0 w...

Page 285: ...y be set to 1 on returning from the Hibernate mode Therefore set each bit of the PIUINTREG register to 1 to clear an interrupt request immediately after a restore from the Hibernate mode 14 3 3 PIUSIVLREG 0x0B00 0126 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved SCAN INTVAL10 SCAN INTVAL9 SCAN INTVAL8 R W R R R R R R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0...

Page 286: ...rved Reserved R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved STABLE5 STABLE4 STABLE3 STABLE2 STABLE1 STABLE0 R W R R R W R W R W R W R W R W RTCRST 0 0 0 0 0 1 1 1 Other resets 0 0 0 0 0 1 1 1 Bit Name Function 15 to 6 Reserved 0 is returned when read 5 to 0 STABLE 5 0 Touch panel voltage stabilization wait time DataScan CMDScan s...

Page 287: ...ime STABLE 5 0 of PIUSTBLREG enable during command scan 1 Wait for panel voltage stabilization time 0 Ignore panel voltage stabilization time wait time 0 11 10 TPYEN 1 0 TPY port input output switching during command scan 11 TPY1 output TPY0 output 10 TPY1 output TPY0 input 01 TPY1 input TPY0 output 00 TPY1 input TPY0 input 9 8 TPXEN 1 0 TPX port input output switching during command scan 11 TPX1 ...

Page 288: ...1000 RFU 0111 AUDIOIN port 0110 ADIN2 port 0101 ADIN1 port 0100 ADIN0 port 0011 TPY1 port 0010 TPY0 port 0001 TPX1 port 0000 TPX0 port This register switches input output and sets output level for each port during a command scanning operation The setting of the TPYD bits are invalid when a port is set as input in the TPYEN bits The setting of the TPXD bits are invalid when a port is set as input i...

Page 289: ...0 general purpose as A D port and AUDIOIN as audio input port 0 ADPSSTART ADPScan start 1 Start ADPScan 0 Do not perform ADPScan This register is used for ADPScan setting The ADPScan begins when the ADPSSTART bit is set After the ADPScan is completed the sequencer returns to the state when ADPScan was started and the ADPSSTART bit is cleared to 0 automatically If the ADPScan is not completed withi...

Page 290: ...manipulation Scan sequencer s state Interval ADPScan CMDScan ADPSSTART Note1 0 1 ADPScan Note2 ADPScan Note2 1 0 TPPSCAN 0 1 1 0 Notes 1 Immediately after a transition to the ADPScan state the bit is automatically cleared to 0 2 After ADPScan is completed the sequencer returns to the state in which the scan has started Remark The bit change is retained but there is no state transition Setting proh...

Page 291: ... R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 8 Reserved 0 is returned when read 7 ADINM3 Audio input port mask 1 Mask 0 Normal 6 to 4 ADINM 2 0 General purpose A D port mask 1 Mask 0 Normal 3 2 TPYM 1 0 Touch panel A D port TPY mask 1 Mask 0 Normal 1 0 TPXM 1 0 Touch panel A D port TPX mask 1 Mask 0 Normal This register is used to set masking each A D po...

Page 292: ...0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name CHECK INTVAL7 CHECK INTVAL6 CHECK INTVAL5 CHECK INTVAL4 CHECK INTVAL3 CHECK INTVAL2 CHECK INTVAL1 CHECK INTVAL0 R W R R R R R R R R RTCRST 1 0 1 0 0 0 0 0 Other resets 1 0 1 0 0 0 0 0 Bit Name Function 15 to 11 Reserved 0 is returned when read 10 to 0 CHECKINTVAL 10 0 Interval count value This register indicates the value of an internal reg...

Page 293: ...id 0 Invalid 14 to 10 Reserved 0 is returned when read 9 to 0 PADDATA 9 0 A D converter s sampling data These registers are used to store coordinate data or touch pressure data There are four coordinate data buffers and one touch pressure data buffer each of which holds two pages of coordinate data or pressure data and the addresses register addresses where the coordinate data or the pressure data...

Page 294: ... data in buffer 1 Valid 0 Invalid 14 to 10 Reserved 0 is returned when read 9 to 0 PADDATA 9 0 A D converter s sampling data These registers are used to store sampling data of the general purpose A D port and audio input port or command scan data There are four data buffers and the addresses register address where the data is stored are fixed The VALID bit which indicates whether the data is valid...

Page 295: ... the PIU registers Table 14 7 Mask Clear During Scan Sequencer Operation Setting Unit Register Bit Value Interrupt mask clear ICU MSYSINT1REG MPIUINTR 1 ICU MPIUINTREG bits 6 to 0 0x7F Clock mask clear MBA Host Bridge CMUCLKMSK MSKPIUPCLK 1 1 Transition flow for voltage detection at A D general purpose ports and audio input port Standby WaitPenTouch or Interval state 1 PIUAMSKREG Mask setting for ...

Page 296: ...Touch or Interval state 1 PIUCNTREG PIUSEQEN 0 Standby state 2 PIUCNTREG PIUPWR 1 Disable state 5 Transition flow when returning from Suspend mode Disable state 1 PIUCNTREG PIUPWR 1 Standby state 2 PIUCNTREG PIUMODE 1 0 00 PADATSTART 1 PADATSTOP 1 3 PIUCNTREG PIUSEQEN 1 WaitPenTouch state Touch detected DataScan state 6 Transition flow for command scan Disable state 1 PIUCNTREG PIUPWR 1 Standby st...

Page 297: ...port ADPScan 00 00 I Voltage detection at audio input port ADPScan 00 00 I Touch pressure detection Z DataScan HH d TPY1 L TPY0 H TPX0 samp X DataScan I LH TPY1 H TPY0 L TPX0 samp X DataScan I HL TPX1 L TPX0 H TPY0 samp Y DataScan LH I TPX1 H TPX0 L TPY0 samp Y DataScan HL I Note The states of pins are not guaranteed if the PADSTATE 2 0 immediately before the CPU s SUSPEND or HIBERNATE instruction...

Page 298: ...Y Release detected Note TPY 1 0 TPX 1 0 PADSCANTYPE 1 Touch detected Note X Release detected Note X Y X Z Y Y X Note Determined according to the status of the TPY1 signal as follows High level touched Low level released 14 6 2 A D port scan timing During an A D port scan the four ports of A D converter s input channel are sequentially scanned and the scanned data are stored in the data buffers ded...

Page 299: ...requently implement a countermeasure that temporarily prohibits the AIU s use of the A D converter Response After clearing the data lost interrupt request by setting the PADDLOSTINTR bit to 1 set the PADATSTART bit or PADSCANSTART bit of the PIUCNTREG register to restart the coordinate detection operation Once the data lost interrupt request is cleared the page in which the loss occurred becomes i...

Page 300: ...the three interrupt requests by writing 1 to the PADDLOSTINTR PADPAGE1INTR and PADPAGE0INTR bits in the PIUINTREG register After clearing these interrupt requests set the PADATSTART or PADSCANSTART bit of the PIUCNTREG register to restart the coordinate detection operation 4 When the next data transfer starts while there is valid data in the ADPScan buffer Cause This condition is caused when valid...

Page 301: ...alue converted by the internal A D converter Holding the digital value to be converted by the internal D A converter Separating data being converted by the A D or D A converter and transfer data by using double buffers Linking the update of the double buffers and the generation of DMA transfer requests with the data conversion rate Caution No clocks are supplied to the AIU A D converter and D A co...

Page 302: ...ontrol register 0x0B00 0170 R W MIDATREG Microphone input data register 0x0B00 0172 R W MCNTREG Microphone input control register 0x0B00 0178 R W DVALIDREG Data valid indication register 0x0B00 017A R W SEQREG Sequencer enable register 0x0B00 017C R W INTREG Interrupt register 0x0B00 017E R W MCNVC_END Microphone sample rate control register State of interrupt requests caused by AIU is indicated a...

Page 303: ...DMA1 SDMA0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 SDMA 9 0 Speaker output DMA data This register is used to store 10 bit DMA data for speaker output When SODATREG register is empty the data is transferred to the SODATREG register Write is used for debugging and is enabled when the AI...

Page 304: ...RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 MDMA 9 0 Microphone input DMA data This register is used prior to DMA transfer to store 10 bit data that has been converted by the A D converter and stored in the MIDATREG register Write is used for debugging and is enabled when the AIUMEN bit of the SEQREG register is set to 1 Th...

Page 305: ...REF5 DAVREF4 DAVREF3 DAVREF2 DAVREF1 DAVREF0 R W R W R W R W R W R W R W R W R W RTCRST 0 1 1 1 1 1 0 1 Other resets 0 1 1 1 1 1 0 1 Bit Name Function 15 to 0 DAVREF 15 0 D A converter Vref setup time This register is used to select a Vref setup time for the D A converter The following expression is used to calculate the value set to this register DAVREF 15 0 5 µs PCLK frequency For example if the...

Page 306: ...T2 SODAT1 SODAT0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 SODAT 9 0 Speaker output data This register is used to store 10 bit DMA data for speaker output Data is received from the SDMADATREG register and is sent to the D A converter Write is used for debugging and is enabled when the A...

Page 307: ...urned when read 3 SSTATE Indicates speaker operation state 1 Operating 0 Stopped 2 Reserved 0 is returned when read 1 SSTOPEN Speaker output DMA transfer page boundary interrupt 1 Stop DMA request at 1 page boundary 0 Stop DMA request at 2 page boundary 0 Reserved 0 is returned when read This register is used to control the AIU s speaker block The DAENAIU bit controls the connection of VDD_AD and ...

Page 308: ...R W R W RTCRST 1 1 0 1 1 1 0 0 Other resets 1 1 0 1 1 1 0 0 Bit Name Function 15 to 0 SCNVC 15 0 Speaker sample rate control This register is used to select a conversion rate for the D A converter The following expression is used to calculate the value set to this register SCNVC 15 0 PCLK frequency sample rate For example if the desired conversion rate is 8 ksps and internal peripheral clock PCLK ...

Page 309: ...W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 MIDAT 9 0 Microphone input data This register is used to store 10 bit speaker input data that has been converted by the A D converter Data is sent to the MDMADATREG register and is received from the A D converter Write is used for debugging and is...

Page 310: ...ting 0 Stopped 2 Reserved 0 is returned when read 1 MSTOPEN Microphone input DMA transfer page boundary interrupt 1 Stop DMA request at 1 page boundary 0 Stop DMA request at 2 page boundary 0 ADREQAIU Request for use of A D converter 1 Requesting 0 No request This register is used to control the AIU s microphone block The ADENAIU bit controls the connection of VDD_AD and Vref input to ladder type ...

Page 311: ...s whether valid data has been stored in SDMADATREG 1 Valid data exists 0 No valid data 1 MIDATV This indicates whether valid data has been stored in MIDATREG 1 Valid data exists 0 No valid data 0 MDMAV This indicates whether valid data has been stored in MDMADATREG 1 Valid data exists 0 No valid data This register indicates whether valid data has been stored in the SODATREG SDMADATREG MIDATREG or ...

Page 312: ...ame Reserved Reserved Reserved AIUMEN Reserved Reserved Reserved AIUSEN R W R R R R W R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 AIURST AIU reset via software 1 Reset 0 Normal 14 to 5 Reserved 0 is returned when read 4 AIUMEN Microphone block operation and DMA enable 1 Enable 0 Disable 3 to 1 Reserved 0 is returned when read 0 AIUSEN Speaker block operation ...

Page 313: ...mpletion interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal 7 to 2 Reserved 0 is returned when read 1 SIDLEINTR Speaker idle interrupt request mute Cleared to 0 when 1 is written 1 Occurred 0 Normal 0 Reserved 0 is returned when read This register indicates occurrence of various interrupt request of the AIU When data is received from the A D converter the MIDLEINTR bit is set if ...

Page 314: ...RTCRST 1 1 0 1 1 1 0 0 Other resets 1 1 0 1 1 1 0 0 Bit Name Function 15 to 0 MCNVC 15 0 Microphone sample rate control This register is used to select a conversion rate for the A D converter The following expression is used to calculate the value set to this register MCNVC 15 0 PCLK frequency sample rate For example if the desired conversion rate is 11 025 ksps and internal peripheral clock PCLK ...

Page 315: ... when speaker power is set to ON 6 Set speaker power ON via GPIO 7 Enable speaker operation 0x0B00 017A AIUSEN 1 DMA request Receive acknowledge and DMA data from DMA 0x0B00 0178 SDMAV SODATV 1 Output 10 bit data 0x0B00 0166 SODAT 9 0 to D A converter SODATV 0 SDMAV 1 Send SDMADATREG data to SODATREG SODATV 1 SDMAV 0 Output DMA request and store the data after the next into SDMADATREG SODATV 1 SDM...

Page 316: ...t A D request to A D converter Acknowledge and 10 bit conversion data are returned from A D converter Store data in MIDATREG 0x0B00 0178 MDMAV 0 MIDATV 1 Transfer data from MIDATREG to MDMADATREG MDMAV 1 MIDATV 0 MSTINTR 1 and an interrupt request receive complete occurs Issue DMA request and store MDMADATREG data to memory MDMAV 0 MIDATV 0 Issue an A D request once per conversion timing interval ...

Page 317: ...he SCANIN lines are pulled to VDD by external 4 7 kΩ resistors When any key in the matrix is pressed at least one SCANIN input is driven as low and signals a key press event to the KIU Once the key press event has been detected the KIU may be programmed to generate a key down interrupt request and to begin scanning the keyboard automatically or to wait until software enables the scan operation Key...

Page 318: ...oard scan mode Auto Scan mode Automatic Scan mode is enabled through the ASTART and ASTOP bits of the KIUSCANREP register When the ASTART bit is set to 1 keyboard scanning starts automatically following a key down interrupt request When the ASTOP bit is set to 1 keyboard scanning stops automatically after no valid keyboard data i e all SCANIN lines are high level has been read for the number of sc...

Page 319: ...one of the SCANOUT 7 0 pins the KIU will wait for the time set in the T1CNT 4 0 bits before reading returned data to the SCANIN 7 0 pins Actually the SCANOUT pins will be driven as low for T1CNT 4 0 1 32 768 kHz clock cycles The T3CNT 4 0 bits specify the delay from driving one SCANOUT pin as high impedance to driving the next SCANOUT pin as low and is also expressed in 32 768 kHz clock cycles Whe...

Page 320: ...t request KDATLOST bit signals that a data from the SCANIN line written to the key data register corresponding to the SCANOUT0 pin before the previous data value is read by the CPU core This interrupt source can be masked through the MSKKDATLOST bit of the MKIUINTREG register The key data ready interrupt request KDATRDY bit signals one complete scan operation has been completed This interrupt requ...

Page 321: ... 0x0B00 018C R KIUDAT6 Scan line 6 keyboard data register 0x0B00 018E R KIUDAT7 Scan line 7 keyboard data register 0x0B00 0190 R W KIUSCANREP Scan control register 0x0B00 0192 R KIUSCANS Scan status register 0x0B00 0194 R W KIUWKS Key scan stable time register 0x0B00 0196 R W KIUWKI Key scan interval time register 0x0B00 0198 R W KIUINT Interrupt register State of interrupt requests caused by KIU ...

Page 322: ... 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name RETDAT7 RETDAT6 RETDAT5 RETDAT4 RETDAT3 RETDAT2 RETDAT1 RETDAT0 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 8 Reserved 0 is returned when read 7 to 0 RETDAT 7 0 Scan data 1 Key is released 0 Key is pressed These registers reflect the state of the returned signals for the selected SCAN...

Page 323: ...P 5 0 Scan sequencer stop count These bits select the number of scan operation performed after all keys have been released 0xFF is loaded to KIUDAT registers 111111 63 times 000001 1 time 000000 64 times 3 MSTOP Scan stop manual mode This bit is sampled at the end of each scan operation and causes the scan sequencer to stop scanning when set to 1 1 Stop 0 Operate 2 MSTART Manual scan start manual ...

Page 324: ... R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved SSTAT1 SSTAT0 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 2 Reserved 0 is returned when read 1 0 SSTAT 1 0 Scan sequencer status 11 During scan interval WINTVL 10 Scanning T1CNT or T3CNT 01 Waiting for key pr...

Page 325: ...0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 Reserved 0 is returned when read 14 to 10 T3CNT 4 0 Scan idle time These bit determine the wait time the scan sequencer waits following a deassertion of one SCANOUT pin before an assertion of the next SCANOUT pin 11111 960 µs T3CNT 4 0 1 x 30 µs 00001 60 µs 00000 Setting prohibited 9 to 5 Reserved 0 is returned when read 4 to 0 T1CNT 4 0 Scan dat...

Page 326: ... 6 5 4 3 2 1 0 Name WINTVL7 WINTVL6 WINTVL5 WINTVL4 WINTVL3 WINTVL2 WINTVL1 WINTVL0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 10 Reserved 0 is returned when read 9 to 0 WINTVL 9 0 Scan interval time These bits determine the time the scan sequencer waits following completion of one scan operation before starting the next scan ope...

Page 327: ...eserved 0 is returned when read 2 KDATLOST Key data lost interrupt request This interrupt request occurs if the KIUDAT0 register is updated with the next key data prior to being read by the CPU core 1 Occurred 0 Not occurred This bit is cleared by writing 1 1 KDATRDY Key data ready interrupt request This interrupt request occurs when a set of scanning is completed and all the KIUDAT registers are ...

Page 328: ...bit of the KEYEN register 17 2 Register Set Summary This section provides details of the ECU registers Two of the ECU registers are located in the I O addressing space These registers as well as the Interrupt and Configuration registers are shown in the following table Table 17 1 ECU Control Registers Physical address R W Register symbol Function 0x0B00 08E0 R W ECUINDX Index register I O space 0x...

Page 329: ... stop address 1 low byte register 0x000F R W IOSHB1REG I O stop address 1 high byte register 0x0010 R W SYSMEMSL0REG System memory 0 mapping start address low byte register 0x0011 R W MEMWID0_REG System memory 0 mapping start address high byte register 0x0012 R W SYSMEMEL0REG System memory 0 mapping stop address low byte register 0x0013 R W MEMSEL0_REG System memory 0 mapping stop address high byt...

Page 330: ... R W MEMWID3_REG System memory 3 mapping start address high byte register 0x002A R W SYSMEMEL3REG System memory 3 mapping stop address low byte register 0x002B R W MEMSEL3_REG System memory 3 mapping stop address high byte register 0x002C R W MEMOFFL3REG Card memory 3 offset address low byte register 0x002D R W MEMOFFH3REG Card memory 3 offset address high byte register 0x002F R W VOLTSELREG Card ...

Page 331: ... Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 14 IRQ 15 14 Status of interrupt request 15 and 14 internal 0 Invalid 1 Valid 13 Reserved 0 is returned when read 12 to 9 IRQ 12 9 Status of interrupt request 12 11 10 and 9 internal 0 Invalid 1 Valid 8 Reserved 0 is returned when read 7 IRQ7 Status of interrupt request 7 internal 0 Invalid 1 Valid 6 Reserved 0 is returned when read 5 to 3 IRQ 5 3 Status...

Page 332: ... W R R R Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 14 IMSK0 15 14 Mask for interrupt request 15 and 14 internal 0 Unmask 1 Mask 13 Reserved 0 is returned when read 12 to 9 IMSK0 12 9 Mask for interrupt request 12 11 10 and 9 internal 0 Unmask 1 Mask 8 Reserved 0 is returned when read 7 IMSK07 Mask for interrupt request 7 internal 0 Unmask 1 Mask 6 Reserved 0 is returned when read 5 to 3 IMSK0 5 3...

Page 333: ...ll IRQ signals are ORed together to generate ecuint after ANDed with IMSK0n bits in the INTMSKREG register n 0 to 15 17 3 3 CFG_REG_1 0x0B00 08FE Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved WSE R W R R R R R R R...

Page 334: ...4 3 2 1 0 Name IFTYP1 IFTYP0 Reserved Reserved REV3 REV2 REV1 REV0 R W R R R R R R R R Reset 1 0 0 0 0 0 1 1 Bit Name Function 7 6 IFTYP 1 0 PCSC interface type These bits indicate 10 to reflect that both memory and I O cards are supported 5 4 Reserved 0 is returned when read 3 to 0 REV 3 0 Revision level 0011 is always displayed ...

Page 335: ...t indicates the current status of WP CF_IOIS16 signal from a CompactFlash card 0 Off 1 On 3 2 CD 2 1 Complement of the values of CD1 and CD2 Note 11 Active low level 00 Inactive high level Values other than above are not displayed 1 Reserved 0 is returned when read 0 BVD1 This bit indicates the current status of STSCHG CF_STSCHG signal from a CompactFlash card Note The card detect pins CD1 and CD2...

Page 336: ...his bit should not be set until this register has been written to set the CompactFlash card power enable 6 Reserved 0 is returned when read 5 Reserved 1 is returned when read 4 PWREN Card power enable 0 Disabled Vcc is 0 V 1 Enabled Voltage selected in the VOLTSELREG register 0x2F is applied The power to the socked is turned on when a card is inserted and off when removed Caution The VR4181 suppor...

Page 337: ...ter if this signal is configures as a source for the card status change interrupt 1 Used as the RI For memory PC Cards this bit has no function 6 CRDRST Card reset This bit is for a software reset to the PC Card to which the status of the CF_RESET signal is set 0 Active The CF_RESET signal will be active until this bit is set to 1 1 Inactive 5 CRDTYP Card type 0 Memory card 1 I O card 4 Reserved 0...

Page 338: ...he system software then has to read the status change register in the I O card to determine the cause of STSCHG Caution CompactFlash cards do not support the BVD battery status detection signal so that the BVD2 SPKR signal of the ECU is internally fixed to low level This register indicates the source of the card status change interrupt request Each source can be enabled to generate this interrupt ...

Page 339: ...d 1111 IRQ15 is used 3 CD_EN Card detect enable Enables a card status change interrupt request when a change has been detected on the CD1 or CD2 signals 0 Disable 1 Enable 2 RDY_EN Ready enable Enables a card status change interrupt request when a transition has been detected on the CF_BUSY signal 0 Disable 1 Enable 1 Reserved 0 is returned when read 0 BDEAD_EN Battery not usable or status change ...

Page 340: ...m the system bus directly to the card Caution The start and stop address register pairs must be set to values for the window to be used before setting these bits to 1 5 Reserved 0 is returned when read 4 to 0 MWEN 4 0 Memory window enables Generates the card enable signals to the card when a memory access occurs within the corresponding memory address window 0 Does not generate 1 Generates When th...

Page 341: ... 1 wait state 5 IO1_CS16MD I O window 1 IOCS16 source 0 Value of the IO1DSZ bit 1 CF_IOIS16 signal from the card 4 IO1DSZ I O window 1 access data size 0 8 bits 1 16 bits This bit has no function when the IO1_CS16MD bit is set to 1 3 IO0WT I O window 0 wait addition in 16 bit accesses 0 Without additional wait state 1 Adds 1 wait state 2 W0_IOWS I O window 0 wait addition in 8 bit accesses 0 No ad...

Page 342: ...mum 1 byte can be specified for the I O address window 17 4 10 IOADSHBnREG Index 0x09 0x0D Remark n 0 1 IOADSHB0REG 0x09 for Window 0 IOADSHB1REG 0x0D for Window 1 Bit 7 6 5 4 3 2 1 0 Name STARTA15 STARTA14 STARTA13 STARTA12 STARTA11 STARTA10 STARTA9 STARTA8 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 to 0 STARTA 15 8 I O window start address bits 15 to 8 High ord...

Page 343: ... of an I O address window 17 4 12 IOSHBnREG Index 0x0B 0x0F Remark n 0 1 IOSHB0REG 0x0B for Window 0 IOSHB1REG 0x0F for Window 1 Bit 7 6 5 4 3 2 1 0 Name STOPA15 STOPA14 STOPA13 STOPA12 STOPA11 STOPA10 STOPA9 STOPA8 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 to 0 STOPA 15 8 I O window stop address bits 15 to 8 High order address bits used to determine the stop ad...

Page 344: ...memory address window 17 4 14 MEMWIDn_REG Index 0x11 0x19 0x21 0x29 0x31 Remark n 0 to 4 MEMWID0_REG 0x11 for Window 0 MEMWID3_REG 0x29 for Window 3 MEMWID1_REG 0x19 for Window 1 MEMWID4_REG 0x31 for Window 4 MEMWID2_REG 0x21 for Window 2 Bit 7 6 5 4 3 2 1 0 Name DWIDTH ZWSEN MWSTART A25 MWSTART A24 MWSTART A23 MWSTART A22 MWSTART A21 MWSTART A20 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0...

Page 345: ...etermine the stop address of a memory address window 17 4 16 MEMSELn_REG Index 0x13 0x1B 0x23 0x2B 0x33 Remark n 0 to 4 MEMSEL0_REG 0x13 for Window 0 MEMSEL3_REG 0x2B for Window 3 MEMSEL1_REG 0x1B for Window 1 MEMSEL4_REG 0x33 for Window 4 MEMSEL2_REG 0x23 for Window 2 Bit 7 6 5 4 3 2 1 0 Name M16W1 M16W0 MWSTOPA 25 MWSTOPA 24 MWSTOPA 23 MWSTOPA 22 MWSTOPA 21 MWSTOPA 20 R W R W R W R W R W R W R W...

Page 346: ...4181 17 4 18 MEMOFFHnREG Index 0x15 0x1D 0x25 0x2D 0x35 Remark n 0 to 4 MEMOFFH0REG 0x15 for Window 0 MEMOFFH3REG 0x2D for Window 3 MEMOFFH1REG 0x1D for Window 1 MEMOFFH4REG 0x35 for Window 4 MEMOFFH2REG 0x25 for Window 2 Bit 7 6 5 4 3 2 1 0 Name WP REG OFFSETA 25 OFFSETA 24 OFFSETA 23 OFFSETA 22 OFFSETA 21 OFFSETA 20 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 WP...

Page 347: ...o be 16 bit in the DWIDTH bit of the MEMWIDn_REG register 0 Delayed 1 Not delayed The functionality and acknowledgment of this software interrupt request operate in the same way as those of the hardware generated interrupt requests The functionality and acknowledgement of the hardware card detect or card status change interrupt request are not affected by the setting of the SWCDINT bit If card det...

Page 348: ...nt 0 Reading of the CDSTCHGREG register Each bit of the register is cleared after read 1 Writing 1 to the CDSTCHGREG register Each bit of the register is cleared after write of 1 1 0 Reserved 0 is returned when read 17 4 21 VOLTSENREG Index 0x1F Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved VS2 VS1 R W R R R R R R R R Reset 0 0 0 0 0 0 1 0 Bit Name Function 7 to 2 ...

Page 349: ... R R W R W Reset 0 0 0 0 0 0 1 0 Bit Name Function 7 to 2 Reserved 0 is returned when read 1 0 VCCEN 1 0 Card connection status 01 3 3 V card connected 10 No card connected Caution Do not perform any write to this bit If the PWREN bit of the PWRRSETDRV register is set to 1 when the VCCEN 1 0 bits are 01 the CF_VCCEN signal becomes active Remark The VR4181 supports cards with the card voltage of 3 ...

Page 350: ...mum memory window size is 4 KB Accordingly when using CompactFlash with the VR4181 the card s entire memory space is mapped to a single memory window Mapping starts from the LSB The remaining part of the memory window becomes a mirror area occupying the lower 2 KB Figure 17 2 Mapping of CompactFlash Memory Space 0x13FF FFFF 0x1ppp p000 0x1qqq q000 0x0000 0000 0x1sss s000 0x1rrr r000 VR4181 ISA mem...

Page 351: ...ctFlash card do not map a space for programmable chip select or another external device to the lower 64 KB within external ISA I O space where I O windows are assigned Figure 17 3 Mapping of CompactFlash I O Space 0x17FF FFFF 0x1400 0000 VR4181 ISA I O space internal 64 MB I O window m I O window n 0x3F FFFF 0x00 0000 VR4181 Space specified via ADD pins 4 MB 0x7FF 0x000 CompactFlash card I O space...

Page 352: ... 1 0 and IOWS 1 0 bits of the XISACTL register of the ISA bridge regardless of whether the memory or I O is accessed In addition the ECU deasserts the IORDY signal and extends the bus cycle if the CF_WAIT signal from the CompactFlash card is asserted Additional wait states can be controlled by ECU settings 1 Wait when memory window is accessed The zero wait state can be enabled or disabled via the...

Page 353: ...gisters are listed below Table 18 1 LED Registers Physical address R W Register symbol Function 0x0B00 0240 R W LEDHTSREG LED ON time set register 0x0B00 0242 R W LEDLTSREG LED OFF time set register 0x0B00 0248 R W LEDCNTREG LED control register 0x0B00 024A R W LEDASTCREG LED auto stop time setting register 0x0B00 024C R W LEDINTREG LED interrupt register These registers are described in detail be...

Page 354: ...ote Note Bit Name Function 15 to 5 Reserved 0 is returned when read 4 to 0 HTS 4 0 LED ON time setting 11111 1 9375 seconds 10000 1 second 01000 0 5 seconds 00100 0 25 seconds 00010 0 125 seconds 00001 0 0625 seconds 00000 Prohibited Note A value before reset is retained This register is used to set the LED s ON time high level width of LEDOUT The ON time ranges from 0 0625 to 1 9375 seconds and c...

Page 355: ...ion 15 to 7 Reserved 0 is returned when read 6 to 0 LTS 6 0 LED OFF time setting 1111111 7 9375 seconds 1000000 4 seconds 0100000 2 seconds 0010000 1 second 0001000 0 5 seconds 0000100 0 25 seconds 0000010 0 125 seconds 0000001 0 0625 seconds 0000000 Prohibited Note A value before reset is retained This register is used to set the LED s OFF time low level width of LEDOUT The OFF time ranges from 0...

Page 356: ... 0 0 0 0 0 1 0 Other resets 0 0 0 0 0 0 Note Note Bit Name Function 15 to 3 Reserved 0 is returned when read 2 LEDHLB LED status indication 1 ON 0 OFF 1 LEDSTOP LED blink auto stop setting 1 Automatically stops 0 Does not stop automatically 0 LEDENABLE LED blink setting 1 Blinks 0 Does not blink Note A value before reset is retained This register is used to make various LED settings Caution When s...

Page 357: ...ion 15 to 0 ASTC 15 0 LED auto stop time count This register is used to set the number of ON OFF times prior to automatic stopping of LED blink The set value is read on a read The initial setting is 1 200 times of ON OFF pairs i e one hour in which each time includes one second of ON time and two seconds of OFF time The pair of operations in which the LED is switched ON once and OFF once is counte...

Page 358: ...R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 15 to 1 Reserved 0 is returned when read 0 LEDINT Auto stop interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Not occurred This register indicates when an auto stop interrupt request has occurred An auto stop interrupt request occurs when 1 has already been set to both the LEDSTOP bit and the LEDENABLE bit ...

Page 359: ...r LED blinking terminates when the auto stop counter reaches 0 LED blinking operation termination LEDENABLE LED blinking operation is terminated by setting 0 to this bit LED blinking operation terminate interrupt request generation LEDINT An interrupt request to the ICU is generated when 1 is set to this bit Caution Setting the LEDENABLE and LEDSTOP bits to 0 is prohibited because it may cause und...

Page 360: ... advance so that the clock is supplied 19 2 Clock Control Logic The power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer The clock control logic for the 16550 core monitors activity on the four serial interface input signals RxD1 RTS1 DCD1 and DTR1 It also monitors writes to the 16550 transmit buffer Each source has an associated ...

Page 361: ...able register 1 R W SIUDLM_1 Divisor latch most significant byte register 0x0C00 0012 R SIUIID_1 Interrupt identification register read W SIUFC_1 FIFO control register write 0x0C00 0013 R W SIULC_1 Line control register 0x0C00 0014 R W SIUMC_1 Modem control register 0x0C00 0015 R SIULS_1 Line status register 0x0C00 0016 R W SIUMS_1 Modem status register 0x0C00 0017 R W SIUSC_1 Scratch register 0x0...

Page 362: ...ndefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Name Function 7 to 0 TXD 7 0 Serial transmit data This register stores transmit data used in serial communications To access this register set the LCR7 bit bit 7 of the SIULC_1 register to 0 19 3 3 SIUDLL_1 0x0C00 0010 LCR7 1 Bit 7 6 5 4 3 2 1 0 Name DLL7 DLL6 DLL5 DLL4 DLL3 DLL2 DLL...

Page 363: ...upt or character timeout interrupt in FIFO mode 1 Enable 0 Prohibit This register is used to specify interrupt enable prohibit settings for the five types of interrupt requests used in the SIU1 An interrupt is enabled by setting the corresponding bit to 1 Overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0 When interrupts are prohibited pending is not disp...

Page 364: ... Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Name Function 7 to 0 DLM 7 0 Baud rate divisor high order byte This register is used to set the divisor division rate for the baud rate generator The data in this register and the data in the SIUDLL_1 register as lower 8 bits are together handled as 16 bit data To access this register set the LCR7 bit bit 7 of the SIULC_1 r...

Page 365: ...5 15360 13333 33 110 10473 9090 91 134 5 8565 7434 94 150 7680 6666 67 300 3840 3333 33 600 1920 1666 67 1200 960 833 33 1800 640 555 56 2000 576 500 00 2400 480 416 67 3600 320 277 78 4800 240 208 33 7200 160 138 89 9600 120 104 17 19200 60 52 08 38400 30 26 04 57600 20 17 36 115200 10 8 68 128000 9 7 81 144000 8 6 94 192000 6 5 21 230400 5 4 34 288000 4 3 47 384000 3 2 60 576000 2 1 74 1152000 1...

Page 366: ...n FIFO mode 1 No pending 0 Pending 2 1 IIR 2 1 Indicates the priority level of interrupts See the following table 0 IIR0 Pending interrupt requests 1 No pending 0 Pending This register indicates priority levels for interrupts and existence of pending interrupt requests From highest to lowest priority the involved interrupts are the receive line status the receive data ready the character timeout t...

Page 367: ... the trigger level Read the receive buffer register or lower the data in the FIFO than trigger level 1 1 0 2nd Character timeout During the time period for the four most recent characters not one character has been read from the receive FIFO nor has a character been input to the receive FIFO During this period at least one character has been held in the receive FIFO Read receive buffer register 0 ...

Page 368: ...bytes 01 4 bytes 00 0 bytes 5 4 Reserved 0 is returned when read 3 FCR3 Switch between 16450 mode and FIFO mode 1 From 16450 mode to FIFO mode 0 From FIFO mode to 16450 mode 2 FCR2 Transmit FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 1 FCR1 Receive FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 0 F...

Page 369: ...ceive interrupts are enabled receive FIFO timeout interrupt requests can occur as described below 1 Followings are the conditions under which FIFO timeout interrupt requests occur At least one character is being stored in the FIFO The time required for sending four characters has elapsed since the serial reception of the last character includes the time for the second stop bit in cases where it is...

Page 370: ...ediately The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt Whether data to be transmitted exists or not in the transmit FIFO and the transmit shift register check the LSR6 bi...

Page 371: ...arity 3 LCR3 Parity enable 1 Create parity during transmission or check parity during reception 0 No parity during transmission or no checking during reception 2 LCR2 Stop bit specification 1 1 5 bits character length is 5 bits 2 bits character length is 6 7 or 8 bits 0 1 bit 1 0 LCR 1 0 Specifies the length of one character number of bits 11 8 bits 10 7 bits 01 6 bits 00 5 bits This register is u...

Page 372: ...receive data path in SIU1 The following operation local loopback is executed inside the SIU1 when the MCR4 bit 1 The transmit block s serial output TxD1 enters the marking state 1 and the serial input RxD1 to the receive block is cut off The transmit shift register s output is looped back to the receive shift register s input The four modem control inputs DSR1 CTS1 RI internal and DCD1 are cut off...

Page 373: ...FIFO is empty during FIFO mode 0 Character is stored in transmit holding register during 16450 mode Transmit data exists in transmit FIFO during FIFO mode 4 LSR4 Break interrupt 1 Detected 0 No break 3 LSR3 Framing error 1 Detected 0 No error 2 LSR2 Parity error 1 Detected 0 No error 1 LSR1 Overrun error 1 Detected receive data is overwritten 0 No error 0 LSR0 Receive data ready 1 Receive data exi...

Page 374: ...otified of a framing error when that character reaches the highest position in the FIFO When a framing error occurs the SIU1 prepares for synchronization again The next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice The value of LSR2 bit becomes 1 when a received character does not satisfy the even or odd ...

Page 375: ...R6 RI signal internal status 1 Low level 0 High level 5 MSR5 DSR1 input status 1 Low level 0 High level 4 MSR4 CTS1 input status 1 Low level 0 High level 3 MSR3 DCD1 signal change 1 Changed 0 No change 2 MSR2 RI signal internal change 1 Changed 0 No change 1 MSR1 DSR1 signal change 1 Changed 0 No change 0 MSR0 CTS1 signal change 1 Changed 0 No change This register indicates the current status and ...

Page 376: ...efined Undefined Undefined Bit Name Function 7 to 0 SCR 7 0 General purpose data This register is a readable writable 8 bit register and can be used freely by users It does not affect control of the SIU1 19 3 13 SIURESET_1 0x0C00 0019 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIU RESET R W R R R R R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0...

Page 377: ...ask 0 Unmask 4 RTSMSK Mask for notification of change on RTS1 1 Mask 0 Unmask 3 DCDMSK Mask for notification of change on DCD1 1 Mask 0 Unmask 2 DTRMSK Mask for notification of change on DTR1 1 Mask 0 Unmask 1 Reserved Write 0 when write 0 is returned when read 0 TxWRMSK Mask for notification of transmit buffer write 1 Mask 0 Unmask This register is used to set masks for notification of operation ...

Page 378: ...UTMO7 SIUTMO6 SIUTMO5 SIUTMO4 SIUTMO3 SIUTMO2 SIUTMO1 SIUTMO0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 7 to 0 SIUTMO 7 0 SIU activity timeout period 11111111 255 x 30 5 µs 11111110 254 x 30 5 µs 01111111 127 x 30 5 µs 00000001 30 5 µs 00000000 Activity Timer disabled ...

Page 379: ...the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that the clock is supplied 20 2 Clock Control Logic The power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer The clock control logic for the 16550 core monitors activity on the four serial interface input signals RxD2 RTS2 DCD2 and DTR2 It also monitors writes to the...

Page 380: ...icant byte register 0x0C00 0002 R SIUIID_2 Interrupt identification register read W SIUFC_2 FIFO control register write 0x0C00 0003 R W SIULC_2 Line control register 0x0C00 0004 R W SIUMC_2 Modem control register 0x0C00 0005 R SIULS_2 Line status register 0x0C00 0006 R W SIUMS_2 Modem status register 0x0C00 0007 R W SIUSC_2 Scratch register 0x0C00 0008 R W SIUIRSEL_2 SIU IrDA select register 0x0C0...

Page 381: ... Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Name Function 7 to 0 TXD 7 0 Serial transmit data This register stores transmit data used in serial communications To access this register set the LCR7 bit bit 7 of the SIULC_2 register to 0 20 3 3 SIUDLL_2 0x0C00 0000 LCR7 1 Bit 7 6 5 4 3 2 1 0 Name DLL7 DLL6 DLL5 DLL4 DLL3 DLL2 D...

Page 382: ...upt or character timeout interrupt in FIFO mode 1 Enable 0 Prohibit This register is used to specify interrupt enable prohibit settings for the five types of interrupt requests used in the SIU2 An interrupt is enabled by setting the corresponding bit to 1 Overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0 When interrupts are prohibited pending is not disp...

Page 383: ...ed Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Name Function 7 to 0 DLM 7 0 Baud rate divisor high order byte This register is used to set the divisor division rate for the baud rate generator The data in this register and the data in SIUDLL_2 register as lower 8 bits are together handled as 16 bit data To access this register set the LCR7 bit bit 7 of the SIULC_2 reg...

Page 384: ...5 15360 13333 33 110 10473 9090 91 134 5 8565 7434 94 150 7680 6666 67 300 3840 3333 33 600 1920 1666 67 1200 960 833 33 1800 640 555 56 2000 576 500 00 2400 480 416 67 3600 320 277 78 4800 240 208 33 7200 160 138 89 9600 120 104 17 19200 60 52 08 38400 30 26 04 57600 20 17 36 115200 10 8 68 128000 9 7 81 144000 8 6 94 192000 6 5 21 230400 5 4 34 288000 4 3 47 384000 3 2 60 576000 2 1 74 1152000 1...

Page 385: ...n FIFO mode 1 No pending 0 Pending 2 1 IIR 2 1 Indicates the priority level of interrupts See the following table 0 IIR0 Pending interrupt requests 1 No pending 0 Pending This register indicates priority levels for interrupts and existence of pending interrupt requests From highest to lowest priority the involved interrupts are the receive line status the receive data ready the character timeout t...

Page 386: ...trigger level Read the receive buffer register or lower the data in the FIFO than trigger level 1 1 0 2nd Character timeout During the time period for the four most recent characters not one character has been read from the receive FIFO nor has a character been input to the receive FIFO During this period at least one character has been held in the receive FIFO Read receive buffer register 0 0 1 3...

Page 387: ...bytes 01 4 bytes 00 0 bytes 5 4 Reserved 0 is returned when read 3 FCR3 Switch between 16450 mode and FIFO mode 1 From 16450 mode to FIFO mode 0 From FIFO mode to 16450 mode 2 FCR2 Transmit FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 1 FCR1 Receive FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 0 F...

Page 388: ...ceive interrupts are enabled receive FIFO timeout interrupt requests can occur as described below 1 Followings are the conditions under which FIFO timeout interrupt requests occur At least one character is being stored in the FIFO The time required for sending four characters has elapsed since the serial reception of the last character includes the time for the second stop bit in cases where it is...

Page 389: ...ediately The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt Whether data to be transmitted exists or not in the transmit FIFO and the transmit shift register check the LSR6 bi...

Page 390: ...arity 3 LCR3 Parity enable 1 Create parity during transmission or check parity during reception 0 No parity during transmission or no checking during reception 2 LCR2 Stop bit specification 1 1 5 bits character length is 5 bits 2 bits character length is 6 7 or 8 bits 0 1 bit 1 0 LCR 1 0 Specifies the length of one character number of bits 11 8 bits 10 7 bits 01 6 bits 00 5 bits This register is u...

Page 391: ...receive data path in SIU2 The following operation local loopback is executed inside the SIU2 when the MCR4 bit 1 The transmit block s serial output TxD2 enters the marking state 1 and the serial input RxD2 to the receive block is cut off The transmit shift register s output is looped back to the receive shift register s input The four modem control inputs DSR2 CTS2 RI internal and DCD2 are cut off...

Page 392: ...FIFO is empty during FIFO mode 0 Character is stored in transmit holding register during 16450 mode Transmit data exists in transmit FIFO during FIFO mode 4 LSR4 Break interrupt 1 Detected 0 No break 3 LSR3 Framing error 1 Detected 0 No error 2 LSR2 Parity error 1 Detected 0 No error 1 LSR1 Overrun error 1 Detected receive data is overwritten 0 No error 0 LSR0 Receive data ready 1 Receive data exi...

Page 393: ...otified of a framing error when that character reaches the highest position in the FIFO When a framing error occurs the SIU2 prepares for synchronization again The next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice The value of LSR2 bit becomes 1 when a received character does not satisfy the even or odd ...

Page 394: ...R6 RI signal internal status 1 Low level 0 High level 5 MSR5 DSR2 input status 1 Low level 0 High level 4 MSR4 CTS2 input status 1 Low level 0 High level 3 MSR3 DCD2 signal change 1 Changed 0 No change 2 MSR2 RI signal internal change 1 Changed 0 No change 1 MSR1 DSR2 signal change 1 Changed 0 No change 0 MSR0 CTS2 signal change 1 Changed 0 No change This register indicates the current status and ...

Page 395: ...used freely by users It does not affect control of the SIU2 20 3 13 SIUIRSEL_2 0x0C00 0008 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIRSEL R W R R R W R R W R W R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 7 6 Reserved 0 is returned when read 5 Reserved Write 0 when write 0 is returned when read 4 Reserved 0 is returned ...

Page 396: ...SET SIU2 reset 1 Reset 0 Release reset This register is used to reset SIU2 forcibly 20 3 15 SIUCSEL_2 0x0C00 000A Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIUCSEL R W R R R R R R R R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 7 to 1 Reserved 0 is returned when read 0 SIUCSEL Mask for echo back of IrDA 1 Mask disabled 0 Mas...

Page 397: ...ask 0 Unmask 4 RTSMSK Mask for notification of change on RTS2 1 Mask 0 Unmask 3 DCDMSK Mask for notification of change on DCD2 1 Mask 0 Unmask 2 DTRMSK Mask for notification of change on DTR2 1 Mask 0 Unmask 1 Reserved Write 0 when write 0 is returned when read 0 TxWRMSK Mask for notification of transmit buffer write 1 Mask 0 Unmask This register is used to set masks for notification of operation ...

Page 398: ...UTMO7 SIUTMO6 SIUTMO5 SIUTMO4 SIUTMO3 SIUTMO2 SIUTMO1 SIUTMO0 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function 7 to 0 SIUTMO 7 0 SIU activity timeout period 11111111 255 x 30 5 µs 11111110 254 x 30 5 µs 01111111 127 x 30 5 µs 00000001 30 5 µs 00000000 Activity Timer disabled ...

Page 399: ... 4 bpp mode 16 colors and 8 bpp mode 256 colors The LCD controller includes a 256 entry x 18 bit color pallet In color 8 bpp mode the pallet is used to select 256 colors out of possible 262 144 colors The LCD controller can support up to 320 x 320 pixels and typical LCD panel horizontal vertical resolutions are as follows Table 21 1 LCD Panel Resolutions in Pixels TYP Horizontal resolution Vertica...

Page 400: ...K VPGPIO1 VPLCD VPGPIO0 VPBIAS 21 2 LCD Module Features Resolutions Horizontal Up to 320 pixels the number of pixels must be multiplies of 8 Vertical Up to 320 pixels Color 4 bpp 8 bpp up to 256 colors Monochrome 1 bpp 2 bpp 4 bpp up to 16 gray scale Color Palette 18 bits High vertical refresh rates for flicker free LCD frame modulation The following is a block diagram of the LCD controller ...

Page 401: ...GPU I O pins Pixel packing MBAGP interface 32 16 16 32 MGCLK 6R 6G 6B 1R 1G 1B Shift clock Load clock FLM 32 18 32 MGCLK MBA clock LCD interrupt request Data 4 bits Shift clock Load clock FLM Data 8 bits Data 4 bits Data 4 bits LCD Controller The LCD controller is a slave module of the MBA bus Its registers can be accessed via the MBA slave interface The frame data are read from main memory via th...

Page 402: ...d includes the horizontal and vertical blanks Vvisible and Hvisible define the view rectangle and outside of the view rectangle are the horizontal blank and vertical blank Figure 21 2 View Rectangle and Horizontal Vertical Blank Origin 0 0 Hvisible 1 0 Htotal 1 Vtotal 1 View rectangle LCD panel Hvisible 1 Vvisible 1 0 Vvisible 1 Vertical blank Y X Horizontal blank Each parameter is defined using b...

Page 403: ... the LCS 7 0 bits of the LDCLKSTREG register The second edge is defined by the LCE 7 0 bits of the LDCLKENDREG register and is usually inside the horizontal blank The LPPOL bit of the LCDCTRLREG register controls the directions of toggles If the LPPOL bit is 0 the first LOCLK edge is positive and the second is negative If the LPPOL bit is 1 the reverse is true Figure 21 3 Position of Load Clock LO...

Page 404: ...e FLMHE 7 0 bits of the FHENDREG register and the FLME 8 0 bits of the FVENDREG register The location of second edge is at FLMHE x 2 FLME If the FLMPOL bit of the LCDCTRLREG register is 0 the first FLM edge is positive and the second is negative If the FLMPOL bit is 1 the reverse is true Figure 21 4 Position of Frame Clock FLM Origin 0 0 Hvisible 1 0 Htotal 1 0 View rectangle FLM 0 Vvisible 1 Vert...

Page 405: ...ured to be polled or to generate an interrupt request To enable the interrupt set the MVIReq bit of the LCDIMSKREG register to 1 Once an interrupt request is generated writing to the VIReq bit clears the interrupt request However the state of the VIReq bit changes to 0 only after the controller returns to top left corner Note that there is some delay between the controller s entering or leaving th...

Page 406: ... each double word depends on the color depth as shown in the following table Bit 31 Bit 0 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 0C 0D 0E 0F 08 09 0A 0B 04 05 06 07 00 01 02 03 06 07 04 05 02 03 00 01 03 02 01 00 The frame buffer memory starts from the 32 bit address specified by the FBSA 31 0 bits of the FBSTADREG1 and FBSTADREG2 registers ...

Page 407: ...wer on sequence the power supply control pins are brought out of high impedance to a programmed state at a programmed time and the panel interface signals become active at a programmed time The following table lists the control pins and the programming register bits Pin Power on time bit Power on state bit VPBIAS Biason 4 0 BiasCon VPLCD Vccon 4 0 VccC LCD Interface I Fon 4 0 active For example st...

Page 408: ... FPD2 Output FPD3 Output W 4 0 4 8 FPD0 Output FPD1 Output W 2 2 6 10 SHCLK Output LOCLK Output W 3 1 5 9 W 1 3 7 11 W 4 0 4 W 2 2 6 W 3 1 5 W 1 3 7 SHCLK x W 4 pulses Remark W panel width Hact 5 0 x 8 The polarity order of rising and falling edges of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits ...

Page 409: ...Output W 2B 1G 4R 6B FPD4 Output FPD5 Output W 1G 2R 4B 7G W 1R 1B 4G 7R W 1B 2G 5R 7B W 3G 0R 2B W 2R 0B 3G W 3B 0G 3R W 2G 1R 3B W 2B 1G 4R W 1G 2R 4B W 1R 1B 4G W 1B 2G 5R Remark W panel width Hact 5 0 x 8 The polarity order of rising and falling edges of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits Remark In the color 8 bit data bus mode FPD 3 0 are for upper 4 bits ...

Page 410: ...re inserted when needed For example some panels can display only 240 lines but has 242 line cycles Load clock can be deactivated during the dummy lines see DummyL bit description in 21 4 6 Figure 21 8 Frame Clock FLM Pixel row 0 YE FLM Output YS 0 XE XS TH 1 TH 1 Remark YS Y Coordinates of the second FLM edge FLMS YE Y Coordinates of the first FLM edge FLME The polarity order of rising and falling...

Page 411: ... edge The two FLM edges are on the same row in this diagram but they need not be The active edge of the LOCLK is programmable through the LPPOL bit In this diagram the first edge is a rising edge the falling edge is the active edge The polarity of the SHCLK is programmable through the SCLKPOL bit In this diagram the first edge is a rising edge the falling edge is the active edge Figure 21 10 FLM P...

Page 412: ... HpckL T2 Shift clock cycle Color T2 Tg x HpckH HpckL 4 bit bus monochrome T2 Tg x HpckH HpckL x 2 T3 Panel data setup time Color T3 Tg x HpckH 4 bit bus monochrome T3 Tg x HpckH HpckL T4 Panel data hold time Color T4 Tg x HpckL 4 bit bus monochrome T4 Tg x HpckH HpckL T5 Row cycle time T5 Tg x HpckH HpckL x Htot T6 Load clock start time T6 Tg x HpckH HpckL x LCS T7 Load clock end time T7 Tg x Hpc...

Page 413: ...x0A00 0412 R W LCDINRQREG LCD interrupt request register 0x0A00 0414 R W LCDCFGREG0 LCD configuration register 0 0x0A00 0416 R W LCDCFGREG1 LCD configuration register 1 0x0A00 0418 R W FBSTADREG1 Frame buffer start address 1 register 0x0A00 041A R W FBSTADREG2 Frame buffer start address 2 register 0x0A00 0420 R W FBENDADREG1 Frame buffer end address 1 register 0x0A00 0422 R W FBENDADREG2 Frame buf...

Page 414: ...ber of horizontal total columns Set this register to a value one half of the horizontal total Horizontal total horizontal visible width horizontal blank 21 4 2 HRVISIBREG 0x0A00 0402 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Hact5 Hact4 Hact3 Hact2 Hact1...

Page 415: ... 7 to 0 LCS 7 0 X coordinate of the first edge of the LOCLK Set this register to a value one half of the first edge of the LOCLK 21 4 4 LDCLKENDREG 0x0A00 0406 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name LCE7 LCE6 LCE5 LCE4 LCE3 LCE2 LCE1 LCE0 R W R W R W R W R W R W R W R ...

Page 416: ...ed when read 8 to 0 Vtot 8 0 Vertical total number of lines including vertical retrace period 21 4 6 VRVISIBREG 0x0A00 040A Bit 15 14 13 12 11 10 9 8 Name DummyL Reserved Reserved Reserved Reserved Reserved Reserved Vact8 R W R W R R R R R R R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Vact7 Vact6 Vact5 Vact4 Vact3 Vact2 Vact1 Vact0 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 B...

Page 417: ...eset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 9 Reserved 0 is returned when read 8 to 0 FLMS 8 0 Y coordinate of the first FLM edge 21 4 8 FVENDREG 0x0A00 040E Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved FLME8 R W R R R R R R R R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name FLME7 FLME6 FLME5 FLME4 FLME3 FLME2 FLME1 FLME0 R W R W R W R W R W R W ...

Page 418: ... 0 0 0 0 0 Bit Name Function 15 to 8 Reserved 0 is returned when read 7 to 5 FIFOC 2 0 FIFO control A FIFO transfer is performed when only the number of double words set here is left in the FIFO 4 Reserved 0 is returned when read 3 ContCkE LCD controller clock enable 0 OFF 1 ON 2 LPPOL LOCLK clock polarity 0 Leading edge is rising 1 Leading edge is falling 1 FLMPOL FLM clock polarity 0 Leading edg...

Page 419: ... 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved VIReq FIFOOV ERR Reserved R W R R R R R R W R W R Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 3 Reserved 0 is returned when read 2 VIReq Vertical retrace interrupt request 0 No request outside vertical blank 1 Requested vertical blank 1 FIFOOVERR FIFO overrun interrupt request 0 No request 1 Requested 0 Reserved 0...

Page 420: ...he software reset is active only in test mode 0 Normal operation 1 Reset 6 Reserved 0 is returned when read 5 4 Pre scal 1 0 gclk clock for LCD controller pre scalar mode to the MBA clock 00 Divide by 1 01 Divide by 2 10 Divide by 4 11 RFU 3 2 Col 1 0 Color depth selection 00 1 bit black and white for monochrome panel 01 2 bits 4 gray scale for monochrome panel 10 4 bits 16 gray scale for monochro...

Page 421: ... W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved HpckH5 HpckH4 HpckH3 HpckH2 HpckH1 HpckH0 R W R R R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 14 Reserved 0 is returned when read 13 to 8 HpckL 5 0 Number of gclk cycles for hpck low level width 7 6 Reserved 0 is returned when read 5 to 0 HpckH 5 0 Number of gclk cycles for hpck high level width ...

Page 422: ...its must be cleared to 0 21 4 14 FBSTADREG2 0x0A00 041A Bit 15 14 13 12 11 10 9 8 Name FBSA31 FBSA30 FBSA29 FBSA28 FBSA27 FBSA26 FBSA25 FBSA24 R W R R R R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name FBSA23 FBSA22 FBSA21 FBSA20 FBSA19 FBSA18 FBSA17 FBSA16 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 0 FBSA 31 16 Frame buffer start address up...

Page 423: ...W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 0 FBEA 15 0 Frame buffer end address lower 16 bits 21 4 16 FBENDADREG2 0x0A00 0422 Bit 15 14 13 12 11 10 9 8 Name FBEA31 FBEA30 FBEA29 FBEA28 FBEA27 FBEA26 FBEA25 FBEA24 R W R R R R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name FBEA23 FBEA22 FBEA21 FBEA20 FBEA19 FBEA18 FBEA17 FBEA16 R W R W R W R W R W R W R W R W R W R...

Page 424: ...rned when read 7 to 0 FLMHS 7 0 X coordinate of the first FLM edge Set this register to a value one half of the first edge of FLM 21 4 18 FHENDREG 0x0A00 0426 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name FLMHE7 FLMHE6 FLMHE5 FLMHE4 FLMHE3 FLMHE2 FLMHE1 FLMHE0 R W R W R W R W...

Page 425: ...erved R W R R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Biason4 Biason3 Biason2 Biason1 Biason0 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 Reserved 0 is returned when read 14 to 5 Reserved Write 0 when write 0 is returned when read 4 to 0 Biason 4 0 Frame at which the bias voltage is turned on ...

Page 426: ...0 R W R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 Testmode Test mode enable 0 Normal operation 1 Enters test mode 14 VccC Vcc VPLCD signal polarity control 0 Active low 1 Active high 13 12 Reserved Write 0 when write 0 is returned when read 11 BiasCon Bias VPBIAS signal polarity control 0 Active low 1 Active high 10 PowerC Power control 0 Off 1 On 9 to 5 I Fon 4 0 Fr...

Page 427: ...R W R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved MVIReq MFIFO OVERR Reserved R W R R R R R R W R W R Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 3 Reserved 0 is returned when read 2 MVIReq Vertical retrace interrupt mask 0 Mask 1 Unmask 1 MFIFOOVERR FIFO overrun interrupt mask 0 Mask 1 Unmask 0 Reserved 0 is returned when read ...

Page 428: ... R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 15 to 12 PalPage 3 0 Palette page select used in 4 bpp mode 11 10 Reserved 0 is returned when read 9 PalRDI Palette index read status 0 No change after read 1 Incremented by 1 after read 8 PalWRI Palette index write status 0 No change after write 1 Incremented by 1 after write 7 to 0 PalIndex 7 0 Palette index Remark In the 4 bpp mode 16 gra...

Page 429: ...5 14 13 12 11 10 9 8 Name PalData15 PalData14 PalData13 PalData12 PalData11 PalData10 PalData9 PalData8 R W R W R W R W R W R W R W R W R W Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit 7 6 5 4 3 2 1 0 Name PalData7 PalData6 PalData5 PalData4 PalData3 PalData2 PalData1 PalData0 R W R W R W R W R W R W R W R W R W Reset Undefined Undefined Undefined Undef...

Page 430: ...em the optimum values for each system should be decided after repeated experimentation It is essential to isolate the analog power and ground for the PLL circuit VDD_PLL GND_PLL from the regular power and ground VDD_LOGIC GND_LOGIC The following values are an example for each component R 100 Ω C1 0 1 µF C2 1 0 µF Since the optimum values for the filter components depend upon the application and th...

Page 431: ...ds of the VR4110 CPU core are as or less stringent than those of the VR4000 Table 23 1 lists the Coprocessor 0 hazards of the VR4110 CPU core Code that complies with these hazards will run without modification on the VR4000 The contents of the CP0 registers or the bits in the Source column of this table can be used as a source after they are fixed The contents of the CP0 registers or the bits in t...

Page 432: ...tatus EXL Status ERL 4 CACHE Index Load Tag TagLo TagHi PErr 5 CACHE Index Store Tag TagLo TagHi PErr 3 CACHE Hit operations cache line 3 cache line 5 Coprocessor usable test Status CU KSU EXL ERL 2 EntryHi ASID Status KSU EXL ERL RE Config K0 2 Instruction fetch TLB 2 EPC Status 4 Instruction fetch exception Cause BadVAddr Context XContext 5 Interrupts Cause IP Status IM IE EXL ERL 2 EntryHi ASID...

Page 433: ...tore and a CACHE instruction directed to the same cache line to be stored The status during execution of the following instruction for which CP0 hazards must be considered is described below 1 MTC0 Destination The completion of writing to a destination register CP0 of MTC0 2 MFC0 Source The confirmation of a source register CP0 of MFC0 3 TLBR Source The confirmation of the status of TLB and the In...

Page 434: ...ter the KSU EXL and ERL bits of the Status register are modified 2 When fetching instructions using the modified TLB entry after TLB modification 11 Instruction fetch exception Destination The completion of writing to registers containing information related to the exception when an exception occurs on instruction fetch 12 Interrupts Source The confirmation of registers judging the condition of oc...

Page 435: ...uction that requires the setting of CU Status CU 2 5 2 1 TLBR MFC0 EntryHi EntryHi 1 5 3 1 MTC0 EntryLo0 TLBWR TLBWI EntryLo0 2 5 2 1 TLBP MFC0 Index Index 2 6 3 1 MTC0 EntryHi TLBP EntryHi 2 5 2 1 MTC0 EPC ERET EPC 2 5 2 1 MTC0 Status ERET Status 2 5 2 1 MTC0 Status IE Note Instruction that causes an interrupt Status IE 2 5 2 1 Note The number of hazards is undefined if the instruction execution ...

Page 436: ...cuits Particularly when the reset signal to a flash memory that includes a boot vector and the RSTSW signal are shared the VR4181 may not be able to read the correct program and hang up for 4 seconds between when the VR4181 is started and when the HALTimer is shut down Workaround Do not share the reset signal to the external peripheral circuits with the RSTSW signal However if it is necessary to d...

Page 437: ...released After that DRAM returns to the self refresh mode At this time the following phenomena may occur and the DRAM data may be lost DRAM is in the normal operation mode while the RAS signal is high a in Figure A 2 but a CBR refresh is not executed The high level output of the CAS signal b in Figure A 2 may be a spike Figure A 2 Release of Self Refresh Mode by RSTSW Signal EDO DRAM RAS 1 0 outpu...

Page 438: ...gnal is kept low this problem does not occur in SDRAM that requires the rising edge of the SDCLK signal to release the self refresh mode Figure A 3 Release of Self Refresh Mode by RSTSW Signal SDRAM CLKEN output SDCLK output L RSTSW input RTC internal SDCS 1 0 output SDRAS output CAS output Workaround Mask the RSTSW signal via an external circuit using the MPOWER signal and GPIO pin so that the RS...

Page 439: ...DREG 113 bpp 34 399 bus control 108 bus control registers 110 bus cycles 16 bits 242 bus interface 31 bus size 352 C cache 44 106 cache algorithm 71 Cache Error register 87 card CompactFlash 350 352 detection 338 347 status change 338 347 Cause register 79 CDSTCHGREG 338 CFG_REG_1 333 CLKSPEEDREG 117 clock control 360 379 clock interface 47 clock interface signals 55 clock oscillator 48 clock supp...

Page 440: ... 334 EDO DRAM 128 129 192 201 203 205 207 437 EDOMCYTREG 131 ElapsedTime timer 216 endian 40 EntryHi register 75 EntryLo register 70 EPC register 81 ErrorEPC register 89 ETIMEHREG 218 ETIMELREG 217 ETIMEMREG 217 ExCA 328 exception code 80 external ROM connection 119 cycle 125 memory map 118 external system bus space 93 F FBENDADREG1 423 FBENDADREG2 423 FBSTADREG1 422 FBSTADREG2 422 FHENDREG 424 FH...

Page 441: ...or 1 342 IOADSLBnREG n 0 or 1 342 IOCTRL_REG 341 IOSHBnREG n 0 or 1 343 IOSLBnREG n 0 or 1 343 IrDA 32 395 396 IrDA interface signals 58 ISA Bridge 137 ISABRGCTL 138 ISABRGSTS 139 ITGENCTREG 337 K key press 317 318 keyboard interface signals 56 keyboard interface unit 317 KEYEN 267 KIU 317 KIU register 321 KIUDATn n 0 to 7 322 KIUINT 327 KIUINTREG 184 KIUSCANREP 323 KIUSCANS 324 KIUWKI 326 KIUWKS ...

Page 442: ...panel 408 420 MPIUINTREG 185 MSYSINT1REG 176 MSYSINT2REG 181 N NMIREG 178 O operating modes 78 ordinary ROM 114 120 125 P PageROM 114 121 122 126 page sizes 72 PageMask register 72 palette 406 428 429 Parity Error register 87 PC 37 PCLK 47 138 PClock 31 47 57 117 PCS0HIA 269 PCS0STPA 268 PCS0STRA 268 PCS1HIA 271 PCS1STPA 270 PCS1STRA 270 PCSMODE 272 physical address 92 pin functions 52 configurati...

Page 443: ...5 SCK phase 157 SCNTREG 307 SCNVC_END 308 SDCLK 47 135 SDMADATREG 303 SDRAM 130 192 202 204 206 207 438 SDTIMINGREG 136 SEQREG 312 serial interface 239 240 serial interface signals 57 serial interface unit 1 360 serial interface unit 2 379 SHCLK 405 shift clock 405 shutdown control 193 SIU1 360 SIU1 registers 361 SIU2 379 SIU2 registers 380 SIUACTMSK_1 377 SIUACTMSK_2 397 SIUACTTMR_1 378 SIUACTTMR...

Page 444: ...rface signals 52 system control coprocessor 67 T TagHi register 88 TagLo register 88 TClock 31 47 57 117 timing parameter 411 TLB 44 touch detection 298 touch panel 276 touch panel interface signals 56 touch panel interface unit 275 transmit FIFO 160 370 389 transmit operation 156 U UMA 34 399 V VDD signals 59 vertical blank 402 405 view rectangle 402 VOLTSELREG 349 VOLTSENREG 348 VRTOTALREG 416 V...

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