CHAPTER 1 INTRODUCTION
User’s Manual U14272EJ3V0UM
37
1.4.1 CPU registers
The V
R
4110 core has thirty-two 64-bit general-purpose registers (GPRs).
In addition, the processor provides the following special registers:
•
64-bit Program Counter (PC)
•
64-bit HI register, containing the integer multiply and divide upper doubleword result
•
64-bit LO register, containing the integer multiply and divide lower doubleword result
Two of the general-purpose registers have assigned functions as follows:
•
r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to
be discarded. r0 can also be used as a source when a zero value is needed.
•
r31 is the link register used by link instructions, such as JAL (Jump and Link) instruction. This register can be
used for other instructions. However, be careful that use of the register by a link instruction will not coincide
with use of the register for other operations.
The register group is provided within the CP0, to process exceptions and to manage addresses.
CPU registers can operate as either 32-bit or 64-bit registers, depending on the V
R
4181 processor mode of
operation.
The operation of the CPU registers differs depending on what instructions are executed: 32-bit instructions or
MIPS16 instructions. For details, refer to V
R
4100 Series Architecture User’s Manual.
The V
R
4181 has no Program Status Word (PSW) register as such; this is covered by the Status and Cause
registers incorporated within the CP0 (see 1.4.4 CP0 registers).
Figure 1-3 shows the CPU registers.
Figure 1-3. CPU Registers
0
31
32
63
HI
0
31
32
63
LO
0
PC
31
General-purpose registers
Multiply/divide registers
Program Counter
0
32
31
63
32
63
r2
r1
r0 = 0
r31 = LinkAddress
r30
r29
