CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2.21 TagLo (28) and TagHi (29) registers
The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag during cache
initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and MTC0
instructions.
The contents of these registers are undefined after a reset.
Figure 3-25. TagLo Register
31
10
9
8
7
6
0
PTagLo
(a) When used with data cache
V
D
W
0
31
10
9
8
0
PTagLo
(b) When used with instruction cache
V
0
PTagLo:
Specifies physical address bits 31 to 10.
V:
Valid bit
D:
Dirty bit. However, this bit is defined only for the compatibility with the V
R
4000 Series processors,
and does not indicate the status of cache memory in spite of its readability and writability. This bit
cannot change the status of cache memory.
W:
Writeback bit (set if cache line has been updated)
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
Figure 3-26. TagHi Register
31
0
0
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
