User’s Manual U14272EJ3V0UM
14
2.2.7 LED interface signals ...................................................................................................................
56
2.2.8 CompactFlash interface and keyboard interface signals .............................................................
56
2.2.9 Serial interface channel 1 signals ................................................................................................
57
2.2.10 IrDA interface signals ................................................................................................................
58
2.2.11 General-purpose I/O signals ......................................................................................................
58
2.2.12 Dedicated V
DD
/GND signals ......................................................................................................
59
2.3 Pin Status in Specific Status .................................................................................................. 60
2.4 Recommended Connection of Unused Pins and I/O Circuit Types .................................... 63
2.5 Pin I/O Circuits ......................................................................................................................... 66
CHAPTER 3 CP0 REGISTERS ............................................................................................................ 67
3.1 Coprocessor 0 (CP0) ............................................................................................................... 67
3.2 Details of CP0 Registers ......................................................................................................... 69
3.2.1 Index register (0) .........................................................................................................................
69
3.2.2 Random register (1) .....................................................................................................................
69
3.2.3 EntryLo0 (2) and EntryLo1 (3) registers ......................................................................................
70
3.2.4 Context register (4) ......................................................................................................................
71
3.2.5 PageMask register (5) .................................................................................................................
72
3.2.6 Wired register (6) .........................................................................................................................
73
3.2.7 BadVAddr register (8) ..................................................................................................................
74
3.2.8 Count register (9) .........................................................................................................................
74
3.2.9 EntryHi register (10) ....................................................................................................................
75
3.2.10 Compare register (11) ...............................................................................................................
76
3.2.11 Status register (12) ....................................................................................................................
76
3.2.12 Cause register (13) ....................................................................................................................
79
3.2.13 Exception Program Counter (EPC) register (14) .......................................................................
81
3.2.14 Processor Revision Identifier (PRId) register (15) .....................................................................
82
3.2.15 Config register (16) ....................................................................................................................
83
3.2.16 Load Linked Address (LLAddr) register (17) .............................................................................
84
3.2.17 WatchLo (18) and WatchHi (19) registers .................................................................................
85
3.2.18 XContext register (20) ...............................................................................................................
86
3.2.19 Parity Error register (26) ............................................................................................................
87
3.2.20 Cache Error register (27) ...........................................................................................................
87
3.2.21 TagLo (28) and TagHi (29) registers .........................................................................................
88
3.2.22 ErrorEPC register (30) ...............................................................................................................
89
CHAPTER 4 MEMORY MANAGEMENT SYSTEM ............................................................................ 91
4.1 Overview ................................................................................................................................... 91
4.2 Physical Address Space ......................................................................................................... 92
4.2.1 ROM space ..................................................................................................................................
93
4.2.2 External system bus space ..........................................................................................................
93
4.2.3 Internal I/O space ........................................................................................................................
94
4.2.4 DRAM space ...............................................................................................................................
95
