APPENDIX A RESTRICTIONS ON V
R
4181
User’s Manual U14272EJ3V0UM
437
A.2 RSTSW# in Hibernate Mode
The V
R
4181 may release the self-refresh mode of DRAM when the RSTSW# signal is asserted in the Hibernate
mode. As a result, the DRAM data may be lost.
(1) With EDO DRAM
When the RSTSW# signal goes low, the RAS# and CAS# signals go high and the self-refresh mode is released.
After that DRAM returns to the self-refresh mode. At this time, the following phenomena may occur, and the
DRAM data may be lost.
•
DRAM is in the normal operation mode while the RAS# signal is high ((a) in Figure A-2) but a CBR refresh is
not executed.
•
The high-level output of the CAS# signal ((b) in Figure A-2) may be a spike.
Figure A-2. Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM)
RAS(1:0)# (output)
(a)
LCAS#, UCAS# (output)
Exit self-refresh mode
Resume self-refresh mode
RSTSW# (input)
RTC (internal)
(b)
(c)
Pulse width: (a) 30 to 60
µ
s
(b) 0 (spike) to 30
µ
s
(c) 30
µ
s
