CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User’s Manual U14272EJ3V0UM
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10.6 DRAM Interface Control
The PMU provides a register to control the DRAM interface during Hibernate mode or Suspend mode. The
DRAMHIBCTL register permits software to directly control the state of the DRAM interface pins prior to executing a
HIBERNATE or SUSPEND instruction.
The DRAMHIBCTL register also provides status indication of the memory controller.
The software flow when entering and exiting Hibernate mode or Suspend mode is shown below.
10.6.1 Entering Hibernate mode (EDO DRAM)
<1> Copy contents of all 2.5 V registers (i.e. DRAM type and configuration, ROM type and configuration, etc.)
that must be preserved during Hibernate mode into the general-purpose registers, MISCREG(0:15), in the
GIU or into external memory.
Remark
3.3 V peripheral units: PMU, GIU, LED, and RTC
2.5 V peripheral units: all peripherals except PMU, GIU, LED, and RTC
<2> Stop operations of the DMA controller and LCD controller.
<3> Copy the codes for the Hibernate mode (<4> through <11> below) beginning at a 16-byte boundary into
the cache by using a Fill operation of CACHE instruction, and jump to the cached codes.
<4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge.
<5> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the
refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute
CBR refresh cycles for a specific time period (i.e. 0x3FFF
×
TClock burst refresh interval
required by DRAM).
<6> Set 0x3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to
maximum to prevent an interruption of a Hibernate mode sequence.
<7> Set the SUSPEND bit in the DRAMHIBCTL register to 1. If the BstRefr bit of the MEMCFG_REG register
in the memory controller to 1, the memory controller performs a burst refresh cycle and then put the
DRAM into self-refresh mode.
<8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller completes
a burst refresh cycle and put the DRAM into self-refresh mode.
<9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory
controller.
<10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched.
<11> Execute a HIBERNATE instruction.
<12> Stop applying 2.5 V power supply when the MPOWER signal becomes low level.
Caution When entering Hibernate mode, set the BEV bit of the Status register in the CP0 of the CPU core
to 1 to make sure that the vector of the exception handler points the ROM area.
