CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2.10 Compare register (11)
The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own.
When the value of the Count register (see 3.2.8 Count register (9)) equals the value of the Compare register, the
IP7 bit in the Cause register is set. This causes an interrupt as soon as the interrupt is enabled. Writing a value to
the Compare register, as a side effect, clears the timer interrupt request.
For diagnostic purposes, the Compare register is a read/write register. Normally, this register should be only used
for a write.
The contents of the Compare register are undefined after a reset.
Figure 3-11. Compare Register
0
31
Compare
Compare: Value that is compared with the count value of the Count register.
3.2.11 Status register (12)
The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic
states of the processor.
Figure 3-12. Status Register (1/2)
29 28 27 26 25 24
16 15
8
7
6
5
3
2
1
0
31
0
CU0
0
RE
DS
IM
UX
KSU
ERL
IE
KX SX
EXL
4
CU0:
Enables/disables the use of the coprocessor (1
→
Enabled, 0
→
Disabled).
CP0 can be used in Kernel mode at all times.
RE:
Enables/disables reversing of the endian setting in User mode (0
→
Disabled, 1
→
Enabled). This
bit must be set to 0 since the V
R
4181 supports the little-endian order only.
DS:
Diagnostic Status field (see Figure 3-13).
IM:
Interrupt mask field used to enable/disable interrupts (0
→
Disabled, 1
→
Enabled). This field
consists of 8 bits that are used to control eight interrupts. The bits are assigned to interrupts as
follows:
IM7:
Masks a timer interrupt.
IM(6:2):
Mask ordinary interrupts (Int(4:0)
Note
). However, Int(4:3)
Note
never occur in the V
R
4181.
IM(1:0):
Mask software interrupts.
Note
Int(4:0) are internal signals of the V
R
4110 CPU core. For details about connection to
the on-chip peripheral units, refer to CHAPTER 9 INTERRUPT CONTROL UNIT
(ICU).
