CHAPTER 1 INTRODUCTION
User’s Manual U14272EJ3V0UM
31
1.3.1 CPU core
The V
R
4181 integrates an NEC Electronics’ V
R
4110 CPU core supporting both the MIPS III and MIPS16
instruction sets.
The V
R
4181 supports the following pipeline clock (PClock) and internal bus clock (TClock) frequencies. The
PClock is set by attaching pull-up or pull-down resistors to the CLKSEL(2:0) pins. The frequency of the TClock, which
is used in MBA bus, is set by PMUDIVREG register in Power Management Unit.
Table 1-1. Supported PClock and TClock Frequencies
PClock frequency
TClock frequency
65.4 MHz
65.4/32.7/21.8 MHz
62.0 MHz
62.0/31.0/20.7 MHz
49.1 MHz
49.1/24.6 MHz
The V
R
4110 core of the V
R
4181 includes 4 KB of instruction cache and 4 KB of data cache.
The V
R
4110 core also supports the following power management modes:
•
Fullspeed
•
Standby
•
Suspend
Note
•
Hibernate
Note
Suspend mode is supported only when the internal LCD controller has been disabled or the LCD panel
has been powered off.
1.3.2 Bus interface
The V
R
4181 incorporates single bus architecture. All external memory and I/O devices are connected to the same
22-bit address bus and 16-bit data bus. These external address and data bus are together called the system bus.
When the external bus operates at a very high speed, the DRAM data bus must be isolated from other low speed
devices such as ROM array. The V
R
4181 provides two pins, SYSEN# and SYSDIR, to control the data buffers for this
isolation.
The V
R
4181 supports the following types of devices connected to the system bus.
Table 1-2. Devices Supported by System Bus
Device
Data width
ROM, flash memory
16 bits only
DRAM
16 bits only
CompactFlash
8 or 16 bits
External I/O
8 or 16 bits
External memory
8 or 16 bits
Six of the external bus interface signals, IORD#, IOWR#, IORDY, IOCS16#, MEMCS16# and RESET#, can be
individually defined as general-purpose I/O pins or LCD interface pin if they are not needed by external system
components.
