CHAPTER 23 COPROCESSOR 0 HAZARDS
User’s Manual U14272EJ3V0UM
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Cautions 1. If the setting of the K0 bit in the Config register is changed by executing an MTC0 instruction
within the kseg0 or ckseg0 area, the change is reflected one to three instructions later from the
MTC0 instruction.
2.
The instruction following an MTC0 instruction must not be an MFC0 instruction.
3.
The five instructions following an MTC0 instruction for the Status register that changes the
KSU bit and sets the EXL and ERL bits may be executed in the new mode, and not kernel mode.
This can be avoided by setting the EXL bit first, leaving the KSU bit set to kernel, and later
changing the KSU bit.
4.
If interrupts are disabled by setting the EXL bit in the Status register with an MTC0 instruction,
an interrupt may occur immediately after the MTC0 instruction without change of the contents
of the EPC register. This can be avoided by clearing the IE bit first, and later setting the EXL bit.
5.
There must be two non-load, non-CACHE instructions between a store and a CACHE
instruction directed to the same cache line to be stored.
The status during execution of the following instruction for which CP0 hazards must be considered is described
below.
(1) MTC0
Destination: The completion of writing to a destination register (CP0) of MTC0.
(2) MFC0
Source:
The confirmation of a source register (CP0) of MFC0.
(3) TLBR
Source:
The confirmation of the status of TLB and the Index register before the execution of TLBR.
Destination: The completion of writing to a destination register (CP0) of TLBR.
(4) TLBWI, TLBWR
Source:
The confirmation of a source register of these instructions and registers used to specify a TLB
entry.
Destination: The completion of writing to TLB by these instructions.
(5) TLBP
Source:
The confirmation of the PageMask register and the EntryHi register before the execution of TLBP.
Destination: The completion of writing the result of execution of TLBP to the Index register.
(6) ERET
Source:
The confirmation of registers containing information necessary for executing ERET.
Destination: The completion of the processor state transition by the execution of ERET.
(7) CACHE Index Load Tag
Destination: The completion of writing the results of execution of this instruction to the related registers.
