CHAPTER 2 PIN FUNCTIONS
User’s Manual U14272EJ3V0UM
52
2.2 Pin Function Description
Remark
# indicates active low.
2.2.1 System bus interface signals
(1/2)
Signal name
I/O
Description of function
ADD(21:0)
Note
Output
Address bus.
Used to specify address for the DRAM, ROM, flash memory, or system bus (ISA).
DATA(15:0)
I/O
Data bus.
Used to transmit and receive data between the V
R
4181 and DRAM, ROM, flash
memory, or system bus.
IORD#/GPIO16
I/O
System bus I/O read signal output or general-purpose I/O.
It is active when the V
R
4181 accesses the system bus to read data from an I/O port
when configured as IORD#.
IOWR#/GPIO17
I/O
System bus I/O write signal output or general-purpose I/O.
It is active when the V
R
4181 accesses the system bus to write data to an I/O port
when configured as IOWR#.
IORDY/GPIO18
I/O
System bus I/O channel ready input or general-purpose I/O.
Set this signal as active when system bus controller is ready to be accessed by the
V
R
4181 when configured as IORDY.
IOCS16#/GPIO19
I/O
Bus sizing request input for system bus I/O or general-purpose I/O.
Set this signal as active when system bus I/O accesses data in 16-bit width, if
configured as IOCS16#.
UBE#/GPIO20/M
I/O
System bus upper byte enable output, general-purpose input, or LCD modulation
output.
During system bus accesses, this signal is active when the high-order byte is valid on
the data bus.
RESET#/GPIO21
I/O
System bus reset output or general-purpose I/O.
It is active when the V
R
4181 resets the system bus controller when configured as
RESET#.
Note The V
R
4181 utilizes different addressings depending on the types of the external accesses.
During ROM accesses, bits 22 to 1 of the internal address lines are output to the ADD(21:0) pins (the
minimum transfer data width is a half word (1 word = 32 bits)).
During accesses other than ROM accesses, bits 21 to 0 of the internal address lines are output to the
ADD(21:0) pins (the minimum transfer data width is 1 byte).
