CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2.5 PageMask register (5)
The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison
mask that sets the page size for each TLB entry, as shown in Table 3-3. Five page sizes can be selected between 1
KB and 256 KB.
TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets
of comparison are masked during address translation.
The contents of the PageMask register are undefined after a reset so that it must be initialized by software.
Figure 3-5. PageMask Register
31
19 18
11 10
0
MASK
0
0
MASK:
Page comparison mask, which determines the virtual page size for the corresponding entry.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
Table 3-3 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB behaves
unexpectedly.
Table 3-3. Mask Values and Page Sizes
Page size
Bit
18
17
16
15
14
13
12
11
1 KB
0
0
0
0
0
0
0
0
4 KB
0
0
0
0
0
0
1
1
16 KB
0
0
0
0
1
1
1
1
64 KB
0
0
1
1
1
1
1
1
256 KB
1
1
1
1
1
1
1
1
