CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2)
User’s Manual U14272EJ3V0UM
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LSR7 bit is valid only in FIFO mode, and it indicates always 0 in 16450 mode.
The value of LSR4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time
required for transmission of one word (start bit + data bits + parity bit + stop bit). When in FIFO mode, if a break is
detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a
break when that character reaches the highest position in the FIFO. When a break occurs, one “zero” character is
sent to the FIFO. When the RxD2 enters marking status, and the next valid start bit is received, the next character
can be transmitted.
The value of LSR3 bit becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or
parity bit. When in FIFO mode, if a framing error is detected for one character in the FIFO, the character is regarded
as an error character and the CPU is notified of a framing error when that character reaches the highest position in
the FIFO. When a framing error occurs, the SIU2 prepares for synchronization again. The next start bit is assumed
to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice.
The value of LSR2 bit becomes 1 when a received character does not satisfy the even or odd parity specified in
the LCR4 bit. When in FIFO mode, if a parity error is detected for one character within the FIFO, the character is
regarded as an error character and the CPU is notified of a parity error when that character reaches the highest
position in the FIFO.
The value of LSR1 bit becomes 1 when a character is transferred to the receive buffer register before reading by
the CPU and the previous character is lost. When in FIFO mode, if the data continues to be transferred to the FIFO
though it exceeds the trigger level, even after the FIFO becomes full an overrun error will not occur until all
characters are stored in the shift register.
The CPU is notified as soon as an overrun error occurs. The characters in the shift register are overwritten and
are not transferred to the FIFO.
