CHAPTER 3 CP0 REGISTERS
User’s Manual U14272EJ3V0UM
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3.2.9 EntryHi register (10)
The EntryHi register is write-accessible. It is used to access the built-in TLB. The EntryHi register holds the high-
order bits of a TLB entry for TLB read and write operations. If a TLB Refill, TLB Invalid, or TLB Modified exception
occurs, the EntryHi register holds the high-order bit of the TLB entry. The EntryHi register is also set with the virtual
page number (VPN2) for a virtual address where an exception occurred and the ASID. See V
R
4100 Series
Architecture User’s Manual for details of the TLB exception.
The ASID is used to read from or write to the ASID field of the TLB entry. It is also checked with the ASID of the
TLB entry as the ASID of the virtual address during address translation.
The EntryHi register is accessed by the TLBP, TLBWR, TLBWI, and TLBR instructions.
The contents of the EntryHi register are undefined after a reset so that it must be initialized by software.
Figure 3-10. EntryHi Register
31
11 10
8
7
0
(a) 32-bit mode
(b) 64-bit mode
VPN2
0
ASID
63
62 61
11 10
40 39
8
7
0
Fill
VPN2
R
0
ASID
VPN2:
Virtual page number divided by two (mapping to two pages)
ASID:
Address space ID. An 8-bit ASID field that allows multiple processes to share the TLB; each
process has a distinct mapping of otherwise identical virtual page numbers.
R:
Space type (00
→
user, 01
→
supervisor, 11
→
kernel). Matches bits 63 and 62 of the virtual
address.
Fill:
Reserved. Ignored on write. When read, returns zero.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
