CHAPTER 5 INITIALIZATION INTERFACE
User’s Manual U14272EJ3V0UM
98
5.1.2 RSTSW reset
After the RSTSW# pin becomes active and then becomes inactive 100
µ
s later, the V
R
4181 starts PLL oscillation
and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL
oscillation).
An RSTSW reset basically initializes the entire internal state except for the RTC timer, the GIU, and the PMU. The
V
R
4181 has function to preserve DRAM data during RSTSW reset. For detail, refer to CHAPTER 10 POWER
MANAGEMENT UNIT (PMU).
After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset exception vectors in the ROM space. Since only part of the internal status is reset
when a reset occurs in the V
R
4181, the processor should be completely initialized by software (see 5.4 Notes on
Initialization).
Figure 5-2. RSTSW Reset
L
16MasterClock
Note
Reset# (Internal)
ColdReset# (Internal)
MPOW ER (Output)
POWER (Input)
RSTSW# (Input)
16 ms
PLL (Internal)
> 3RTC
H
Stable oscillation
Stable oscillation
Undefined
Stable oscillation
RTC (Internal,
32.768 kHz)
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
