Mitsubishi Electric M32170F3VFP, User Manual

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15
15-3 Ver.0.10
EXTERNAL BUS INTERFACE
15.1 External Bus Interface Related Signals
(6) Data bus (DB0 - DB15)
This is the 16-bit data bus used to access external devices.
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(7) System clock/write (BCLK / WR)
The pin function changes depending on the Bus Mode Control Register (BUSMODC).
When BUSMOD = 0 and this signal is System Clock (BCLK), it outputs the system clock necessary
to synchronize operations in an external system. When the CPU clock = 40 MHz, a 20 MHz clock is
output from BCLK. When not using the BCLK/WR function, this pin can be used as P70 by setting
the P7 Operation Mode Register P70MOD bit to 0.
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When BUSMOD = 1 and this signal is Write (WR), during external write access it indicates the valid
data on the data bus to transfer. During external read cycle and when accessing the internal
function, it outputs a high.
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(8) Wait (WAIT)
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When the 32170 started an external bus cycle, it automatically inserts wait cycles while the WAIT
signal is asserted. For details, refer to Chapter 16, "Wait Controller." When not using the WAIT
function, this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0.
Note that the 32170 always inserts one or more wait cycles for external access. Therefore, the
shortest time in which an external device can be accessed is one wait cycle (2 BCLK periods).
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(9) Hold control (HREQ, HACK)
The hold state refers to a state in which the 32170 has stopped bus access and bus interface
related pins are tristated (high impedance). While the 32170 is in a hold state, any bus master
external to the chip can use the system bus to transfer data.
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The 32170 is placed in a hold state by pulling the HREQ pin input low. While the 32170 remains in
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a hold state after accepting the hold request and during a transition to the hold state, the HACK pin
outputs a low-level signal. To exit from the hold state and return to normal operating state, release
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the HREQ signal back high. When not using the HREQ and HACK functions, these pins can be
used as P72 and P7 by setting the P73 Operation Mode Register P72MOD and P73MOD bits to 0.
The status of each 32170 pin during hold are shown below.
Table 15.1.1 Pin State during Hold Period
Pin Name Pin State or Operation
___ ___ __ ___ ___ ___ ___ __
A11-A30, DB0-DB15, CS0, CS1, RD, BHW, BLW, BHE, BLE, WR High impedance
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HACK Outputs a low
Other pins (e.g., ports and timer output) Normal operation