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9

9-2

Ver.0.10

9.1 Outline of the DMAC

The 32170 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer

data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O,

and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O.

Table 9.1.1 Outline of the DMAC

Item

Description

Number of channel

10 channels

Transfer request

• Software trigger

• Request from internal peripheral I/Os: A-D converter, multijunction timer, or serial

I/O (reception completed, transmit buffer empty)

• Transfer operation can be cascaded between DMA channels (Note)

Maximum number

256 times

of times transferred

Transferable

• 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF)

address space

• Transfers between internal peripheral I/Os, between internal RAM and internal

peripheral I/O, between internal RAMs are supported

Transfer data size

16 or 8 bits

Transfer method

Single transfer DMA (control of the internal bus is relinquished for each transfer

performed), dual-address transfer

Transfer mode

Single transfer mode

Direction of transfer

One of three modes can be selected for the source and destination:

• Address fixed

• Address incremental

• Ring buffered

Channel priority

Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel

6 > channel 7 > channel 8 > channel 9 (Priority is fixed)

Maximum transfer rate 13.3 Mbytes per second (with 20 MHz internal peripheral clock)

Interrupt request

Group interrupt request can be generated when each transfer count register underflows.

Transfer area

64 Kbytes from H'0080 0000 to H'0080 FFFF

(Transferable in the entire internal RAM/SFR area)

Note: Transfer operation can be cascaded between DMA channels as shown below.

Completion of one transfer in channel 0 starts DMA transfer in channel 1

Completion of one transfer in channel 1 starts DMA transfer in channel 2
Completion of one transfer in channel 2 starts DMA transfer in channel 0
Completion of one transfer in channel 3 starts DMA transfer in channel 4
Completion of one transfer in channel 5 starts DMA transfer in channel 6
Completion of one transfer in channel 6 starts DMA transfer in channel 7
Completion of one transfer in channel 7 starts DMA transfer in channel 5
Completion of one transfer in channel 8 starts DMA transfer in channel 9
Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer
in channel 5

DMAC

9.1 Outline of the DMAC

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Summary of Contents for M32170F3VFP

Page 1: ...ems Corporation NOTE Information in this manual may be changed without prior notice Mitsubishi 32 bit RISC Single chip Microcomputers M32R Family M32R E Series 2000 03 17 Ver0 10 Group M32170F6VFP WG M32170F4VFP WG M32170F3VFP WG User s Manual 32170 Preliminary ADVANCED AND EVER ADVANCING ...

Page 2: ...accuracies or typographical errors Mitsubishi Electric Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Mitsubishi Electric Corporation by various means including the Mitsubishi Semiconductor home page http www mitsubishichips com When using any or all of the information conta...

Page 3: ... can take full advantage of the versatile performance ca pabilities of these microcomputers The CPU features and the functionality of each internal peripheral circuit are described in detail which we hope will prove useful for your circuit de sign For details about the M32R family software products and development support tools please refer to the user s manuals and related other documentation inc...

Page 4: ... bits after reset are indicated each in column At read read enabled read disabled read value invalid 0 Read always as 0 1 Read always as 1 At write Write enabled Write enable conditionally include some conditions at write Write disabled Written value invalid Abit 1 2 3 4 D0 D Bit name Function W R at reset H 04 0 Not assigned 0 1 Abit 0 1 3 2 Not implemented in the shaded portion Example of repres...

Page 5: ...N Function 1 6 1 1 7 Built in Debug Function 1 6 1 2 Block Diagram 1 7 1 3 Pin Function 1 10 1 4 Pin Layout 1 18 CHAPTER 2 CPU 2 1 CPU Registers 2 2 2 2 General purpose Registers 2 2 2 3 Control Registers 2 3 2 3 1 Processor Status Word Register PSW CR0 2 4 2 3 2 Condition Bit Register CBR CR1 2 5 2 3 3 Interrupt Stack Pointer SPI CR2 2 5 User Stack Pointer SPU CR3 2 5 2 3 4 Backup PC BPC CR6 2 5 ...

Page 6: ... ICU Vector Table 3 29 3 7 Note about Address Space 3 31 CHAPTER 4 EIT 4 1 Outline of EIT 4 2 4 2 EIT Event 4 3 4 2 1 Exception 4 3 4 2 2 Interrupt 4 3 4 2 3 Trap 4 3 4 3 EIT Processing Procedure 4 4 4 4 EIT Processing Mechanism 4 6 4 5 Acceptance of EIT Event 4 7 4 6 Saving and Restoring the PC and PSW 4 8 4 7 EIT Vector Entry 4 10 4 8 Exception Processing 4 11 4 8 1 Reserved Instruction Exceptio...

Page 7: ... 3 4 Interrupt Control Registers 5 10 5 4 ICU Vector Table 5 14 5 5 Description of Interrupt Operation 5 17 5 5 1 Acceptance of Internal Peripheral I O Interrupts 5 17 5 5 2 Processing of Internal Peripheral I O Interrupts by Handlers 5 20 5 6 Description of System Break Interrupt SBI Operation 5 22 5 6 1 Acceptance of SBI 5 22 5 6 2 SBI Processing by Handler 5 22 CHAPTER 6 INTERNAL MEMORY 6 1 Out...

Page 8: ...ication Example of Virtual Flash Emulation Mode 6 53 6 8 Connecting to A Serial Programmer 6 55 6 9 Precautions to Be Taken When Rewriting Flash Memory 6 57 CHAPTER 7 RESET 7 1 Outline of Reset 7 2 7 2 Reset Operation 7 2 7 2 1 Reset at Power on 7 2 7 2 2 Reset during Operation 7 2 7 2 3 Reset Vector Relocation during Flash Rewrite 7 2 7 3 Internal State Immediately after Reset Release 7 3 7 4 Thi...

Page 9: ... Registers 9 18 9 2 4 DMA Destination Address Registers 9 19 9 2 5 DMA Transfer Count Registers 9 20 9 2 6 DMA Interrupt Request Status Registers 9 21 9 2 7 DMA Interrupt Mask Registers 9 23 9 3 Functional Description of the DMAC 9 27 9 3 1 Cause of DMA Request 9 27 9 3 2 DMA Transfer Processing Procedure 9 31 9 3 3 Starting DMA 9 32 9 3 4 Channel Priority 9 32 9 3 5 Gaining and Releasing Control ...

Page 10: ...0 96 10 4 TIO Input Output related 16 bit Timer 10 100 10 4 1 Outline of TIO 10 100 10 4 2 Outline of Each Mode of TIO 10 102 10 4 3 TIO Related Register Map 10 105 10 4 4 TIO Control Registers 10 108 10 4 5 TIO Counter TIO0CT TIO9CT 10 119 10 4 6 TIO Reload 0 Measure Register TIO0RL0 TIO9RL0 10 120 10 4 7 TIO Reload 1 Registers TIO0RL1 TIO9RL1 10 121 10 4 8 TIO Enable Control Registers 10 122 10 ...

Page 11: ... Map 10 162 10 7 3 TID Control Prescaler Enable Registers 10 163 10 7 4 TID Counters TID0CT TID1CT TID2CT 10 166 10 7 5 TID Reload Registers TID0RL TID1RL TID2RL 10 167 10 7 6 Outline of Each Mode of TID 10 168 10 8 TOD Output related 16 bit Timer 10 173 10 8 1 Outline of TOD 10 173 10 8 2 Outline of Each Mode of TOD 10 175 10 8 3 TOD Related Register Map 10 177 10 8 4 TOD Control Registers TOD0CR...

Page 12: ... TOD Continuous Output Mode Without Correction Function 10 201 10 9 TOM Output related 16 bit Timer 10 203 10 9 1 Outline of TOM 10 203 10 9 2 Outline of Each Mode of TOM 10 205 10 9 3 TOM Related Register Map 10 207 10 9 4 TOM Control Registers 10 209 10 9 5 TOM Counters 10 210 10 9 6 TOM Reload 0 Registers 10 211 10 9 7 TOM Reload 1 Registers 10 212 10 9 8 TOM Enable Protect Registers 10 213 10 ...

Page 13: ...12 2 4 SIO Transmit Receive Mode Registers 12 18 12 2 5 SIO Transmit Buffer Registers 12 21 12 2 6 SIO Receive Buffer Registers 12 22 12 2 7 SIO Receive Control Registers 12 23 12 2 8 SIO Baud Rate Registers 12 26 12 3 Transmit Operation in CSIO Mode 12 28 12 3 1 Setting the CSIO Baud Rate 12 28 12 3 2 Initial Settings for CSIO Transmission 12 29 12 3 3 Starting CSIO Transmission 12 31 12 3 4 Succ...

Page 14: ... 8 Transmit DMA Transfer Request 12 51 12 6 9 Typical UART Transmit Operation 12 53 12 7 Receive Operation in UART Mode 12 55 12 7 1 Initial Settings for UART Reception 12 55 12 7 2 Starting UART Reception 12 57 12 7 3 Processing at End of UART Reception 12 57 12 7 4 Typical UART Receive Operation 12 59 12 8 Fixed Period Clock Output Function 12 61 12 9 Precautions on Using UART Mode 12 62 CHAPTER...

Page 15: ...ve Operation 13 65 13 6 3 Reading Out Received Data Frames 13 67 13 7 Transmitting Remote Frames 13 69 13 7 1 Remote Frame Transmit Procedure 13 69 13 7 2 Remote Frame Transmit Operation 13 71 13 7 3 Reading Out Received Data Frames when Set for Remote Frame Transmission 13 74 13 8 Receiving Remote Frames 13 76 13 8 1 Remote Frame Receive Procedure 13 76 13 8 2 Remote Frame Receive Operation 13 78...

Page 16: ... External Extension Memory 15 14 CHAPTER 16 WAIT CONTROLLER 16 1 Outline of the Wait Controller 16 2 16 2 Wait Controller Related Registers 16 4 16 2 1 Wait Cycles Control Register 16 5 16 3 Typical Operation of the Wait Controller 16 6 CHAPTER 17 RAM BACKUP MODE 17 1 Outline 17 2 17 2 Example of RAM Backup when Power is Down 17 2 17 2 1 Normal Operating State 17 3 17 2 2 RAM Backup State 17 4 17 ...

Page 17: ... 19 6 19 4 1 Outline of JTAG Operation 19 6 19 4 2 IR Path Sequence 19 8 19 4 3 DR Path Sequence 19 10 19 4 4 Examining and Setting Data Registers 19 12 19 5 Boundary Scan Description Language 19 14 19 6 Precautions about Board Design when Connecting JTAG 19 34 CHAPTER 20 POWER UP POWER SHUTDOWN SEQUENCE 20 1 Configuration of the Power Supply Circuit 20 2 20 2 Power On Sequence 20 3 20 2 1 Power O...

Page 18: ...ERISTICS 22 1 A D Conversion Characteristics 22 2 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1 1 Dimensional Outline Drawing Appendix 1 2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 32170 Instruction Processing Time Appendix 2 2 APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3 1 Precautions about Noise Appendix 3 2 Appendix 3 1 1 Reduction of Wiring Length Appendix 3 2 Appendix 3 1 2 Inser...

Page 19: ...CHAPTER 1 CHAPTER 1 OVERVIEW 1 1 Outline of the 32170 1 2 Block Diagram 1 3 Pin Function 1 4 Pin Layout ...

Page 20: ...oad and store instructions or register to register operation instructions compound instructions such as Load Address Update and Store Address Update also are executed in one cycle Instructions are entered into the execution stage in the order they are fetched but this does not always mean that the first instruction entered is executed first If the execution of a load or store instruction entered e...

Page 21: ...ted in one cycle so that when combined with high speed data transfer instructions such as Load Address Update and Store Address Update they enable the M32R to exhibit high data processing capability comparable to that of DSP 1 1 3 Built in Flash Memory and RAM The 32170 contains flash memory and RAM which can be accessed with no wait states allowing you to build a high speed embedded system The in...

Page 22: ...uced as desired thus materializing real time output control 2 Built in 10 channel DMA The 10 channel DMA is built in supporting data transfers between internal peripheral I Os or between internal peripheral I O and internal RAM Not only can DMA transfer requests be generated in software but can also be triggered by a signal generated by an internal peripheral I O e g A D converter MJT or serial I ...

Page 23: ... external device independently of the M32R The debugger can generate an RTD interrupt to notify that RTD based data transmission or reception is completed 6 Eight level interrupt controller The interrupt controller manages interrupt requests from each internal peripheral I O by resolving interrupt priority in eight levels including an interrupt disabled state Also it can accept external interrupt ...

Page 24: ...32170 contains CAN Specification V2 0B compliant CAN module thereby providing 16 message slots 1 1 7 Built in Debug Function The 32170 supports JTAG interface Boundary scan test can be performed using this JTAG interface OVERVIEW 1 1 Outline of the 32170 ...

Page 25: ...M32170F6 40KB M32170F4 32KB M32170F3 32KB Internal flash memory M32170F6 768KB M32170F4 512KB M32170F3 384KB M32R CPU core max 40MHz Multiplier accumulator 32 X 16 56 DMAC 10 channels Multijunction timer MJT 64 channels Serial I O 6 channels A D converter 10 bit resolution 16 channels x 2 Wait controller Interrupt controller 31 sources 8 levels Real time debugger RTD External bus interface Interna...

Page 26: ...s Control register 32 bits 5 registers Instruction set 16 bit and 32 bit instruction formats 83 distinct instructions and 9 addressing modes Built in multiplier accumulator 32 16 56 Table 1 2 2 Features of Internal Memory Functional Block Features RAM Capacity M32170F6 40 Kbytes M32170F4 M32170F3 32 Kbytes No wait access when operating with 40 MHz CPU clock By using RTD real time debugger the inte...

Page 27: ...onversion Can read out conversion results in 8 or 10 bits Serial I O 6 channel serial I O Can be set for clock synchronized serial I O or UART Capable of high speed data transfer at 2 Mbits per second when clock synchronized or 156 Kbits per second during UART Real time debugger Can rewrite or monitor the internal RAM independently of the CPU by command input from an external source Has its exclus...

Page 28: ...P137 TIN16 TIN23 34 Port 19 Port 17 Port 15 Port 14 Port 13 P124 P127 TCLK0 TCLK 3 4 Multi junction timer 45 P210 P217 TO37 TO44 P180 P187 TO29 TO36 P160 P167 TO21 TO28 P110 P117 TO0 TO7 P100 P107 TO8 TO15 P93 P97 TO16 TO20 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 P74 RTDTXD P75 RTDRXD P76 RTDACK P77 RTDCLK Real time debugger Port 7 P70 BCLK WR Port 7 P82 TXD0 P83 RXD0 P84 SCLKI0 SCL...

Page 29: ...5 P93 P97 TO16 TO20 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 P74 RTDTXD P75 RTDRXD P76 RTDACK P77 RTDCLK Real time debugger Port 7 P70 BCLK WR Port 7 P82 TXD0 P83 RXD0 P84 SCLKI0 SCLKO0 P85 TXD1 P86 RXD1 P87 SCLKI1 SCLKO1 Serial I O Port 8 16 AD1IN0 AD1IN15 A D converter P67 ADTRG AVCC0 AVCC1 AVSS0 AVSS1 Port 6 P61 P63 Port 6 AVREF0 AVREF1 VDD FVCC FP VCCE 7 P174 TXD2 P175 RXD2 P176 ...

Page 30: ...al input clock When using 10 MHz external input clock BCLK output 20 MHz Use this output when external operation needs to be synchronized OSC VCC Power supply Power supply for PLL circuit Connect OSC VCC to the power supply rail OSC VSS Ground Connect OSC VSS to ground VCNT PLL control Input This pin controls the PLL circuit Connect a resistor and capacitor to it For external circuits refer to Sec...

Page 31: ...rresponds to the lower address D8 D15 is valid ____ WAIT Wait Input When the M32R accesses an external device a low on this ____ WAIT input extends the wait cycle ____ HREQ Hold request Input This pin is used by an external device to request control of ____ the external bus A low on this HREQ input causes the M32R to enter a hold state ____ HACK Hold Output This signal is used to notify that the M...

Page 32: ... BRG output by halving it output or CSIO transmit receive When channel 1 is in CSIO mode clock input output This pin accepts as its input a transmit receive clock when external clock source is selected or outputs a transmit receive clock when internal clock source is selected SCLKI4 UART transmit Input output When channel 4 is in UART mode SCLKO4 receive clock This pin outputs a clock derived from...

Page 33: ...ut Input Serial data transmit receive clock input pin for the real time debugger RTDACK Acknowledge Output This pin outputs a low pulse synchronously with the beginning clock of the real time debugger s serial data output word The duration of this low pulse indicates the type of command data that the real time debugger has received Flash FP Flash Protect Input This mode pin has a function to prote...

Page 34: ...0 P77 Input output Input output Programmable input output port port 7 P82 P87 Input output Input output Programmable input output port port 8 P93 P97 Input output Input output Programmable input output port port 9 P100 Input output Input output Programmable input output port P107 port 10 P110 Input output Input output Programmable input output port P117 port 11 P124 Input output Input output Progr...

Page 35: ...n Name Signal Name Input Output Function DEBOG JDBI Debug interrupt Input Debug interrupt request input pin A low on this input request requests a debug interrupt JEVENT0 Event output Output Output synchronously with TRCLK When an event occurs JEVENT1 this output is driven high for a 1 TRCLK period TRCLK Trace clock Output Clock output pin for trace operation Trace data is output output synchronou...

Page 36: ... P133 TIN19 P132 TIN18 P131 TIN17 P130 TIN16 VSS VCCI P42 BHW BHE P127 TCLK3 P126 TCLK2 P125 TCLK1 P124 TCLK0 P107 TO15 P106 TO14 P105 TO13 P104 TO12 VSS VCCI P103 TO11 VSS VCCI P43 RD P44 CS0 P45 CS1 P14 DB12 P37 A22 P36 A21 P33 A18 P31 A16 P30 A15 P35 A20 P34 A19 P32 A17 VCCE P27 A30 P25 A28 P26 A29 P24 A27 P07 DB7 P02 DB2 P01 DB1 P00 DB0 P23 A26 P22 A25 P20 A23 P10 DB8 P11 DB9 VSS P15 DB13 P13 ...

Page 37: ...VSS 57 P14 DB12 97 P197 TIN33 137 VCCI 18 OSC VSS 58 P15 DB13 98 VCCI 138 VSS 19 XIN 59 P16 DB14 99 VSS 139 VCCE 20 XOUT 60 P17 DB15 100 P160 TO21 140 ___ P70 BCLK WR 21 OSC VCC 61 VREF0 101 P161 TO22 141 ____ P71 WAIT 22 VSS 62 AVCC0 102 P162 TO23 142 ____ P72 HREQ 23 VCNT 63 AD0IN0 103 P163 TO24 143 ____ P73 HACK 24 VSS 64 AD0IN1 104 P164 TO25 144 P74 RTDTXD 25 P30 A15 65 AD0IN2 105 P165 TO26 14...

Page 38: ...227 VREF1 168 P101 TO9 188 P105 TO13 208 P141 TIN9 228 AVCC1 169 P102 TO10 189 P106 TO14 209 P142 TIN10 229 AD1IN0 170 VDD 190 P107 TO15 210 P143 TIN11 230 AD1IN1 171 VCCI 191 P124 TCLK0 211 P144 TIN12 231 AD1IN2 172 VSS 192 P125 TCLK1 212 P145 TIN13 232 AD1IN3 173 P210 TO37 193 P126 TCLK2 213 P146 TIN14 233 AD1IN4 174 P211 TO38 194 P127 TCLK3 214 P147 TIN15 234 AD1IN5 175 P212 TO39 195 VCCI 215 P...

Page 39: ...N33 VCCI VSS P160 TO21 P161 TO22 P162 TO23 P163 TO24 P164 TO25 P165 TO26 P166 TO27 P167 TO28 P172 TIN24 P173 TIN25 P174 TXD2 P175 RXD2 P176 TXD3 P177 RXD3 VCCE VSS P82 TXD0 P87 SCLK1 P84 SCLK0 P85 TXD1 P86 RXD1 TRDATA 0 TRDATA 1 TRDATA 2 TRDATA 3 P200 TXD4 P201 RXD4 P202 TXD5 P203 RXD5 VCCI VSS P83 RXD0 VSS P61 P62 FVCC P64 SBI P65 SCLK4 P66 SCLK5 P63 VCCI VSS VCCE P67 ADTRG P71 WAIT P72 HREQ P73 ...

Page 40: ... F18 P100 TO8 J18 P110 TO0 A15 P124 TCLK0 C15 P125 TCLK1 F19 P117 TO7 J19 VSS A16 P104 TO12 C16 P105 TO13 F20 P116 TO6 J20 VCCE A17 JEVENT1 C17 JTDO G1 XIN K1 TRCLK A18 JEVENT0 C18 P213 TO40 G2 OSC VSS K2 P35 A20 A19 JTCK C19 P215 TO42 G3 VSS K3 P34 A19 A20 JTMS C20 P214 TO41 G4 P225 A12 K4 P33 A18 B1 AD1IN12 D1 _________ P44 CS0 G17 TRADATA5 K17 P97 TO20 B2 AD1IN11 D2 _____ P43 RD G18 P114 TO4 K1...

Page 41: ...RXD R18 ___ P64 SBI U14 P165 TO26 W14 P172 TIN24 M19 P76 RTDACK R19 P65 SCLK4 U15 P173 TIN25 W15 P176 TXD3 M20 P77 RTDCLK R20 P66 SCLK5 U16 P177 RXD3 W16 P82 TXD0 N1 P24 A27 T1 VCCE U17 P83 RXD0 W17 P86 RXD1 N2 P25 A28 T2 VSS U18 P203 RXD5 W18 TRDATA2 N3 P26 A29 T3 P10 DB8 U19 VCCI W19 N C N4 VSS T4 P07 DB7 U20 VSS W20 P201 RXD4 N17 P70 BCLK T17 FVCC V1 P15 DB13 Y1 N C N18 _____ P71 WAIT T18 VSS V...

Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...

Page 43: ...CHAPTER 2 CHAPTER 2 CPU 2 1 CPU Registers 2 2 General purpose Registers 2 3 Control Registers 2 4 Accumulator 2 5 Program Counter 2 6 Data Formats ...

Page 44: ... R14 is used as a link register and R15 is used as a stack pointer The link register is used to store the return address when executing a subroutine call instruction The stack pointer is switched between an interrupt stack pointer SPI and a user stack pointer SPU depending on the value of the Processor Status Word register PSW s stack mode SM bit 31 31 0 0 R8 R9 R10 R11 R12 R13 R14 Link register R...

Page 45: ...Dedicated MVTC and MVFC instructions are used to set and read these control registers Figure 2 3 1 Control Registers Control Registers CR0 CR1 CR2 CR3 0 31 PSW CBR SPI SPU Processor status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer BPC CR6 Backup PC CRn Notes 1 CRn n 0 3 6 denotes control register numbers 2 Dedicated MVTC and MVFC instructions are used to set a...

Page 46: ...ate is accepted 17 BIE Backup IE Holds the value of IE bit when EIT Indeterminate is accepted 23 BC Backup C Holds the value of C bit when EIT Indeterminate is accepted 24 SM Stack Mode 0 Interrupt stack pointer is used 0 1 User stack pointer is used 25 IE Interrupt Enable 0 No interrupt is accepted 0 1 Interrupt is accepted 31 C Condition bit Depending on instruction execution it indicates 0 whet...

Page 47: ... general purpose register R15 In this case whether R15 is used as SPI or as SPU depends on the PSW s Stack Mode SM bit 2 3 4 Backup PC BPC CR6 The Backup PC BPC is a register used to save the value of the Program Counter PC when an EIT occurs Bit 31 is fixed to 0 When an EIT occurs the value held in the PC immediately before the EIT occurred or the value of the next instruction is set in this regi...

Page 48: ... and MVFACMI instructions are used to read data from the accumulator The MVFACHI instruction reads data from the 32 high order bits bits 0 31 the MVFACLO instruction reads data from the 32 low order bits bits 32 63 and the MVFACHI instruction reads data from the 32 middle bits bits 16 47 CPU 2 4 Accumulator Note Bits 0 7 always show the sign extended value of bit 8 Writes to this bit field are ign...

Page 49: ...ntegers Values of signed integers are represented by 2 s complements Figure 2 6 1 Data Types CPU 2 6 Data Formats Signed byte 8 bit integer Unsigned byte 8 bit integer Signed halfword 16 bit integer Unsigned halfword 16 bit integer Signed word 32 bit integer Unsigned word 32 bit integer 0 MSB 0 MSB 0 MSB 0 MSB 0 MSB 0 MSB 7 LSB 7 LSB 15 LSB 15 LSB 31 LSB 31 LSB S S S S Sign bit ...

Page 50: ...The ST instruction stores the entire 32 bit data of the register the STH instruction stores the least significant 16 bit data and the STB instruction stores the least significant 8 bit data Figure 2 6 2 Data Formats in Register Rn 0 MSB 31 LSB When loading Byte Rn 0 MSB 31 LSB Halfword Rn 0 MSB 31 LSB Word Sign extended LDB instruction or zero extended LDUB instruction From memory LDB LDUB instruc...

Page 51: ... the LSB address bit 0 and word data must be located at word boundaries where two LSB address bits 00 If an attempt is made to access memory data across these halfword or word boundaries an address exception is generated Figure 2 6 3 Data Formats in Memory CPU 2 6 Data Formats Address Byte Halfword Word 0 address 1 address 2 address 3 address 0 31 Byte 7 8 15 16 23 24 MSB LSB MSB LSB Byte Byte Byt...

Page 52: ...23 H 45 H 67 MSB LSB LL LH HL HH H 67 H 45 H 23 H 01 MSB LSB B 0000001 D0 D7 MSB LSB B 0000001 D7 D0 Little Little LL LH HL HH Big Big HH HL LH LL Little Big HH HL LH LL Endian Bit Byte Data arrangement MPU name 7700 family M16C family Competition M32R family M16 family 7 0 31 24 15 8 23 16 0 7 24 31 8 15 16 23 Bit number 0 1 2 3 0 1 2 3 0 1 2 3 Address MSB LSB MSB LSB MSB LSB Ex 0x01234567 byte 6...

Page 53: ...est imm16 23 0 Rdest imm24 31 0 LD24 Rdest imm24 15 0 Rdest imm16 31 0 SETH Rdest imm16 00 8 15 00 00 Register to register transfer MV Rdest Rsrc Control register transfer MVFC Rdest CRsrc MVTC Rsrc CRdest Note For the MVTC instruction the condition bit C does not change unless CRdest is CR0 PSW Rsrc 31 0 Rdest 31 0 Rsrc 31 0 CRdest 31 0 MVTC Rsrc CRdest MV Rdest Rsrc ...

Page 54: ... LD24 Rsrc label LDB Rdest Rsrc label Rdest 31 0 0 1 2 3 Rdest label 00 00 FF FF Check the MSB 0 positive 1 negative 31 0 0 1 2 3 Rdest label 00 00 00 FF FF FF 31 0 0 1 2 3 Memory Register Check the MSB 0 positive 1 negative Unsigned 32 bits LD24 Rsrc label LD Rdest Rsrc Unsigned 16 bits LD24 Rsrc label LDUB Rdest Rsrc Unsigned 8 bits LD24 Rsrc label LDUH Rdest Rsrc Rdest 00 00 31 0 label 0 1 2 3 ...

Page 55: ...are different Figure 2 6 9 Difference in Data Arrangements Data in memory Data in register Word data 32 bits 0 1 2 3 D0 D31 HH HL LH LL D0 D31 HH HL LH LL Half word data 16 bits 0 1 2 3 D0 D31 H L D0 D15 H L Byte data 8 bits 0 1 2 3 D0 D31 D0 D7 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB R0 R15 R0 R15 R0 R15 CPU 2 6 Data Formats ...

Page 56: ...2 2 14 Ver 0 10 This is a blank page ...

Page 57: ...3 ADDRESS SPACE 3 1 Outline of Address Space 3 2 Operation Modes 3 3 Internal ROM Area and Extended External Area 3 4 Internal RAM Area and SFR Area 3 5 EIT Vector Entry 3 6 ICU Vector Table 3 7 Note about Address Space ...

Page 58: ...l RAM area and Spe cial Function Register SFR area an area containing a group of internal peripheral I O regis ters Of these the internal ROM and extended external areas are located differently depend ing on mode settings which will be described later 2 Boot program space A 1 Gbyte of address space from H 8000 0000 to H BFFF FFFF is the boot program space This space stores a program boot program w...

Page 59: ...00 0000 H 00FF FFFF H 007F FFFF H 0080 0000 SFR area 16 Kbytes H 0080 3FFF H 0080 4000 H 001F FFFF H 0020 0000 H 003F FFFF H 0040 0000 Internal ROM area 768 Kbytes Note 1 Extended external area 4 Mbytes Ghost area in units of 128 Kbytes 1 Gbyte 1 Gbyte 2 Gbytes Ghost area in units of 16 Mbytes Ghost area in 4 Mbytes Internal RAM area 40 Kbytes H 0080 DFFF H 8000 0000 H 8000 1FFF Ghost area in unit...

Page 60: ...H 0040 0000 Internal ROM area 512 Kbytes Note 1 Extended external area 4 Mbytes Ghost area in units of 128 Kbytes 1 Gbyte 1 Gbyte 2 Gbytes Ghost area in units of 16 Mbytes Ghost area in 4 Mbytes Internal RAM area 32 Kbytes H 0080 BFFF H 8000 0000 H 8000 1FFF Ghost area in units of 16 Mbytes Reserved area 8 Kbytes AAAA AAAA AAAA AAAA Reserved area 80 Kbytes H 0081 FFFF H 0082 0000 H 0080 C000 H 800...

Page 61: ...H 0040 0000 Internal ROM area 384 Kbytes Note 1 Extended external area 4 Mbytes Ghost area in units of 128 Kbytes 1 Gbyte 1 Gbyte 2 Gbytes Ghost area in units of 16 Mbytes Ghost area in 4 Mbytes Internal RAM area 32 Kbytes H 0080 BFFF H 8000 0000 H 8000 1FFF Ghost area in units of 16 Mbytes Reserved area 8 Kbytes AAAA AAAA AAAA AAAA Reserved area 80 Kbytes H 0081 FFFF H 0082 0000 H 0080 C000 H 800...

Page 62: ...rnal ROM and extended external areas are located differently depending on the 32170 s operation mode All other areas in address space are located the same way The address maps of internal ROM and extended external areas in each mode are shown below For flash rewrite mode FP VCC not listed in the above table refer to Section 6 5 Programming of Internal Flash Memory ADDRESS SPACE 3 2 Operation Modes...

Page 63: ...ytes Extended external area Extended external area Internal ROM area 512 Kbytes H 000F FFFF H 0010 0000 H 001F FFFF H 0020 0000 CS0 area 1 Mbyte Reserved area 512 Kbytes H 0000 0000 H 0005 FFFF H 0006 0000 H 003F FFFF Non CS0 area Single chip mode Processor mode CS1 area 2 Mbytes CS0 area 2 Mbytes CS1 area 2 Mbytes Extended external mode Internal ROM area 384 Kbytes Extended external area Extended...

Page 64: ...F32170F4 512 Kbytes H 0000 0000 H 0007 FFFF MF32170F3 384 Kbytes H 0000 0000 H 0005 FFFF 3 3 2 Extended External Area An extended external area is provided only when extended external mode or processor mode has been selected when setting the 32170 s operation mode For access to this extended external area the 32170 outputs the control signals necessary to access external devices ________ _______ T...

Page 65: ...3 4 1 Addresses at Which the 32170 s Internal ROM is Located Type Name Size Located address MF32170F6 40 Kbytes H 0080 4000 H 0080 DFFF MF32170F4 32 Kbytes H 0080 4000 H 0080 BFFF MF32170F3 3 4 2 Special Function Register SFR Area Addresses H 0080 0000 to H 0080 3FFFF are the Special Function Register SFR area This area has registers for internal peripheral I O located in it ADDRESS SPACE 3 4 Inte...

Page 66: ...a and Special Function Register SFR Area of the M32170F4 and M32170F3 H 0080 0000 H 0080 BFFF SFR area 16 Kbytes Internal RAM 32 Kbytes H 0080 3FFF H 0080 4000 Pseudo flash emulation areas separated in units of 8 Kbytes or 4 Kbytes can be allocated here For details refer to Section 6 7 ...

Page 67: ...d is transparent to the CPU 0 7 8 15 H 0080 0A00 0 address 1 address 0 7 8 15 Multijunction timer MJT Flash control H 0080 07E0 H 0080 07F2 H 0080 023E H 0080 02FE MJT TOD0 H 0080 078C H 0080 07DE MJT TID0 H 0080 0790 H 0080 078E Multijunction timer MJT Serial I O4 5 H 0080 0A26 H 0080 0A80 A D1 converter H 0080 0AEE MJT TOD1 MJT TOM0 H 0080 0BDE H 0080 0C8C H 0080 0CDE MJT TML1 H 0080 0FE0 H 0080...

Page 68: ...1 A D0 Scan Mode Register 0 AD0SCM0 A D0 Scan Mode Register 1 AD0SCM1 A D0 Successive Approximation Register AD0SAR A D0 Comparate Data Register AD0CMP H 0080 008C H 0080 0092 H 0080 0094 10 bit A D0 Data Register 0 AD0DT0 10 bit A D0 Data Register 1 AD0DT1 10 bit A D0 Data Register 2 AD0DT2 10 bit A D0 Data Register 3 AD0DT3 10 bit A D0 Data Register 4 AD0DT4 10 bit A D0 Data Register 5 AD0DT5 10...

Page 69: ...ter SI03SEL SIO0 Transmit Control Register S0TCNT SIO0 Transmit Receive Mode Register S0MOD SIO0 Receive Control Register S0RCNT H 0080 0124 SIO1 Baud Rate Register S1BAUR SIO1 Transmit Buffer Register S1TXB SIO1 Receive Buffer Register S1RXB SIO1 Transmit Control Register S1TCNT SIO0 Transmit Receive Mode Register S1MOD SIO1 Receive Control Register S1RCNT SIO2 Baud Rate Register S2BAUR SIO2 Tran...

Page 70: ...TINIR2 TIN Interrupt Control Register 4 TINIR4 TIN Interrupt Control Register 6 TINIR6 TIN Interrupt Control Register 1 TINIR1 TIN Interrupt Control Register 3 TINIR3 TIN Interrupt Control Register 5 TINIR5 TOP0 Counter TOP0CT TOP0 Reload Register TOP0RL TOP0 Correction Register TOP0CC TOP1 Counter TOP1CT Address H 0080 0252 H 0080 0254 H 0080 0260 H 0080 0262 H 0080 0264 H 0080 0266 TOP1 Reload R...

Page 71: ...OP9CT TOP9 Reload Register TOP9RL TOP9 Correction Register TOP9CC TOP10 Counter TOP10CT TOP10 Reload Register TOP10RL TOP10 Correction Register TOP10CC H 0080 02E0 H 0080 02E2 H 0080 02E4 H 0080 02E6 H 0080 02E8 H 0080 02EA TOP8 10 Control Register TOP810CR TOP0 10 External Enable Register TOPEEN TOP0 10 Enable Protect Register TOPPRO TOP0 10 Count Enable Register TOPCEN H 0080 02FA H 0080 02FC H ...

Page 72: ...H 0080 0350 H 0080 0352 H 0080 0354 H 0080 0356 TIO6 Counter TIO6CT TIO6 Reload 1 Register TIO6RL1 TIO6 Reload 0 Measure Register TIO6RL0 TIO6 Control Register TIO6CR TIO7 Control Register TIO7CR H 0080 0360 H 0080 0362 H 0080 0364 H 0080 0366 H 0080 0368 H 0080 036A H 0080 0370 H 0080 0372 H 0080 0374 H 0080 0376 TIO7 Counter TIO7CT TIO7 Reload 1 Register TIO7RL1 TIO7 Reload 0 Measure Register TI...

Page 73: ...0MR0H TML0 Control Register TML0CR H 0080 03FE TML0 Measure 0 Register Low TML0MR0L DMA0 4 Interrupt Mask Register DM04ITMK DMA0 Channel Control Register DM0CNT DMA0 Transfer Count Register DM0TCT DMA0 Source Address Register DM0SA DMA0 Destination Address Register DM0DA DMA1 Channel Control Register DM1CNT DMA1 Transfer Count Register DM1TCT DMA1 Source Address Register DM1SA DMA1 Destination Add...

Page 74: ...nation Address Register DM7DA DMA8 Channel Control Register DM8CNT DMA8 Transfer Count Register DM8TCT DMA8 Source Address Register DM8SA DMA8 Destination Address Register DM8DA DMA9 Channel Control Register DM9CNT DMA9 Transfer Count Register DM9TCT DMA9 Source Address Register DM9SA DMA9 Destination Address Register DM9DA DMA4 Software Request Generation Register DM4SRI DMA5 Software Request Gen...

Page 75: ...egister P16MOD P17 Operation Mode Register P17MOD H 0080 078C TID0 Counter TID0CT TID0 Reload Register TID0RL H 0080 078E H 0080 0790 TOD0_0 Counter TOD00CT TOD0_0 Reload 1 Register TOD00RL1 TOD0_0 Reload 0 Register TOD00RL0 TOD0_1 Counter TOD01CT TOD0_1 Reload 1 Register TOD01RL1 TOD0_0 Reload 0 Register TOD01RL0 TOD0_2 Counter TOD02CT TOD0_2 Reload 1 Register TOD02RL1 H 0080 0794 H 0080 0792 H 0...

Page 76: ...OD06RL1 TOD0_6 Reload 0 Register TOD06RL0 TOD0_7 Counter TOD07CT H 0080 07B0 H 0080 07B4 H 0080 07B8 H 0080 07B6 H 0080 07BC H 0080 07BA H 0080 07BE H 0080 07B2 H 0080 07C0 H 0080 07C4 H 0080 07C8 H 0080 07C6 H 0080 07C2 Pseudo flash L Bank Register 0 FELBANK0 H 0080 07EA H 0080 0A00 H 0080 0A02 H 0080 0A10 H 0080 0A12 H 0080 0A14 H 0080 0A16 H 0080 0A20 H 0080 0A22 H 0080 0A24 Pseudo flash L Bank...

Page 77: ...0 0AEA H 0080 0AEC H 0080 0AEE H 0080 0B8C H 0080 0B8E H 0080 0B90 TID1 Reload Register TID1RL TOD1_0 Counter TOD10CT A D1 Single Mode Register 0 AD1SIM0 A D1 Single Mode Register 1 AD1SIM1 A D1 Scan Mode Register 0 AD1SCM0 A D1 Scan Mode Register 1 AD1SCM1 10 bit A D1 Data Register 0 AD1DT0 10 bit A D1 Data Register 4 AD1DT4 10 bit A D1 Data Register 8 AD1DT8 10 bit A D1 Data Register 11 AD1DT11 ...

Page 78: ...er TOD12RL0 TOD1_3 Reload 0 Register TOD13RL0 TOD1_4 Reload 0 Register TOD14RL0 TOD1_5 Reload 1 Register TOD15RL1 TOD1_5 Reload 0 Register TOD15RL0 TOD1_6 Counter TOD16CT TOD1_6 Reload 1 Register TOD16RL1 H 0080 0BD2 H 0080 0BD8 H 0080 0BDE TOD1 Interrupt Status Register TOD1IST F F Protect Register 3 FFP3 F F Data Register 3 FFD3 TOD1 Enable Protect Register TOD1PRO TOD1 Count Enable Register TOD...

Page 79: ...ad 0 Register TOM05RL0 TOM0_6 Reload 1 Register TOM06RL1 TOM0_6 Reload 0 Register TOM06RL0 TOM0_7 Counter TOM07CT TOM0_7 Reload 1 Register TOM07RL1 H 0080 0CDA TOM0 Interrupt Status Register TOM0IST F F Protect Register 4 FFP4 F F Data Register 4 FFD4 TOM0 Count Enable Register TOM0CEN TOM0 Enable Protect Register TOM0PRO TML1 Measure 2 Register Low TML1MR2L H 0080 0CAC H 0080 0CCE H 0080 0FF4 TOM...

Page 80: ... C0MSL7CNT CAN0 Message Slot 9 Control Register C0MSL9CNT CAN0 Message Slot 11 Control Register C0MSL11CNT CAN0 Message Slot 13 Control Register C0MSL13CNT CAN0 Message Slot 15 Control Register C0MSL15CNT CAN0 Message Slot 6 Control Register C0MSL6CNT CAN0 Message Slot 8 Control Register C0MSL8CNT CAN0 Message Slot 10 Control Register C0MSL10CNT CAN0 Message Slot 12 Control Register C0MSL12CNT CAN...

Page 81: ...essage Slot 2 Data 5 C0MSL2DT5 CAN0 Message Slot 2 Data 3 C0MSL2DT3 CAN0 Message Slot 2 Data 1 C0MSL2DT1 CAN0 Message Slot 2 Data Length Register C0MSL2DLC CAN0 Message Slot 2 Extended ID1 C0MSL2EID1 CAN0 Message Slot 2 Standard ID1 C0MSL2SID1 CAN0 Message Slot 1 Data 7 C0MSL1DT7 H 0080 1130 H 0080 1132 H 0080 1136 H 0080 1138 H 0080 113E H 0080 113C H 0080 1134 H 0080 113A CAN0 Message Slot 3 Dat...

Page 82: ...080 118E H 0080 1192 H 0080 1194 H 0080 119A H 0080 1198 H 0080 1190 H 0080 1196 H 0080 119C H 0080 119E CAN0 Message Slot 8 Data 6 C0MSL8DT6 CAN0 Message Slot 8 Time Stamp C0MSL8TSP CAN0 Message Slot 8 Data 7 C0MSL8DT7 CAN0 Message Slot 8 Data 4 C0MSL8DT4 CAN0 Message Slot 8 Data 2 C0MSL8DT2 CAN0 Message Slot 8 Data 0 C0MSL8DT0 CAN0 Message Slot 8 Extended ID2 C0MSL8EID2 CAN0 Message Slot 8 Exten...

Page 83: ...0MSL13SID0 CAN0 Message Slot 13 Extended ID1 C0MSL13EID1 CAN0 Message Slot 13 Standard ID1 C0MSL13SID1 H 0080 11D6 H 0080 11D8 H 0080 11DA H 0080 11DE H 0080 11E0 H 0080 11E6 H 0080 11E4 H 0080 11DC H 0080 11E2 H 0080 11D4 H 0080 11E8 H 0080 11EA H 0080 11EE H 0080 11F0 H 0080 11F6 H 0080 11F4 H 0080 11EC H 0080 11F2 H 0080 11F8 H 0080 11FA H 0080 11FE H 0080 3FFE H 0080 11FC CAN0 Message Slot 14 ...

Page 84: ...he EI vector entry is at H 0080 4000 H 0000 0040 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE Address Exception EI External Interrupt Note H 0000 0044 H 0000 0048 H 0000 004C H 0000 0050 H 0000 0054 H 0000 0058 H 0000 005C H 0000 0060 H 0000 0064 H 0000 0068 H 0000 006C H 0000 0070 H 0000 0074 H 0000 0078 H 0000 007C H 0000 0080 RI Reset ...

Page 85: ... 7 Handler Start Address A16 A31 MJT Input Interrupt 3 Handler Start Address A0 A15 MJT Input Interrupt 3 Handler Start Address A16 A31 MJT Input Interrupt 2 Handler Start Address A0 A15 MJT Input Interrupt 2 Handler Start Address A16 A31 MJT Input Interrupt 1 Handler Start Address A0 A15 MJT Input Interrupt 1 Handler Start Address A16 A31 MJT Input Interrupt 0 Handler Start Address A0 A15 MJT Inp...

Page 86: ...ss A0 A15 SIO2 3 Transmit Receive Interrupt Handler Start Address A16 A31 H 0000 00F0 H 0000 00F2 RTD Interrupt Handler Start Address A0 A15 RTD Interrupt Handler Start Address A16 A31 H 0000 00F4 H 0000 00F6 TID1 Output Interrupt Handler Start Address A0 A15 TID1 Output Interrupt Handler Start Address A16 A31 H 0000 00F8 H 0000 00FA TOD1 TOM0 Output Interrupt Handler Start Address A0 A15 TOD1 TOM...

Page 87: ...2170F6 up to three blocks for the M32170F4 and M32170F3 into internal flash memory areas divided in 8 Kbytes L banks Similarly this function allows the internal RAM to be mapped in blocks of 4 Kbytes for the M32170F6 up to two blocks starting from the RAM address H 0080 C000 for the M32170F4 and M32170F3 up to two blocks starting from the RAM address H 0080 A000 into internal flash memory areas di...

Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...

Page 89: ...Processing Procedure 4 4 EIT Processing Mechanism 4 5 Acceptance of EIT Events 4 6 Saving and Restoring the PC and PSW 4 7 EIT Vector Entry 4 8 Exception Processing 4 9 Interrupt Processing 4 10 Trap Processing 4 11 EIT Priority Levels 4 12 Example of EIT Processing ...

Page 90: ...Exception AE and Reserved Instruction Exception RIE 2 Interrupt This is an event generated irrespective of the context being executed It is generated in hardware by a signal from an external source In the M32R E this type of event includes External Interrupt EI System Break Interrupt SBI and Reset Interrupt RI 3 Trap This refers to a software interrupt generated by executing a TRAP instruction Thi...

Page 91: ...ak Interrupt SBI is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer This interrupt can only be used in cases when after interrupt processing control will not return to the program that was being executed when the interrupt occurred 3 External Interrupt EI External Interrupt EI is requested from internal peripheral I ...

Page 92: ... for SBI RTE instruc tion Instruction C Instruction D Program suspended EIT request accepted Instruction processing canceled type RIE AE Instruction processing completed type EI TRAP Program execution restarted EIT request generated Hardware preprocessing BPC B PSW and general purpose registers saved to stack Branch instruc tion General purpose registers B PSW and BPC restored from stack SBI Syste...

Page 93: ...egister the PSW register including the BPSW field and the general purpose registers to be used in the EIT handler are saved to the stack by the EIT handler you write Remember that these registers must be saved to the stack in a program by the user When processing by the EIT handler is completed restore the saved registers from the stack and finally execute the RTE instruction Control is thereby re...

Page 94: ...for the PC and PSW BPC register and the BPSW field of the PSW register The M32R E s internal EIT processing mechanism is shown below Figure 4 4 1 The M32R E s EIT Processing Mechanism Interrupt controller ICU SBI EI Internal peripheral I O RESET RI AE RIE TRAP IE flag PSW M32R CPU core SBI Low High Priority SBI EI RI M32R E PSW register PSW BPSW BPC register PC register EIT 4 4 EIT Processing Mech...

Page 95: ...ception RIE canceled type execution which generated RIE Address Exception AE Instruction processing During instruction PC value of the instruction canceled type execution which generated AE Reset Interrupt RI Instruction processing Each machine cycle Indeterminate value aborted type System Break Instruction processing Break in instructions PC value of the next instruction Interrupt SBI completed t...

Page 96: ...PC register BPC PC Set the vector address in the PC register Branches to the EIT vector and executes the branch instruction BRA instruction written in it thereby transferring control to the user created EIT handler 2 Hardware postprocessing when the RTE instruction is executed Restore the SM IE and C bits of the PSW register from their backup bits SM BSM IE BIE C BC Restore the value of the PC reg...

Page 97: ... PC Set vector address in PC PC Vector address Restore PC value from BPC The value of BPC after execution of the RTE instruction is indeterminate 2 1 Restore BSM BIE and BC bits from backup bits SM IE C The values of BSM BIE and BC bits after execution of the RTE instruction are indeterminate BSM BIE BC 16 17 23 24 25 31 LSB 15 8 7 0 MSB SM IE C BC BSM BIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 98: ...f the instruction that generated RIE Trap TRAP0 H 0000 0040 Indeterminate 0 PC of TRAP instruction 4 TRAP1 H 0000 0044 Indeterminate 0 PC of TRAP instruction 4 TRAP2 H 0000 0048 Indeterminate 0 PC of TRAP instruction 4 TRAP3 H 0000 004C Indeterminate 0 PC of TRAP instruction 4 TRAP4 H 0000 0050 Indeterminate 0 PC of TRAP instruction 4 TRAP5 H 0000 0054 Indeterminate 0 PC of TRAP instruction 4 TRAP...

Page 99: ...ting SM IE and C bits The SM IE and C bits of the PSW register are updated as shown below SM Unchanged BIE 0 BC 0 3 Saving PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register For example if the instruction that generated the reserved instruction exception is at address 4 the value 4 is set in the BPC register Similarly if the instruction ...

Page 100: ...p to the start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler At the end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execute the RTE i...

Page 101: ...M IE and C bits of the PSW register are saved to their backup bits the BSM BIE and BC bits BSM SM BIE IE BC C 2 Updating SM IE and C bits The SM IE and C bits of the PSW register are updated as shown below SM Unchanged IE 0 C 0 3 Saving PC The PC value of the instruction that generated the address exception is set in the BPC register For example if the instruction that generated the address except...

Page 102: ...he start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler At the end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execute the RTE instruc...

Page 103: ...SM BIE and BC bits are indeterminate SM 0 IE 0 C 0 2 Branching to the EIT vector entry Control branches to the address H 0000 0000 in the user space However when operating in boot mode control goes to the beginning of the boot ROM address H 8000 0000 For details refer to Section 6 5 Programming of Internal Flash Memory 3 Jumping from the EIT vector entry to the user program The M32R E executes the...

Page 104: ...em break interrupt occurred Occurrence Conditions _______ A system break interrupt is accepted by a falling edge on SBI input pin The system break interrupt cannot be masked by the PSW register IE bit In no case will a system break interrupt be activated immediately after executing a 16 bit instruction that starts from a word boundary For 16 bit branch instructions however the interrupt may be acc...

Page 105: ... 0000 0010 in the user space This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at address H 0000 0010 of the EIT vector entry by the user to jump to the start address of the user created handler The system break interrupt can only be used when some fatal event ...

Page 106: ...fied to the M32R CPU by the interrupt controller The M32R E checks these interrupt requests at a break in instructions residing on word boundaries and when an interrupt request is detected and the PSW register IE flag 1 accepts it as an external interrupt In no case will an external interrupt be activated immediately after executing a 16 bit instruction that starts from a word boundary For 16 bit ...

Page 107: ...r to Section 6 5 Writing to Internal Flash Memory This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at address H 0000 0080 of the EIT vector entry by the user to jump to the start address of the user created handler At the beginning of the EIT handler you creat...

Page 108: ...AP instruction 4 is set in the BPC register For example if the TRAP instruction is located at address 4 the value H 08 is set in the BPC register Similarly if the instruction is located at address 6 the value H 0A is set in the BPC register In this case the value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary BPC 30 0 or not on a word boundary BPC 30 1...

Page 109: ...user to jump to the start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler At the end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execut...

Page 110: ...pt Controller Priority EIT Event Type of Processing Values Set in BPC Register 1 Highest Reset Interrupt RI Instruction processing Indeterminate aborted type Address Exception AE Instruction processing PC of the instruction that canceled type generated AE 2 Reserved Instruction Instruction processing PC of the instruction that Exception RIE canceled type generated AE Trap TRAP Instruction processi...

Page 111: ...EI Occurs Simultaneously RTE instruction IE 0 IE 1 BPC register Return address A IE 1 RIE AE SBI EI or TRAP occurrs Singly Return address A If IE 0 no events but reset and SBI are accepted EIT handler RIE AE or TRAP is accepted first BPC register Return address A RIE AE or TRAP and EI occurs simultaneously EI is accepted next BPC register Return address A RTE instruction IE 0 IE 1 IE 1 Return addr...

Page 112: ...ave general purpose registers to stack Processing by EIT handler Restore general purpose registers Restore PSW Restore BPC EIT event occurs SBI System Break Interrupt processing Program terminated or system reset Any event other than SBI PC BPC PSW B PSW Hardware preprocessing Hardware postprocessing B PSW PSW BPC PC AA AA AAA AA EIT 4 12 Example of EIT Processing ...

Page 113: ...R ICU 5 1 Outline of the Interrupt Controller ICU 5 2 Interrupt Sources of Internal Peripheral I Os 5 3 ICU Related Registers 5 4 ICU Vector Table 5 5 Description of Interrupt Operation 5 6 Description of System Break Interrupt SBI Operation ...

Page 114: ... interrupt status register provided for internal peripheral I Os On the other hand the system break interrupt SBI is recognized when a low going transition _______ occurs on the SBI signal input pin This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer so that it is always accepted irrespective of the PSW ...

Page 115: ...ed ILEVEL Priority resolution by interrupt priority levels set System Break Interrupt request generated SBI EI SBI Interrupt controller Interrupt Control Register SBI Control Register SBICR SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Peripheral circuits Edge recognized Interrupt control circuit Level recognized Interrupt request Interrupt request Interrupt request To the CPU core Edge recognized Edge rec...

Page 116: ...transmit receive 5 Level recognized error interrupt Note ICU type of input source Edge recognized Interrupt requests are generated on a falling edge of the interrupt signal applied to the ICU Level recognized Interrupt requests are generated when the interrupt signal applied to the ICU is held low For these level recognized interrupts the ICU s Interrupt Control Register IRQ bit cannot be set or c...

Page 117: ...ized MJT output interrupt 0 MJT output interrupt group 0 TIO0 TIO3 output 4 Level recognized MJT input interrupt 4 MJT input interrupt group 4 TIN3 TIN6 input 4 Level recognized MJT input interrupt 3 MJT input interrupt group 3 TIN20 TIN23 input 4 Level recognized MJT input interrupt 2 MJT input interrupt group 2 TIN12 TIN19 input 8 Level recognized MJT input interrupt 1 MJT input interrupt group ...

Page 118: ...ister IMJTOCR6 MJT Output Interrupt Control Register IMJTOCR1 MJT Output Interrupt Control Register 3 IMJTOCR3 MJT Output Interrupt Control Register5 IMJTOCR5 MJT Output Interrupt Control Register7 IMJTOCR7 MJT Input Interrupt Control Register 0 IMJTICR0 MJT Input Interrupt Control Register 1 IMJTICR1 MJT Input Interrupt Control Register 2 IMJTICR2 MJT Input Interrupt Control Register 3 IMJTICR3 M...

Page 119: ...ow order bits of ICU vector table address for the accepted interrupt source is stored in this IVECT register The EIT handler reads out the content of the IVECT register by the LDH instruction to acquire the ICU vector table address When the IVECT register is read out operations 1 to 4 below are automatically performed in hardware 1 The accepted new IMASK NEW_IMASK is set in the IMASK register 2 Th...

Page 120: ...n hardware 1 The interrupt request EI to the CPU core is cleared 2 The ICU s internal sequencer is activated to start internal processing interrupt priority resolution Note that the Interrupt Mask Register IMASK can only be read out by the EIT handler PSW register IE bit being disabled When reset H 07 D Bit Name Function R W 0 4 No functions assigned 0 5 7 IMASK Interrupt mask 000 Maskable interru...

Page 121: ...an SBI occurs the SBI Control Register s SBIREQ SBI request bit is set to 1 The SBIREQ bit cannot be set in software To clear the SBIREQ bit after being set perform the operation described below Be careful not to clear this bit when no SBI request has been generated Write a 1 and then a 0 to SBIREQ When reset H 00 D Bit Name Function R W 0 6 No functions assigned 0 7 SBI REQ SBI request 0 SBI is n...

Page 122: ...006D SIO0 Receive Interrupt Control Register ISIO0RXCR Address H 0080 006E SIO1 Transmit Interrupt Control Register ISIO1TXCR Address H 0080 006F SIO1 Receive Interrupt Control Register ISIO1RXCR Address H 0080 0070 DMA0 4 Interrupt Control Register IDMA04CR Address H 0080 0071 MJT Output Interrupt Control Register 0 IMJTOCR0 Address H 0080 0072 MJT Output Interrupt Control Register 1 IMJTOCR1 Add...

Page 123: ...IREQ bit is cleared in software at the same time it is set by an interrupt request generated clearing in software has priority Also if the IREQ bit is cleared by reading out the IVECT register at the same time it is set by an interrupt request generated clearing by a read of IVECT has priority When reset H 07 D Bit Name Function R W 0 2 No functions assigned 0 8 10 3 IREQ Interrupt request 0 Inter...

Page 124: ...5 3 ICU Related Registers Interrupt priority resolving circuit Interrupt request from each peripheral function Interrupt enabled ILEVEL Levels 0 7 D3 11 Data bus D5 7 13 15 3 F F set set clear IREQ D3 11 D5 7 13 15 RD 3 IREQ Group interrupt Interrupt priority resolving circuit Group Interrupt request from each peripheral function Interrupt enabled ILEVEL Levels 0 7 Data bus Read only circuit ...

Page 125: ...determine whether to forward an EI request to the CPU or keep it pending The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted Table 5 3 1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 ILEVEL 000 Accepted when IMASK is 1 7 1 ILEVEL 001 Accepted when IMASK is 2 7 2 ILEVEL 010...

Page 126: ...tput Interrupt 1 H 0000 00C0 H 0000 00C3 MJT Output Interrupt 0 H 0000 00C4 H 0000 00C7 DMA0 4 Interrupt H 0000 00C8 H 0000 00CB SIO1 Receive Interruptt H 0000 00CC H 0000 00CF SIO1 Transmit Interruptt H 0000 00D0 H 0000 00D3 SIO0 Receive Interruptt H 0000 00D4 H 0000 00D7 SIO0 Transmit Interruptt H 0000 00D8 H 0000 00DB A D0 Converter Interruptt H 0000 00DC H 0000 00DF TID0 Output Interruptt H 00...

Page 127: ...00 00C4 H 0000 00C6 MJT Output Interrupt 7 Handler Start Address A0 A15 MJT Output Interrupt 7 Handler Start Address A16 A31 MJT Output Interrupt 6 Handler Start Address A0 A15 MJT Output Interrupt 6 Handler Start Address A16 A31 MJT Output Interrupt 5 Handler Start Address A0 A15 MJT Output Interrupt 5 Handler Start Address A16 A31 MJT Output Interrupt 4 Handler Start Address A0 A15 MJT Output In...

Page 128: ...art Address A16 A31 DMA5 9 Interrupt Handler Start Address A0 A15 DMA5 9 Interrupt Handler Start Address A16 A31 SIO2 3 Transmit Receive Interrupt Handler Start Address A0 A15 SIO2 3 Transmit Receive Interrupt Handler Start Address A16 A31 H 0000 00F0 H 0000 00F2 RTD Interrupt Handler Start Address A0 A15 RTD Interrupt Handler Start Address A16 A31 H 0000 00F4 H 0000 00F6 TID1 Input Interrupt Hand...

Page 129: ...quest which has the highest priority If the interrupt requests have the same LEVEL value they are resolved according to the hardware fixed priority The interrupt request thus selected has its ILEVEL value compared with IMASK value and if its priority is higher than the IMASK value the interrupt controller sends an EI request to the CPU Interrupt requests may be masked by setting the Interrupt Mask...

Page 130: ... DMA0 4 Interrupt H 0000 00C8 H 0000 00CB Level recognized SIO1 Receive Interrupt H 0000 00CC H 0000 00CF Edge recognized SIO1 Transmit Interrupt H 0000 00D0 H 0000 00D3 Edge recognized SIO0 Receive Interrupt H 0000 00D4 H 0000 00D7 Edge recognized SIO0 Transmit Interrupt H 0000 00D8 H 0000 00DB Edge recognized A D0 Converter Interrupt H 0000 00DC H 0000 00DF Edge recognized TID0 Output Interrupt ...

Page 131: ... IMASK is 1 7 1 ILEVEL 001 Accepted when IMASK is 2 7 2 ILEVEL 010 Accepted when IMASK is 3 7 3 ILEVEL 011 Accepted when IMASK is 4 7 4 ILEVEL 100 Accepted when IMASK is 5 7 5 ILEVEL 101 Accepted when IMASK is 6 7 6 ILEVEL 110 Accepted when IMASK is 7 7 ILEVEL 111 Not accepted interrupts disabled INTERRUPT CONTROLLER ICU 5 5 Description of Interrupt Operation ...

Page 132: ...ared in the case of level recognized interrupt sources however The IVECT register has set in it the 16 low order bits of ICU vector table address for the accepted interrupt source Read the IVECT register using a signed halfword load instruction LDH instruction and then the content of the ICU interrupt vector table indicated by the read address Make sure the ICU vector table has the start addresses...

Page 133: ...e BPC to stack Save PSW to stack Save general purpose register to stack Restore BPC Restore PSW Restore general purpose register Read Interrupt Mask Register IMASK and save it to stack IMASK H 0080 0000 PSW register IE bit 1 PSW register IE bit 0 Restore Interrupt Mask Register IMASK 1 2 3 4 6 7 8 5 9 10 10 1 8 5 Processing of EI by interrupt handler When enabling multiple interrupts ICU vector ta...

Page 134: ...d 5 6 2 SBI Processing by Handler When the system break interrupt generated has been serviced always be sure to terminate or reset the system without returning to the program that was being executed when the interrupt occurred Figure 5 6 1 Typical SBI Operation H 0000 0010 BRA instruction SBI System Break Interrupt handler SBI System Break Interrupt vector entry Program being executed SBI generate...

Page 135: ...ernal RAM 6 3 Internal Flash Memory 6 4 Registers Associated with the Internal Flash Memory 6 5 Programming of the Internal Flash Memory 6 6 Boot ROM 6 7 Virtual Flash Emulation Function 6 8 Connecting to A Serial Programmer 6 9 Precautions to Be Taken When Rewriting Flash Memory ...

Page 136: ... can be read monitored or written to any area of the internal RAM via serial communication from external devices independently of the CPU Refer to Chapter 14 Real Time Debugger 6 3 Internal Flash Memory Specifications of the 32170 s internal flash memory are shown below Table 6 3 1 Specifications of the Internal Flash Memory Item Specification Capacity M32170F6 768 Kbytes M32170F4 512Kbytes M32170...

Page 137: ...80 07EA H 0080 07EC H 0080 07EE H 0080 07F0 H 0080 07F2 Blank addresses are reserved for future use NOTE Note The M32170F4 and M32170F3 do not have the FELBANK3 register Flash Mode Register FMOD Flash Controle Register 1 FCNT1 Flash Controle Register 3 FCNT3 Flash Status Register 1 FSTAT1 Flash Controle Register 2 FCNT2 Flash Controle Register 4 FCNT4 Virtual Flash L Bank Register 0 FELBANK0 Virtu...

Page 138: ...h Mode Register FMOD is a read only status register with its FPMOD bit indicating the status of the FP Flash Protect pin Write to the flash memory is enabled only when FPMOD 1 Writing to the flash memory when FPMOD 0 has no effect 6 4 1 Flash Mode Register Flash Mode Register FMOD Address H 0080 07E0 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory ...

Page 139: ...ory use these two status registers FSTAT1 FSTAT2 to control the program erase operations Flash Status Register 1 FSTAT1 Address H 0080 07E1 D8 9 10 11 12 13 14 D15 FSTAT When reset H 01 D Bit Name Function R W 8 14 No functions assigned 0 15 FSTAT 0 Busy Ready Busy status 1 Ready The Flash Status Register 1 FSTAT1 is a read only status register used to know the execution status of whether the flas...

Page 140: ...ion is terminated when programming or erasing the flash memory When FBUSY 0 it means the program or erase operation is being executed when FBUSY 1 the operation is terminated 2 ERASE Auto Erase operating condition bit D10 The ERASE bit is used to determine whether execution of the flash memory erase operation has resulted in an error When ERASE 0 it means the erase operation terminated normally wh...

Page 141: ...ram operation terminated normally when WRERR2 1 the operation terminated in an error The condition under which WRERR2 is set to 1 is when the flash memory could not be written to by repeating the write operation a specified number of times Note This status register is included in the internal flash memory itself and can be read out by writing the Read Status Command H 7070 to any address of the fl...

Page 142: ...rnal flash memory 1 FENTRY Flash Mode Entry bit D3 The FENTRY bit controls entry to flash E W enable mode Flash E W enable mode can be entered only when FENTRY 1 To set the FENTRY bit to 1 write a 0 and then a 1 to the FENTRY bit in succession while the FP pin high The FENTRY bit is cleared in the following cases When the device is reset When a 0 is written to the FENTRY bit When the FP pin change...

Page 143: ...ion to be controlled using interrupts Table 6 4 1 Changes of EI Vector Entry by FENTRY FENTRY EI Vector Entry Address 0 Flash memory area H 0000 0080 1 Internal RAM area H 0080 4000 2 FEMMOD Virtual Flash Emulation Mode bit D7 The FEMMOD bit controls entry to Virtual flash emulation mode Virtual flash emulation mode is entered by setting the FEMMOD bit to 1 while the FENTRY bit 0 For details refer...

Page 144: ...lock bit to disable erasing or programming of the flash memory The flash memory protection becomes invalid unlocked by setting the FPROT bit to 1 so that any blocks protected by the lock bit can be erased or programmed To set the FPROT bit to 1 write a 0 and then a 1 to the FPROT bit in succession while the FENTRY bit 1 The FPROT bit is cleared to 0 by writing a 0 to the FPROT bit and setting the ...

Page 145: ... D Bit Name Function R W 0 6 No functions assigned 0 7 FELEVEL 0 Normal level Raise erase margin 1 Raise erase margin The Flash Control Register 3 FCNT3 controls the depth of erase levels when erasing the internal flash memory with one of erase commands By setting the FELEVEL bit to 1 the flash memory erase level can be deepened which will result in an increased reliability margin ...

Page 146: ...ash memory The Flash Control Register 4 FCNT4 controls canceling program erase operation in the middle and initializing each status bit of Flash Status Register 2 FSTAT2 When the FRESET bit is set to 1 program erase operation is canceled in the middle and each status bit of FSTAT2 is initialized H 80 The FRESET bit is effective only when the FENTRY bit 1 Information on FRESET bit is ignored unless...

Page 147: ...r Using the FCNT4 Register INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory FRESET 1 YES NO FENTRY 1 Program erase flash memory Error found Program erase terminated normally FRESET 0 Program erase flash memory FENTRY 0 ...

Page 148: ...of the L bank L bank address to be selected 15 No functions assigned 0 Note This register must always be accessed in halfword 1 MODENL Virtual Flash Emulation Enable bit D0 The MODENL bit can be set to 1 after entering virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 This causes the virtual flash emulation function to become effective for the L bank area selected ...

Page 149: ... S bank S bank address to be selected Note This register must always be accessed in halfword 1 MODENS Virtual Flash Emulation Enable bit D0 The MODENS bit can be set to 1 after entering virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 This causes the virtual flash emulation function to become effective for the S bank area selected by the SBANKAD bits 2 SBANKAD S B...

Page 150: ...te You now can write to the internal flash memory using the flash write program that has been transferred into the internal RAM For 2 set the FP pin high MOD0 low and MOD1 low to enter flash E W enable mode in single chip mode Transfer the flash write program from the internal flash memory in which it has been prepared beforehand into the internal RAM After this transfer jump to the RAM and set th...

Page 151: ...Entry When in Flash E W Enable Mode EI vector entry Internal ROM area Internal RAM H 0000 0080 H 0000 0000 H 00FF FFFF H 0080 4000 Internal ROM area Internal RAM H 0080 3FFF Flash E W enable mode FENTRY 1 Normal mode FENTRY 0 H 0000 0000 H 0080 3FFF EI vector entry H 0080 4000 H 0080 4000 H 00FF FFFF ...

Page 152: ...RAM RAM Step 1 Initial state where the write program does not exist in the flash memory Step 2 Set the FP pin high the MOD0 pin high and the MOD1 pin low to place the device in boot mode flash E W enable mode Deassert reset and start up using the boot program Transfer the flash write program from boot ROM to RAM Jump to the flash write program in RAM Step 3 Using the flash write program in RAM set...

Page 153: ...re 6 5 3 Internal Flash Memory Write Timings when the write program does not exist in the flash memory RESET MOD0 FENTRY FP MOD1 POWER ON Mode selected Reset deasserted Boot program starts Mode selected Reset deasserted Writes to flash memory by boot program Settings by boot program ...

Page 154: ...write program FP L or H AAAA AAAA RAM RAM Step 1 Initial state where the write program already exists in the flash memory Ordinary program in the flash memory is being executed Step 2 Set the FP pin high the MOD1 pin low and the MOD0 pin low to place the device in single chip flash E W enable mode After determining the FP pin and MOD1 pin levels transfer the flash write program from the flash memo...

Page 155: ...ory Write Timings when the write program already exists in the flash memory RESET MOD0 FENTRY FP H or L H or L Single chip or extended external MOD1 L H or L Write to flash memory by flash rewrite program Flash rewrite starts Flash mode turned off Flash rewrite program transferred to RAM Flash mode turned on ...

Page 156: ...lash E W enable flash memory internal RAM H 0000 0000 H 0080 4000 1 1 0 0 Boot mode Start address of Flash area boot program area H 0000 0080 H 8000 0000 1 1 0 1 Boot mode Start address of Beginning of flash E W enable boot program area internal RAM H 8000 0000 H 0080 4000 1 0 1 1 Extended external mode Start address of Beginning of flash E W enable flash memory internal RAM H 0000 0000 H 0080 400...

Page 157: ...evels high or low can be verified using the P8 Data Register Port Data Register H 00800 0708 MOD0DT and MOD1DT bits P8 Data Register P8DATA Address H 0080 0708 D0 1 2 3 4 5 6 D7 MOD0DT MOD1DT P82DT P83DT P84DT P85DT P86DT P87DT When reset Indeterminate D Bit Name Function R W 0 MOD0DT 0 MOD0 pin low MOD0 data 1 MOD0 pin high 1 MOD1DT 0 MOD1 pin low MOD1 data 1 MOD1 pin high 2 P82DT Depending on ho...

Page 158: ...xtended external mode flash E W enable mode Transfer E W program to internal RAM in each mode Set Flash Control Register in SFR area FCNT1 H 0080 07E2 flash entry FENTRY bit to 0 Set Flash Control Register in SFR area FCNT1 H 0080 07E2 flash entry FENTRY bit to 1 Execute flash E W command and various read commands Note Switched to flash E W program 1 µs wait by hardware timer or software timer Jum...

Page 159: ...ds for the internal flash memory address to be operated on The table below lists the commands that can be issued in flash memory E W enable mode Note During flash E W enable mode the flash memory cannot be accessed for read or write wordwise Table 6 5 2 Commands in Flash Memory E W Enable Mode Command Name Issued Command Data Read Array command H FFFF Page Program command H 4141 Lock Bit Program c...

Page 160: ...ection 6 4 2 Flash Status Registers While the FSTAT bit 1 the next programming can not be performed 3 Lock Bit Program command Flash memory can be protected against program erase one block at a time The Lock Bit Program command is provided for protecting memory blocks Write the Lock Bit Program command data H 7777 to any address of the internal flash memory Next write the Verify command data H D0D...

Page 161: ... 0000 FFFE 4 H 0001 FFFE 5 H 0002 FFFE 6 H 0003 FFFE 7 H 0004 FFFE 8 H 0005 FFFE 9 H 0006 FFFE 10 H 0007 FFFE 11 H 0008 FFFE 12 H 0009 FFFE 13 H 000A FFFE 14 H 000B FFFE Table 6 5 4 M32170F4 Target Blocks and Specified Addresses Target Block Specified Address 0 H 0000 3FFE 1 H 0000 5FFE 2 H 0000 7FFE 3 H 0000 FFFE 4 H 0001 FFFE 5 H 0002 FFFE 6 H 0003 FFFE 7 H 0004 FFFE 8 H 0005 FFFE 9 H 0006 FFFE ...

Page 162: ...ng of the Internal Flash Memory Table 6 5 5 M32170F3 Target Blocks and Specified Addresses Target Block Specified Address 0 H 0000 3FFE 1 H 0000 5FFE 2 H 0000 7FFE 3 H 0000 FFFE 4 H 0001 FFFE 5 H 0002 FFFE 6 H 0003 FFFE 7 H 0004 FFFE 8 H 0005 FFFE ...

Page 163: ...00 4000 H 0000 FFFF H 0001 0000 H 0000 5FFF H 0000 6000 64KB H 0002 FFFF 64KB H 0009 FFFF H 0009 0000 64KB H 000A FFFF H 000A 0000 64KB H 000B FFFF H 000B 0000 64KB Block 0 64KB 64KB 64KB 64KB 64KB H 0003 0000 H 0003 FFFF H 0004 0000 H 0004 FFFF H 0005 0000 H 0005 FFFF H 0006 0000 H 0006 FFFF H 0007 0000 H 0007 FFFF H 0008 0000 H 0008 FFFF Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Bl...

Page 164: ...B 32KB 64KB H 0000 0000 H 0000 7FFF H 0000 8000 H 0001 FFFF H 0000 3FFF H 0000 4000 H 0000 FFFF H 0001 0000 H 0000 5FFF H 0000 6000 64KB H 0002 FFFF 64KB 64KB 64KB Block 0 64KB 64KB H 0003 0000 H 0003 FFFF H 0004 0000 H 0004 FFFF H 0005 0000 H 0005 FFFF H 0006 0000 H 0006 FFFF H 0007 0000 H 0007 FFFF Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Uneven blocks Even blocks Block 9 ...

Page 165: ...ry Area 384KB H 0002 0000 8KB 16KB 8KB 32KB 64KB H 0000 0000 H 0000 7FFF H 0000 8000 H 0001 FFFF H 0000 3FFF H 0000 4000 H 0000 FFFF H 0001 0000 H 0000 5FFF H 0000 6000 64KB H 0002 FFFF 64KB 64KB 64KB Block 0 H 0003 0000 H 0003 FFFF H 0004 0000 H 0004 FFFF H 0005 0000 H 0005 FFFF Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Uneven blocks Even blocks ...

Page 166: ...data H A7A7 to any address of the internal flash memory Next write the command data H D0D0 to any address of the internal flash memory and all of unprotected memory blocks are erased 6 Read Status Register command The Read Status Register command reads out the content of Flash Status Register 2 FSTAT2 that indicates whether flash memory write or erase operation has terminated normally or not To re...

Page 167: ... Bit Status command The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program erase Write the command data H 7171 to any address of the internal flash memory Next read the last even address of the block you want to check see Table 6 5 3 Table 6 5 4 and Table 6 5 5 Target Blocks and Specified Addresses and the data you read shows whether or not ...

Page 168: ...d protection use the Block Erase command H 2020 or Erase All Unprotect Block command H A7A7 to erase the memory block you want to unprotect This is the only way to unprotect a memory block You cannot set the lock bit alone to 1 c Status when the lock bit is reset The lock bit is unaffected by a reset or power outage because it is a nonvolatile bit 9 Execution flow of each command The diagrams belo...

Page 169: ...tion WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for program error END Write data to the internal flash memory address to which you want to write Note 1 Increment the previous write address by 2 and write the next data to the new address Write Page Program command H 4141 to any address of internal flash memory Written to the internal flash memory by ...

Page 170: ...ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for program error END Write Verify command H D0D0 to the last even address of the block you want to protect Written to the lock bit by program Note 1 Write Lock Bit Program command H 7777 to any address of internal flash memory 1 µs wait by hardware timer or software tim...

Page 171: ...ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for erase error END Write Verify command H D0D0 to the last even address of the block you want to erase Flash memory contents erased by Erase program Note 1 Write Erase command H 2020 to any address of internal flash memory 1 µs wait by hardware timer or software timer F...

Page 172: ...ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for erase error END Write Verify command H D0D0 to any address in memory blocks you want to erase Flash memory contents erased by Erase program Note 1 Write Erase All Unlock Block command H A7A7 to any address of internal flash memory 1 µs wait by hardware timer or softw...

Page 173: ...us Register Write Read Status command H 7070 to any address of internal flash memory START Read any address of internal flash memory END Write Clear Status command H 5050 to any address of internal flash memory START END Write Read Lock Bit Status command H 7171 to any address of internal flash memory START Read the last even address of the block whose status you want to read END ...

Page 174: ...an be calculated using the equation below 151 s When writing data to flash memory at high speed by speeding up the serial communication or by other means the fastest write time possible is as follows 25 s 2 M32170F4 Transfer time by SIO for a transfer data size of 512 KB 1 57600 bps 1 frame 11 number of transfer bits 512 KB 100 2 s Flash write time 512 KB 256 byte block 8 ms 16 4 s Erase time enti...

Page 175: ...e entire area 50 ms number of blocks 450 ms Total flash write time entire 384 KB area When communicating at 57600 bps using UART the flash write time can be ignored because it is very short compared to the serial communication time Therefore the flash write time can be calculated using the equation below 76 s When writing data to flash memory at high speed by speeding up the serial communication o...

Page 176: ...ss H 8000 0000 H 8000 1FFF Wait insertion Operates with no wait states with 40 MHz internal CPU memory clock Internal bus connection Connected by 32 bit bus Read Can only be read when FP 1 MOD0 1 and MOD1 0 When read in other modes indeterminate values are read out Cannot be accessed for write Other Because the boot ROM area is a reserved area that can only be used in boot mode the program cannot ...

Page 177: ...S banks in the flash memory that are specified by the Virtual Flash Bank Register For applications that require modifying data during program operation this enables dynamic modification of data using 8 Kbytes or 4 Kbytes of RAM areas The RAM blocks allocated for virtual flash emulation can be read or written to from both internal RAM and internal flash memory areas This function when used in combi...

Page 178: ...AM Bank Configuration of the M32170F4 and M3170F3 H 0080 4000 H 0080 6000 H 0080 8000 H 0080 A000 H 0080 B000 RAM bank L block 0 FELBANK0 8 Kbytes RAM bank L block 1 FELBANK1 8 Kbytes RAM bank L block 2 FELBANK2 8 Kbytes RAM bank S block 0 FESBANK0 4 Kbytes RAM bank S block 1 FESBANK1 4 Kbytes ...

Page 179: ...ight bits A12 A19 of the start address of the desired S bank in the Virtual Flash S Bank Register SBANKAD bits Then by setting the Virtual Flash S Bank Register MODENS0 1 bits to 1 the selected S bank area can be replaced with 4 Kbyte blocks of internal RAM in up to two blocks starting from H 0080 C000 for the M32170F6 or H 0080 A000 for the M32170F4 and M32170F3 For the M32170F6 you can choose fo...

Page 180: ...u enable the Virtual Flash Emulation Enable bit the internal RAM area selected in order of priority FELBANK0 FELBANK1 FELBANK2 FELBANK3 FESBANK0 FESBANK1 is assigned Note 2 When you access an 4 Kbyte area S bank specified by Virtual Flash S Bank Registers 0 1 its corresponding internal RAM area is accessed During Virtual Flash Emulation mode RAM can be read or written to from both internal RAM are...

Page 181: ...ea in multiple Virtual Flash Bank Registers you enable the Virtual Flash Emulation Enable bit the internal RAM area selected in order of priority FELBANK0 FELBANK1 FELBANK2 FESBANK0 FESBANK1 is assigned Note 2 When you access an 4 Kbyte area S bank specified by Virtual Flash S Bank Registers 0 1 its corresponding internal RAM area is accessed During Virtual Flash Emulation mode RAM can be read or ...

Page 182: ...rea in multiple Virtual Flash Bank Registers you enable the Virtual Flash Emulation Enable bit the internal RAM area selected in order of priority FELBANK0 FELBANK1 FELBANK2 FESBANK0 FESBANK1 is assigned Note 2 When you access an 4 Kbyte area S bank specified by Virtual Flash S Bank Registers 0 1 its corresponding internal RAM area is accessed During Virtual Flash Emulation mode RAM can be read or...

Page 183: ...ddress LBANKAD bits Note Set the eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register s S bank address SBANKAD bits H 0000 0000 L bank Start address of bank in flash memory L bank address LBANKAD bit set value H 0000 2000 H 0000 4000 H 000B C000 H 000B E000 H 00 H 02 H 04 H BC H BE NOTE L bank 0 L bank 1 L bank 2 ...

Page 184: ...address LBANKAD bits Note Set the eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register s S bank address SBANKAD bits H 0000 0000 L bank Start address of bank in flash memory L bank address LBANKAD bit set value H 0000 2000 H 0000 4000 H 0007 C000 H 0007 E000 H 00 H 02 H 04 H 7C H 7E NOTE L bank 0 L bank 1 L bank 2...

Page 185: ... address LBANKAD bits Note Set the eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register s S bank address SBANKAD bits H 0000 0000 L bank Start address of bank in flash memory L bank address LBANKAD bit set value H 0000 2000 H 0000 4000 H 0005 C000 H 0005 E000 H 00 H 02 H 04 H 5C H 5E NOTE L bank 0 L bank 1 L bank ...

Page 186: ...n Function In Virtual Flash Emulation Mode also the internal RAM area H 0080 4000 through H 0080 DFFF for the M32170F6 or H 8080 4000 through H 0080 BFFF for the M32170F4 and M32170F3 can be accessed as internal RAM Figure 6 7 15 Virtual Flash Emulation Mode Sequence Set RAM location address in Virtual Flash Bank Register LBANKADn Address A12 A18 SBANKADn Address A12 A19 Write flash data to RAM En...

Page 187: ...plication Example of Virtual Flash Emulation 1 2 Replace area Flash RAM block 0 Data write to RAM0 1 Operation when reset 2 Program operation using RAM block 0 Initial value 3 Program operation changed from RAM block 0 to RAM block 1 Bank xx Bank xx specified RAM block 0 RAM block 1 Replace Flash RAM block 0 Data write to RAM1 Initial value Bank xx RAM block 1 Bank xx specified RAM block 0 Replace...

Page 188: ... valid area 4 Program operation using RAM block 1 Bank xx specified RAM block 1 Replace Flash RAM block 0 Data write to RAM0 Initial value Bank xx RAM block 1 5 Program operation changed from RAM block 1 to RAM block 0 Bank xx specified RAM block 0 Replace Flash RAM block 0 Initial value Bank xx RAM block 1 RAM block 1 Bank xx specified settings invalid ...

Page 189: ... AVCC1 62 228 AVSS0 AVSS1 79 5 FVCC 128 VDD 170 Transfer clock input Serial data input receive data Serial data output transmit data Transmit receive enable output Flash memory protect Operation mode 1 Reset Clock input Clock output PLL circuit power supply PLL circuit ground PLL circuit control input VCNT 23 A D converter reference voltage input Analog power supply Analog ground Flash memory powe...

Page 190: ...lash memory Note 2 If the system circuit uses P83 P87 consideration must be taken for connection of a serial programmer Note 3 P83 must have a high level signal applied to it Note 4 P64 SBI must be fixed high or low to ensure that interrupts will not be generated Note 5 The pullup resistances of P83 P84 P86 and P87 must be set to suit system design conditions Note 6 The typical pullup resistances ...

Page 191: ...are used by a serial programmer take measures not to affect the system when connecting a serial programmer If the flash memory needs to be protected set an appropriate ID in the flash memory protect ID verification area H 0000 0084 through H 0000 0093 If the flash memory does not require protection fill the entire flash memory protect ID verification area H 0000 0084 through H 0000 0093 with H FF ...

Page 192: ...6 6 58 Ver 0 10 INTERNAL MEMORY 6 9 Precautions to Be Taken When Rewriting Flash Memory This is a blank page ...

Page 193: ...CHAPTER 7 CHAPTER 7 RESET 7 1 Outline of Reset 7 2 Reset Operation 7 3 Internal State Immediately after Reset Release 7 4 Things To Be Considered after Reset Release ...

Page 194: ... at Power on _____ When powering on the device hold the RESET input low until its internal multiply by 4 clock generator becomes oscillating stably 7 2 2 Reset during Operation _____ To reset the device during operation hold the RESET input low for more than four clock periods of XIN signal 7 2 3 Reset Vector Relocation during Flash Rewrite When placed in boot mode the reset vector entry address i...

Page 195: ...ion in this manual where the relevant internal peripheral I O is described Table 7 3 1 Internal State Immediately after Reset Register State after Reset Release PSW CR0 B 0000 0000 0000 0000 00 000 0000 0000 BSM BIE BC bits indeterminate CBR CR1 H 0000 0000 C bit 0 SPI CR2 Indeterminate SPU CR3 Indeterminate BPC CR6 Indeterminate PC H 0000 0000 Executed beginning with address H 0000 0000 Note ACC ...

Page 196: ...put ports After reset release the 32170 s input output ports are disabled against input in order to prevent current from flowing through the port To use any ports in input mode enable them for input using the Port Input Function Enable Register PIEN PIEN0 bit For details refer to Section 8 3 Input Output Port Related Registers ...

Page 197: ...CHAPTER 8 CHAPTER 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 1 Outline of Input Output Ports 8 2 Selecting Pin Functions 8 3 Input Output Port Related Registers 8 4 Port Peripheral Circuits ...

Page 198: ...oose or by setting the input output port s Operation Mode Register If any internal peripheral I O has still another function you need to set the register provided for that peripheral I O As a new function the 32170 internally contains a Port Input Function Enable bit that can be used to prevent current from flowing into the input ports This helps to simplify the software and hardware processing to...

Page 199: ...es P19 P190 P197 8 lines P20 P200 P203 4 lines P21 P210 P217 8 lines P22 P220 P225 6 lines Port function The input output ports can individually be set for input or output mode using the Direction Control Register provided for each input output port However P64 is an ___ SBI input only port and P221 is a CAN input only port Pin function Shared with peripheral I O or extended external signals to se...

Page 200: ...ing the MOD0 and MOD1 pins see the table below Table 8 2 1 CPU Operation Mode and Pin Functions of P0 P4 P224 and P225 MOD0 MOD1 Operation Mode Pin Functions of P0 P4 P224 and P225 VSS VSS Single chip mode input output port pin VSS VCCE Extended external mode Extended external signal pin VCCE VSS Processor mode VCCE VCCE Reserved Use inhibited Note VCCE and VSS are connected to 5 V and GND respect...

Page 201: ...14 P61 P62 P63 SBI SCLKI4 SCLKO4 ADTRG BCLK WR WAIT HREQ HACK RTDTXD RTDRXD RTDACK RTDCLK TXD0 RXD0 SCLKI0 SCLKO0 TXD1 RXD1 SCLKI1 SCLKO1 TO16 TO17 TO18 TO19 TO20 TO11 TO12 TO13 TO14 TO15 TO10 TO9 TO8 TO3 TO4 TO5 TO6 TO7 TO2 TO1 TO0 TCLK0 TCLK1 TCLK2 TCLK3 TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 TIN0 TIN1 TIN2 TIN3 TIN4 TIN5 TIN6 TIN7 Settings ...

Page 202: ...ister P11DIR P17 Data Register P17DATA P19 Data Register P19DATA P21 Data Register P21DATA P13 Direction Register P13DIR P15 Direction Register P15DIR P17 Direction Register P17DIR P19 Direction Register P19DIR P21 Direction Register P21DIR H 0080 0700 H 0080 0702 H 0080 0704 H 0080 0706 H 0080 0708 H 0080 070A H 0080 070C H 0080 070E H 0080 0720 H 0080 0722 H 0080 0724 H 0080 0726 H 0080 0728 H 0...

Page 203: ...ster PIEN P19 Operation Mode Register P19MOD P21 Operation Mode Register P21MOD P6 Operation Mode Register P6MOD P8 Operation Mode Register P8MOD P10 Operation Mode Register P10MOD P12 Operation Mode Register P12MOD P14 Operation Mode Register P14MOD P16 Operation Mode Register P16MOD P18 Operation Mode Register P18MOD P20 Operation Mode Register P20MOD P22 Operation Mode Register P22MOD H 0080 07...

Page 204: ...ss H 0080 070B P12 Data Register P12DATA Address H 0080 070C P13 Data Register P13DATA Address H 0080 070D P14 Data Register P14DATA Address H 0080 070E P15 Data Register P15DATA Address H 0080 070F P16 Data Register P16DATA Address H 0080 0710 P17 Data Register P17DATA Address H 0080 0711 P18 Data Register P18DATA Address H 0080 0712 P19 Data Register P19DATA Address H 0080 0713 P20 Data Register...

Page 205: ... output mode 5 Pn5DT Port Pn5 data 0 Port output latch low 6 Pn6DT Port Pn6 data 1 Port output latch high 7 Pn7DT Port Pn7 data Note 1 The following bits have no functions assigned when read the bit 0 writing to the bit has no effect Note 2 Port P64 is input mode only Writing to the P64DT bit has no effect Note 3 Port P221 is input mode only Writing to the P221DT bit has no effect Note 4 Ports P80...

Page 206: ...s H 0080 072B P12 Direction Register P12DIR Address H 0080 072C P13 Direction Register P13DIR Address H 0080 072D P14 Direction Register P14DIR Address H 0080 072E P15 Direction Register P15DIR Address H 0080 072F P16 Direction Register P16DIR Address H 0080 0730 P17 Direction Register P17DIR Address H 0080 0731 P18 Direction Register P18DIR Address H 0080 0732 P19 Direction Register P19DIR Addres...

Page 207: ...4 direction bit 5 Pn5DIR Port Pn5 direction bit 6 Pn6DIR Port Pn6 direction bit 7 Pn7DIR Port Pn7 direction bit Note 1 The following bits have no functions assigned when read the bit 0 writing to the bit has no effect Note 2 When reset all ports are placed in input mode Note 3 Port P64 is input mode only The register does not have a P64DIR bit Note 4 Ports P80 and P81 are input mode only The regis...

Page 208: ...H 00 D Bit Name Function R W 0 4 No functions assigned 0 5 P65MOD 0 P65 Port P65 operation mode 1 SCLKI4 SCLKO4 6 P66MOD 0 P66 Port P66 operation mode 1 SCLKI5 SCLKO5 7 P67MOD 0 P67 Port P67 operation mode _____ 1 ADTRG Note 1 Port 60 is not accommodated Note 2 Ports P61 P63 are always input output ports single function pins ___ Note 3 Port P64 is an SBI input only pin The pin level can be verifie...

Page 209: ...set H 00 D Bit Name Function R W 8 P70MOD 0 P70 Port P70 operation mode __ 1 BCLK WR 9 P71MOD 0 P71 Port P71 operation mode ____ 1 WAIT 10 P72MOD 0 P72 Port P72 operation mode ____ 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode ____ 1 HACK 12 P74MOD 0 P74 Port P74 operation mode 1 RTDTXD 13 P75MOD 0 P75 Port P75 operation mode 1 RTDRXD 14 P76MOD 0 P76 Port P76 operation mode 1 RTDACK 15 P77MOD 0 P...

Page 210: ... When reset H 00 D Bit Name Function R W 0 1 No functions assigned 0 2 P82MOD 0 P82 Port P82 operation mode 1 TXD0 3 P83MOD 0 P83 Port P83 operation mode 1 RXD0 4 P84MOD 0 P84 Port P84 operation mode 1 SCLKI0 SCLKO0 5 P85MOD 0 P85 Port P85 operation mode 1 TXD1 6 P86MOD 0 P86 Port P86 operation mode 1 RXD1 7 P87MOD 0 P87 Port P87 operation mode 1 SCLKI1 SCLKO1 Note Ports P80 and P81 are not accomm...

Page 211: ...MOD P94MOD P95MOD P96MOD P97MOD When reset H 00 D Bit Name Function R W 8 10 No functions assigned 0 11 P93MOD 0 P93 Port P93 operation mode 1 TO16 12 P94MOD 0 P94 Port P94 operation mode 1 TO17 13 P95MOD 0 P95 Port P95 operation mode 1 TO18 14 P96MOD 0 P96 Port P96 operation mode 1 TO19 15 P97MOD 0 P97 Port P97 operation mode 1 TO20 Note Ports P90 P92 are not accommodated ...

Page 212: ... When reset H 00 D Bit Name Function R W 0 P100MOD 0 P100 Port P100 operation mode 1 TO8 1 P101MOD 0 P101 Port P101 operation mode 1 TO9 2 P102MOD 0 P102 Port P102 operation mode 1 TO10 3 P103MOD 0 P103 Port P103 operation mode 1 TO11 4 P104MOD 0 P104 Port P104 operation mode 1 TO12 5 P105MOD 0 P105 Port P105 operation mode 1 TO13 6 P106MOD 0 P106 Port P106 operation mode 1 TO14 7 P107MOD 0 P107 P...

Page 213: ...MOD When reset H 00 D Bit Name Function R W 8 P110MOD 0 P110 Port P110 operation mode 1 TO0 9 P111MOD 0 P111 Port P111 operation mode 1 TO1 10 P112MOD 0 P112 Port P112 operation mode 1 TO2 11 P113MOD 0 P113 Port P113 operation mode 1 TO3 12 P114MOD 0 P114 Port P114 operation mode 1 TO4 13 P115MOD 0 P115 Port P115 operation mode 1 TO5 14 P116MOD 0 P116 Port P116 operation mode 1 TO6 15 P117MOD 0 P1...

Page 214: ...2 3 4 5 6 D7 P124MOD P125MOD P126MOD P127MOD When reset H 00 D Bit Name Function R W 0 3 No functions assigned 0 4 P124MOD 0 P124 Port P124 operation mode 1 TCLK0 5 P125MOD 0 P125 Port P125 operation mode 1 TCLK1 6 P126MOD 0 P126 Port P126 operation mode 1 TCLK2 7 P127MOD 0 P127 Port P127 operation mode 1 TCLK3 Note Ports P120 P123 are not accommodated ...

Page 215: ... reset H 00 D Bit Name Function R W 8 P130MOD 0 P130 Port P130 operation mode 1 TIN16 9 P131MOD 0 P131 Port P131 operation mode 1 TIN17 10 P132MOD 0 P132 Port P132 operation mode 1 TIN18 11 P133MOD 0 P133 Port P133 operation mode 1 TIN19 12 P134MOD 0 P134 Port P134 operation mode 1 TIN20 13 P135MOD 0 P135 Port P135 operation mode 1 TIN21 14 P136MOD 0 P136 Port P136 operation mode 1 TIN22 15 P137MO...

Page 216: ...n reset H 00 D Bit Name Function R W 0 P140MOD 0 P140 Port P140 operation mode 1 TIN8 1 P141MOD 0 P141 Port P141 operation mode 1 TIN9 2 P142MOD 0 P142 Port P142 operation mode 1 TIN10 3 P143MOD 0 P143 Port P143 operation mode 1 TIN11 4 P144MOD 0 P144 Port P144 operation mode 1 TIN12 5 P145MOD 0 P145 Port P145 operation mode 1 TTIN13 6 P146MOD 0 P146 Port P146 operation mode 1 TIN14 7 P147MOD 0 P1...

Page 217: ...When reset H 00 D Bit Name Function R W 8 P150MOD 0 P150 Port P150 operation mode 1 TIN0 9 P151MOD 0 P151 Port P151 operation mode 1 TIN1 10 P152MOD 0 P152 Port P152 operation mode 1 TIN2 11 P153MOD 0 P153 Port P153 operation mode 1 TIN3 12 P154MOD 0 P154 Port P154 operation mode 1 TIN4 13 P155MOD 0 P155 Port P155 operation mode 1 TIN5 14 P156MOD 0 P156 Port P156 operation mode 1 TIN6 15 P157MOD 0...

Page 218: ...When reset H 00 D Bit Name Function R W 0 P160MOD 0 P160 Port P160 operation mode 1 TO21 1 P161MOD 0 P161 Port P161 operation mode 1 TO22 2 P162MOD 0 P162 Port P162 operation mode 1 TO23 3 P163MOD 0 P163 Port P163 operation mode 1 TO24 4 P164MOD 0 P164 Port P164 operation mode 1 TO25 5 P165MOD 0 P165 Port P165 operation mode 1 TO26 6 P166MOD 0 P166 Port P166 operation mode 1 TO27 7 P167MOD 0 P167 ...

Page 219: ...OD When reset H 00 D Bit Name Function R W 8 9 No functions assigned 0 10 P172MOD 0 P172 Port P172 operation mode 1 TIN24 11 P173MOD 0 P173 Port P173 operation mode 1 TIN25 12 P174MOD 0 P174 Port P174 operation mode 1 TXD2 13 P175MOD 0 P175 Port P175 operation mode 1 RXD2 14 P176MOD 0 P176 Port P176 operation mode 1 TXD3 15 P177MOD 0 P177 Port P177 operation mode 1 RXD3 Note Ports P170 and P171 ar...

Page 220: ...When reset H 00 D Bit Name Function R W 0 P180MOD 0 P180 Port P180 operation mode 1 TO29 1 P181MOD 0 P181 Port P181 operation mode 1 TO30 2 P182MOD 0 P182 Port P182 operation mode 1 TO31 3 P183MOD 0 P183 Port P183 operation mode 1 TO32 4 P184MOD 0 P184 Port P184 operation mode 1 TO33 5 P185MOD 0 P185 Port P185 operation mode 1 TO34 6 P186MOD 0 P186 Port P186 operation mode 1 TO35 7 P187MOD 0 P187 ...

Page 221: ... reset H 00 D Bit Name Function R W 8 P190MOD 0 P190 Port P190 operation mode 1 TIN26 9 P191MOD 0 P191 Port P191 operation mode 1 TIN27 10 P192MOD 0 P192 Port P192 operation mode 1 TIN28 11 P193MOD 0 P193 Port P193 operation mode 1 TIN29 12 P194MOD 0 P194 Port P194 operation mode 1 TIN30 13 P195MOD 0 P195 Port P195 operation mode 1 TIN31 14 P196MOD 0 P196 Port P196 operation mode 1 TIN32 15 P197MO...

Page 222: ...1 2 3 4 5 6 D7 P200MOD P201MOD P202MOD P203MOD When reset H 00 D Bit Name Function R W 0 P200MOD 0 P200 Port P200 operation mode 1 TXD4 1 P201MOD 0 P201 Port P201 operation mode 1 RXD4 2 P202MOD 0 P202 Port P202 operation mode 1 TXD5 3 P203MOD 0 P203 Port P203 operation mode 1 RXD5 4 7 No functions assigned 0 Note Ports P204 P207 are not accommodated ...

Page 223: ...When reset H 00 D Bit Name Function R W 8 P210MOD 0 P210 Port P210 operation mode 1 TO37 9 P211MOD 0 P211 Port P211 operation mode 1 TO38 10 P212MOD 0 P212 Port P212 operation mode 1 TO39 11 P213MOD 0 P213 Port P213 operation mode 1 TO40 12 P214MOD 0 P214 Port P214 operation mode 1 TO41 13 P215MOD 0 P215 Port P215 operation mode 1 TO42 14 P216MOD 0 P216 Port P216 operation mode 1 TO43 15 P217MOD 0...

Page 224: ...tions assigned 0 4 P224MOD 0 P224 Port P224 operation mode 1 Use inhibited 5 P225MOD 0 P225 Port P225 operation mode 1 Use inhibited 6 7 No functions assigned 0 Note 1 P221 is a CAN input only pin Note 2 P222 P223 are always input output ports single function pins Note 3 P224 and P225 have their pin functions changed depending on how the MOD0 and MOD1 pins are set Also use of these ports requires ...

Page 225: ...nput This register is provided to prevent current from flowing into the port input pin Because after reset this register is set to disable input it must be set to 1 before input can be processed During boot mode all pins shared with serial I O function are enabled for input so that when rewriting the flash memory via serial communication you can set this register to 0 to prevent current from flowi...

Page 226: ...P203 P210 P217 P220 P222 P225 P61 P63 P65 P67 P70 P77 P00 P07 P10 P17 P82 P87 P93 P97 P100 P107 P20 P27 P30 P37 Extended external P110 P117 P124 P127 P130 P137 P41 P47 P64 P221 P224 Microprocessor P140 P147 P150 P157 P160 P167 P225 FP P172 P177 P180 P187 P190 P197 P200 P203 P210 P217 P220 P222 P223 P00 P07 P10 P17 P20 P27 P64 P66 P82 P87 P30 P37 P41 P47 P61 P63 P174 P177 P200 P203 Boot single chip...

Page 227: ...t their functional description in this block diagram is omitted P00 P07 DB0 DB7 P10 P17 DB8 DB15 P20 P27 A23 A30 P30 P37 A15 A22 ___ ___ P41 BLW BLE ___ ___ P42 BHW BHE __ P43 RD ___ P44 CS0 ___ P45 CS1 P46 P47 A13 A14 P61 P63 P224 P225 A11 A12 P222 P223 _____ P67 ADTRG P75 RTDRXD P77 RTDCLK P83 RXD0 P86 RXD1 P124 P127 TCLK0 TCLK3 P130 P137 TIN16 TIN23 P140 P147 TIN8 TIN15 P150 P157 TIN0 TIN7 P172...

Page 228: ... 4 Port Peripheral Circuits Figure 8 4 2 Port Peripheral Circuit Diagram 2 Note denotes pins ___ P64 SBI P221 CRX ____ P72 HREQ SBI Operation mode register HREQ Data bus DB0 DB15 Port output latch Direction register Input function enable Data bus DB0 DB15 ...

Page 229: ...P82 TXD0 P85 TXD1 P93 P97 TO16 TO20 P100 P107 TO8 TO15 P110 P117 TO0 TO7 P160 P167 TO21 TO28 P174 TXD2 P176 TXD3 P180 P187 TO29 TO36 P200 TXD4 P202 TXD5 P210 P217 TO37 TO44 P220 CTX WAIT Data bus DB0 DB15 Operation mode register Port output latch Direction register Input function enable Peripheral function input Data bus DB0 DB15 Port output latch Direction register Input function enable Operation...

Page 230: ... Note denotes pins P84 SCLKI0 SCLKO0 P87 SCLKI1 SCLKO1 P65 SCLKI14 SCLKO4 P66 SCLKI15 SCLKO5 MOD0 MOD1 FP _____ RESET SCLKIi input SCLKOi output RESET MOD0 MOD1 FP Operation mode register Data bus DB0 DB15 Port output latch Direction register Input function enable UART CSIO function select bit Internal external clock select bit ...

Page 231: ...CHAPTER 9 CHAPTER 9 DMAC 9 1 Outline of the DMAC 9 2 DMAC Related Registers 9 3 Functional Description of the DMAC 9 4 Precautions about the DMAC ...

Page 232: ...es can be selected for the source and destination Address fixed Address incremental Ring buffered Channel priority Channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 9 Priority is fixed Maximum transfer rate 13 3 Mbytes per second with 20 MHz internal peripheral clock Interrupt request Group interrupt request can be generated when each transfer count ...

Page 233: ...nsmit buffer empty Software start MJT TIN2 input signal One DMA6 transfer completed Serial I O2 transmit buffer empty Software start MJT input event bus 0 Serial I O3 reception completed MJT TIN7 input signal Source Destination Transfer count Interrupt request Internal bus arbitration Software start MJT TIN8 input signal One DMA8 transfer completed Serial I O3 transmit buffer empty Transfer count ...

Page 234: ...ister DM0DA DMA0 4 Interrupt Mask Register DM04ITMK DMA5 9 Interrupt Request Status Register DM59ITST DMA5 9 Interrupt Mask Register DM59ITMK DMA0 Channel Control Register DM0CNT DMA0 Transfer Count Register DM0TCT DMA5 Source Address Register DM5SA DMA5 Destination Address Register DM5DA DMA5 Channel Control Register DM5CNT DMA5 Transfer Count Register DM5TCT DMA1 Source Address Register DM1SA DM...

Page 235: ...estination Address Register DM8DA DMA8 Channel Control Register DM8CNT DMA8 Transfer Count Register DM8TCT DMA4 Source Address Register DM4SA DMA4 Destination Address Register DM4DA DMA4 Channel Control Register DM4CNT DMA4 Transfer Count Register DM4TCT DMA9 Source Address Register DM9SA DMA9 Destination Address Register DM9DA DMA9 Channel Control Register DM9CNT DMA9 Transfer Count Register DM9T...

Page 236: ...0 transfer request flag 1 Requested 2 3 REQSL0 00 Software start or one DMA2 transfer completed Selects cause of DMA0 request 01 A D0 conversion completed 10 MJT TIO8_udf 11 MJT input event bus 2 4 TENL0 0 Disables transfer Enables DMA0 transfer 1 Enables transfer 5 TSZSL0 0 16 bits Selects DMA0 transfer size 1 8 bits 6 SADSL0 0 Fixed Selects DMA0 source address direction 1 Incremental 7 DADSL0 0 ...

Page 237: ...r request flag 1 Requested 2 3 REQSL1 00 Software start Selects cause of DMA1 request 01 MJT output event bus 0 10 MJT TIN13 input signal 11 One DMA0 transfer completed 4 TENL1 0 Disables transfer Enables DMA1 transfer 1 Enables transfer 5 TSZSL1 0 16 bits Selects DMA1 transfer size 1 8 bits 6 SADSL1 0 Fixed Selects DMA1 source address direction 1 Incremental 7 DADSL1 0 Fixed Selects DMA1 destinat...

Page 238: ...r request flag 1 Requested 2 3 REQSL2 00 Software start Selects cause of DMA2 request 01 MJT output event bus 1 10 MJT TIN18 input signal 11 One DMA1 transfer completed 4 TENL2 0 Disables transfer Enables DMA2 transfer 1 Enables transfer 5 TSZSL2 0 16 bits Selects DMA2 transfer size 1 8 bits 6 SADSL2 0 Fixed Selects DMA2 source address direction 1 Incremental 7 DADSL2 0 Fixed Selects DMA2 destinat...

Page 239: ...st flag 1 Requested 2 3 REQSL3 00 Software start Selects cause of DMA3 request 01 Serial I O0 transmit buffer empty 10 Serial I O1 reception completed 11 MJT TIN0 input signal 4 TENL3 0 Disables transfer Enables DMA3 transfer 1 Enables transfer 5 TSZSL3 0 16 bits Selects DMA3 transfer size 1 8 bits 6 SADSL3 0 Fixed Selects DMA3 source address direction 1 Incremental 7 DADSL3 0 Fixed Selects DMA3 d...

Page 240: ...quest flag 1 Requested 2 3 REQSL4 00 Software start Selects cause of DMA4 request 01 One DMA3 transfer completed 10 Serial I O0 reception completed 11 MJT TIN19 input signal 4 TENL4 0 Disables transfer Enables DMA4 transfer 1 Enables transfer 5 TSZSL4 0 16 bits Selects DMA4 transfer size 1 8 bits 6 SADSL4 0 Fixed Selects DMA4 source address direction 1 Incremental 7 DADSL4 0 Fixed Selects DMA4 des...

Page 241: ...uested 2 3 REQSL5 00 Software start or one DMA7 transfer completed Selects cause of DMA5 request 01 All DMA0 transfers completed 10 Serial I O2 reception completed 11 MJT TIN20 input signal 4 TENL5 0 Disables transfer Enables DMA5 transfer 1 Enables transfer 5 TSZSL5 0 16 bits Selects DMA5 transfer size 1 8 bits 6 SADSL5 0 Fixed Selects DMA5 source address direction 1 Incremental 7 DADSL5 0 Fixed ...

Page 242: ...quest flag 1 Requested 2 3 REQSL6 00 Software start Selects cause of DMA6 request 01 Serial I O1 transmit buffer empty 10 MJT TIN1 input signal 11 One DMA5 transfer completed 4 TENL6 0 Disables transfer Enables DMA6 transfer 1 Enables transfer 5 TSZSL6 0 16 bits Selects DMA6 transfer size 1 8 bits 6 SADSL6 0 Fixed Selects DMA6 source address direction 1 Incremental 7 DADSL6 0 Fixed Selects DMA6 de...

Page 243: ...quest flag 1 Requested 2 3 REQSL7 00 Software start Selects cause of DMA7 request 01 Serial I O2 transmit buffer empty 10 MJT TIN2 input signal 11 One DMA6 transfer completed 4 TENL7 0 Disables transfer Enables DMA7 transfer 1 Enables transfer 5 TSZSL7 0 16 bits Selects DMA7 transfer size 1 8 bits 6 SADSL7 0 Fixed Selects DMA7 source address direction 1 Incremental 7 DADSL7 0 Fixed Selects DMA7 de...

Page 244: ...r request flag 1 Requested 2 3 REQSL8 00 Software start Selects cause of DMA8 request 01 MJT input event bus 0 10 Serial I O3 reception completed 11 MJT TIN7 input signal 4 TENL8 0 Disables transfer Enables DMA8 transfer 1 Enables transfer 5 TSZSL8 0 16 bits Selects DMA8 transfer size 1 8 bits 6 SADSL8 0 Fixed Selects DMA8 source address direction 1 Incremental 7 DADSL8 0 Fixed Selects DMA8 destin...

Page 245: ...quest flag 1 Requested 2 3 REQSL9 00 Software start Selects cause of DMA9 request 01 Serial I O3 transmit buffer empty 10 MJT TIN8 input signal 11 One DMA8 transfer completed 4 TENL9 0 Disables transfer Enables DMA9 transfer 1 Enables transfer 5 TSZSL9 0 16 bits Selects DMA7 transfer size 1 8 bits 6 SADSL9 0 Fixed Selects DMA7 source address direction 1 Incremental 7 DADSL9 0 Fixed Selects DMA9 de...

Page 246: ...u write a 1 the value you wrote is ignored and the bit retains its previous value If a new DMA transfer request is generated for a channel whose DMA transfer request flag has already been set to 1 the next DMA transfer request is not accepted until the transfer under way in that channel is completed 3 REQSLn cause of DMAn request select bits D2 D3 These bits select the cause of DMA request in each...

Page 247: ...76 DMA9 Software Request Generation Register DM9SRI Address H 0080 0478 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 DM0SRI DM9SRI When reset Indeterminate D Bit Name Function R W 0 15 DM0SRI DM9SRI DMA transfer request is generated Generates DMA software request by writing any data Note This register can be accessed in either bytes or halfwords The DMA Software Request Generation Register is used to g...

Page 248: ...r in such a way that D0 corresponds to A16 and D15 corresponds to A31 Because this register is comprised of a current register the value you get by reading this register is always the current value When DMA transfer finishes at which the Transfer Count Register underflows the value in this register if Address fixed is selected is the same source address that was set in it before DMA transfer began...

Page 249: ... of DMA transfer in such a way that D0 corresponds to A16 and D15 corresponds to A31 Because access to this register is comprised of a current register the value you get by reading this register is always the current value When DMA transfer finishes at which the Transfer Count Register underflows the value in this register if Address fixed is selected is the same destination address that was set i...

Page 250: ... 15 DM0TCT DM9TCT DMA transfer count ignored during 32 channel ring buffer mode The DMA Transfer Count Register is used to set the number of times data is transferred in each channel However the value in this register is ignored during ring buffer mode The transfer count is the value set in the transfer count register 1 Because the DMA Transfer Count Register is comprised of a current register the...

Page 251: ...n channels 0 4 If the DMAn interrupt request status bit n 0 to 4 is set to 1 it means that a DMAn interrupt request in the corresponding channel has been generated DMITSTn DMAn interrupt request status bit n 0 to 4 Setting the DMAn interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the DMAn interrupt request status bit This bit is cleared by wr...

Page 252: ...requests in channels 5 9 If the DMAn interrupt request status bit n 5 to 9 is set to 1 it means that a DMAn interrupt request in the corresponding channel has been generated DMITSTn DMAn interrupt request status bit n 5 to 9 Setting the DMAn interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the DMAn interrupt request status bit This bit is cle...

Page 253: ... DMA3 interrupt request mask 1 Masks disables interrupt request 13 DMITMK2 DMA2 interrupt request mask 14 DMITMK1 DMA1 interrupt request mask 15 DMITMK0 DMA0 interrupt request mask The DMA0 4 Interrupt Mask Register is used to mask interrupt requests in DMA channels 0 4 DMITMKn DMAn interrupt request mask bit n 0 to 4 DMAn interrupt request is masked by setting the DMAn interrupt request mask bit ...

Page 254: ...equest mask 1 Masks disables interrupt request 13 DMITMK7 DMA7 interrupt request mask 14 DMITMK6 DMA6 interrupt request mask 15 DMITMK5 DMA5 interrupt request mask The DMA5 9 Interrupt Mask Register is used to mask interrupt requests in DMA channels 5 9 DMITMKn DMAn interrupt request mask bit n 5 to 9 DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1 However when...

Page 255: ...upt 0 b3 DMITST4 F F DMITMK4 F F b11 b4 DMITST3 F F DMITMK3 F F b12 b5 DMITST2 F F DMITMK2 F F b13 b6 DMITST1 F F DMITMK1 F F b14 b7 DMITST0 F F DMITMK0 F F b15 DM04ITST H 0080 0400 DM04ITMK H 0080 0401 DMA4UDF DMA3UDF DMA2UDF DMA1UDF DMA0UDF Data bus DMA transfer interrupt 0 Level 5 source inputs ...

Page 256: ...upt 1 b3 DMITST9 F F DMITMK9 F F b11 b4 DMITST8 F F DMITMK8 F F b12 b5 DMITST7 F F DMITMK7 F F b13 b6 DMITST6 F F DMITMK6 F F b14 b7 DMITST5 F F DMITMK5 F F b15 DM59ITST H 0080 0408 DM59ITMK H 0080 0409 DMA9UDF DMA8UDF DMA7UDF DMA6UDF DMA5UDF Data bus DMA transfer interrupt 1 Level 5 source inputs ...

Page 257: ... DMA Requests in DMA0 and Generation Timings REQSL0 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA0 Software Request or one DMA2 transfer completed Generation Register software start or one DMA2 transfer is completed cascade mode 0 1 A D0 conversion completed When A D0 conversion is completed 1 0 MJT TIO8_udf When MJT TIO8 underflow occurs 1 1...

Page 258: ...quest DMA Request Generation Timing 0 0 Software start When any data is written to DMA3 Software Request Generation Register 0 1 Serial I O0 transmit buffer empty When serial I O0 transmit buffer is emptied 1 0 Serial I O1 reception completed When serial I O1 reception is completed 1 1 MJT TIN0 input signal When MJT s TIN0 input signal is generated Table 9 3 5 Causes of DMA Requests in DMA4 and Ge...

Page 259: ...ation Timings REQSL6 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA6 Software Request Generation Register 0 1 Serial I O1 transmit buffer empty When serial I O1 transmit buffer is emptied 1 0 MJT TIN1 input signal When MJT s TIN1 input signal is generated 1 1 One DMA5 transfer completed When one DMA5 transfer is completed cascade mode Table 9 ...

Page 260: ...eption completed When serial I O3 reception is completed 1 1 MJT TIN7 input signal When MJT s TIN7 input signal is generated Table 9 3 10 Causes of DMA Requests in DMA9 and Generation Timings REQSL9 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA9 Software Request Generation Register 0 1 Serial I O3 transmit buffer empty When serial I O3 transm...

Page 261: ...terrupt Request Status Register Set DMA0 Channel Control Register Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register Setting DMAC related registers Starting DMA transfer DMA transfer completed Transfers disabled Clears interrupt request status bit Set DMA0 4 Interrupt Mask Register Source address of transfer Address Number of times DMA transfer performed...

Page 262: ...nnels for which DMA transfers are requested the channel that has the highest priority is selected Channel selection is made every transfer cycle one DMA bus cycle consisting of three machine cycles 9 3 5 Gaining and Releasing Control of the Internal Bus For any channel control of the internal bus is gained and released in single transfer DMA mode In single transfer DMA the DMA gains control of the...

Page 263: ... DMA is the internal peripheral I O or 64 Kbytes of RAM space H 0080 0000 through H 0080 FFFF for either source or destination To set the source and destination addresses in each channel use the DMA Source Address Register and DMA Destination Address Register 9 3 9 Transfer Operation 1 Dual address transfer Irrespective of the size of transfer unit data is transferred in two bus cycles one for sou...

Page 264: ...ination address select bits When the transfer size is 16 bits the address is incremented by two for each DMA transfer performed when the transfer size is 8 bits the address is incremented by one Table 9 3 11 Address Count Direction and Address Changes Address Count Direction Transfer Unit Address Change for One DMA Address fixed 8 bits 0 16 bits 0 Address incremental 8 bits 1 16 bits 2 5 Transfer ...

Page 265: ...ransferred from even address to odd address or from odd address to even address When the transfer unit 8 bits the LSB of the address register D15 of the address register is ignored and data are always transferred in two bytes aligned to the 16 bit bus The diagram below shows the valid transfer byte positions Figure 9 3 3 Transfer Byte Positions D0 D7 D8 D15 8 bits 0 1 Source Destination When trans...

Page 266: ...re incremented by two at a time When as transfer proceeds the six low order bits reach B 111110 they are recycled to B 000000 by the next increment operation thus returning to the start address again When the source address has been set to be incremented it is the source address that recycles to the start address when the destination address has been set to be incremented it is the destination add...

Page 267: ...r completed interrupt request is not generated Nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit 9 3 11 Status of Each Register after Completion of DMA Transfer When DMA transfer is completed the status of the source address and destination address registers becomes as follows 1 Address fixed The value set in the addres...

Page 268: ...r is enabled When transfer is disabled Can be accessed Cannot be accessed For even registers that can exceptionally be written to while transfer is enabled the following requirements must be met DMA Channel Control Register s transfer enable bit and transfer request flag For all other bits of the channel control register be sure to write the same data that those bits had before you wrote to the tr...

Page 269: ... rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0 About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register be sure to write 1s to all bits but the one you want to clear The bits to which you wrote 1s retain the previous data they had before the write About the stable operation of DMA...

Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...

Page 271: ...n Units of Multijunction Timer 10 3 TOP Output related 16 bit Timer 10 4 TIO Input Output related 16 bit Timer 10 5 TMS Input related 16 bit Timer 10 6 TML Input related 32 bit Timer 10 7 TID Input related 16 bit Timer 10 8 TOD Output related 16 bit Timer 10 9 TOM Output related 16 bit Timer ...

Page 272: ...hannels Description TOP Output related 11 One of three output modes can be selected by software Timer Output 16 bit timer With correction function down counter Single shot output mode Delayed single shot output mode Without correction function Continuous output mode TIO Input output related 10 One of three input modes or four output modes can be Timer 16 bit timer selected by software Input Output...

Page 273: ...able 10 1 2 MJT Interrupt Generation Functions of the M32170 Signal Name Source of MJT Interrupt Requested Interrupt Controller ICU Input ICU Cause Input IRQ18 TIN30 TIN33 input TML1 input interrupt 4 IRQ17 TID2 output TID2 output interrupt 1 IRQ16 TOD1_0 TOD1_7 output TOD1 TOM0 output interrupt 16 TOM0_0 TOM0_7 output IRQ15 TID1 output TID1 output interrupt 1 IRQ14 TID0 output TID0 output interru...

Page 274: ...nput Channel 4 DRQ7 TIN0 input Channel 3 DRQ8 TIN1 input Channel 6 DRQ9 TIN2 input Channel 7 DRQ10 TIN7 input Channel 8 DRQ11 TIN8 input Channel 9 DRQ12 TIN20 input Channel 5 DRQ13 Input event bus 0 Channel 8 Table 10 1 4 A D Conversion Start Request by MJT Signal Name Source of A D Conversion Start Requested A D Converter AD0TRG Output event bus 3 Can be input to A D0 conversion start trigger AD1...

Page 275: ...IRQ9 TIN1 IRQ9 TIN2 S S clk en udf TOP 8 clk en udf TOP 9 clk en udf TOP 10 clk en cap udf TIO 0 clk en cap udf TIO 1 clk en cap udf TIO 2 clk en cap udf TIO 3 clk en cap udf TIO 4 S S TIN3 S S TIN4 TIN5 S S IRQ12 TIN6 PSC1 PSC0 clk en cap udf TIO 5 S S IRQ8 TIN8 TCLK2 clk en cap udf TIO 6 S S IRQ8 TIN9 clk en cap udf TIO 7 S S IRQ8 TIN10 S S clk en cap udf TIO 8 clk en cap udf TIO 9 IRQ8 TIN11 S ...

Page 276: ...RQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 clk TML0 cap3 cap2 cap1 cap0 S S S S TIN20 TIN21 TIN22 TIN23 IRQ11 IRQ11 IRQ11 IRQ11 IRQ7 IRQ7 TIN12S TIN13S TIN14S TIN15S TIN16S TIN17S TIN18S TIN19S TIN20S TIN21S TIN22S TIN23S S DRQ12 clk TML1 cap3 cap2 cap1 cap0 S S S S TIN30 TIN31 TIN32 TIN33 TIN30S TIN31S TIN32S TIN33S S IRQ18 IRQ18 IRQ18 IRQ18 S Selector 3 21 0 3 21 0 0 12 3 Clock bus Input event bus Outpu...

Page 277: ...32 clk TOD1_4 udf F F33 clk TOD1_5 udf F F34 TO33 TO34 clk TOD1_6 udf F F35 clk TOD1_7 udf F F36 TO35 TO36 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 CLK1 CLK2 PSC4 clk TID2 TIN28 TIN29 clk TOM0_0 udf F F37 clk TOM0_1 udf F F38 TO37 TO38 clk TOM0_2 udf F F39 clk TOM0_3 udf F F40 TO39 TO40 clk TOM0_4 udf F F41 clk TOM0_5 udf F F42 TO41 TO42 clk TOM0_6 udf F F43 clk TOM0_7 udf F F44 TO43 TO44 I...

Page 278: ...RQ1 SIO2 RXD SIO1 TXD DMAIRQ1 DMAIRQ1 SIO2 TXD SIO3 RXD DMAIRQ1 SIO3 TXD TIN2 TIN7 TIN8 TIN20 TIN1 TIN0 S DMAIRQ0 S S S S Clock bus Input event bus Output event bus 3 2 1 0 3 21 0 3 21 0 0 12 3 0 1 2 3 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 DMA5 udf end DMA7 udf end DMA6 ...

Page 279: ...units of the multijunction timer include the following Prescaler unit Clock bus input output event bus control unit Input processing control unit Output flip flop control unit Interrupt control unit 10 2 1 Timer Common Register Map The diagrams in the next pages show a map of registers in the common units of the multijunction timer ...

Page 280: ...Prescaler Register 0 PRS0 Prescaler Register 1 PRS1 TCLK Input Processing Control Register TCLKCR H 0080 0202 TIN Input Processing Control Register 2 TINCR2 TIN Input Processing Control Register 3 TINCR3 F F Source Select Register 0 FFS0 F F Protect Register 1 FFP1 TOP Interrupt Control Register 2 TOPIR2 TOP Interrupt Control Register 3 TOPIR3 TOP Interrupt Control Register 0 TOPIR0 TOP Interrupt ...

Page 281: ... 4 Enable Register TID1PRS4EN H 0080 0BD2 TOD1 Interrupt Mask Register TOD1IMA TOD1 Interrupt Status Register TOD1IST H 0080 0BD4 F F Protect Register 3 FFP3 H 0080 0BD6 F F Data Register 3 FFD3 H 0080 0CD0 Prescaler Register 5 PRS5 TID2 Control Prescaler 5 Enable Register TID2PRS5EN H 0080 0CD2 TOM0 Interrupt Mask Register TOM0IMA TOM0 Interrupt Status Register TOM0IST H 0080 0CD4 F F Protect Reg...

Page 282: ...tion below 1 Prescaler divide by ratio Prescaler set value 1 Prescaler Register 0 PRS0 Address H 0080 0202 Prescaler Register 1 PRS1 Address H 0080 0203 Prescaler Register 2 PRS2 Address H 0080 0204 Prescaler Register 3 PRS3 Address H 0080 07D0 Prescaler Register 4 PRS4 Address H 0080 0BD0 Prescaler Register 5 PRS5 Address H 0080 0CD0 D0 1 2 3 4 5 6 D7 D8 9 10 11 12 13 14 D15 PRS0 PRS5 When reset ...

Page 283: ...ernal prescaler PSC2 or TCLK3 input 1 Internal prescaler PSC1 0 Internal prescaler PSC0 2 Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer and is comprised of four lines of input event bus 0 3 Each timer can use this input event bus signal as enable or capture signal input The table below lists the signals that can be fed t...

Page 284: ...ey are generated at different timings than those forwarded to output flip flops by timers Table 10 2 4 Timings at Which Signals Are Generated to the Output Event Bus by Each Timer 1 2 Timer Mode Timings at which signals are generated to the output event bus TOP Single shot output mode When the counter underflows Delayed single shot output mode When the counter underflows Continuous output mode Whe...

Page 285: ...le shot output mode No signal generation function Continuous output mode No signal generation function Figure 10 2 3 Conceptual Diagram of the Clock Bus and Input Output Event Bus TCLK0S TCLK0 TIN0 TIN2 TIN3 TIN4 TIN5 TIN6 PSC1 PSC0 PSC2 TCLK3 udf TIO 5 udf TIO 6 S udf TIO 7 udf TOP 6 udf TOP 7 udf TOP 8 udf TOP 9 udf TIO 0 udf TIO 1 udf TIO 2 udf TIO 3 udf TIO 4 udf TIO 8 TCLK3S TIN0S TIN2S TIN3S...

Page 286: ...event bus 2 11 Selects TIO7 output 10 11 IEB2S 00 Selects external input 0 TIN0 input event bus 2 input selection 01 Selects external input 2 TIN2 1X Selects external input 4 TIN4 12 IEB1S 0 Selects external input 5 TIN5 input event bus 1 input selection 1 Selects TIO6 output 13 IEB0S 0 Selects external input 6 TIN6 input event bus 0 input selection 1 Selects TIO5 output 14 No functions assigned 0...

Page 287: ...output 10 Selects TIO4 output 11 Selects TIO8 output 10 No functions assigned 0 11 OEB2S 0 Selects TOP9 output output event bus 2 input selection 1 Selects TIO2 output 12 No functions assigned 0 13 OEB1S 0 Selects TOP7 output output event bus 1 input selection 1 Selects TIO1 output 14 No functions assigned 0 15 OEB0S 0 Selects TOP6 output output event bus 0 input selection 1 Selects TIO0 output Th...

Page 288: ...clock signal fed to the clock bus In the TIN input processing unit selection is made of the active edge rising or falling or both or level high or low of the signal at which to generate the enable measure or count source signal for each timer or the signal fed to each event bus Following input processing control registers are included TCLK Input Processing Control Register TCLKCR TIN Input Process...

Page 289: ... control registers Item Function 1 2 internal peripheral clock Rising clock edge Falling clock edge Both edges Low level High level Count clock 1 2 internal peripheral clock TCLK Count clock TCLK Count clock TCLK Count clock TCLK Count clock 1 2 internal peripheral clock TCLK Count clock 1 2 internal peripheral clock ...

Page 290: ... input processing control registers Item Function Rising edge Falling edge Both edges Low level High level TIN Internal edge signal TIN Internal edge signal TIN Internal edge signal TCLK PSC x clock width or TCLK x input Internal edge signal TIN Internal edge signal PSC x clock width or TCLK x input ...

Page 291: ... 000 Invalidates input TCLK2 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 8 No functions assigned 0 9 11 TCLK1S 000 Invalidates input TCLK1 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 12 13 No functions assigned 0 14 15 TCLK0S 00 1 2 internal peripheral clock TCLK0 input 01 Rising...

Page 292: ...alidates input TIN3 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 8 9 No functions assigned 0 10 11 TIN2S 00 Invalidates input TIN2 input 01 Rising edge processing selection 10 Falling edge 11 Both edges 12 13 TIN1S 00 Invalidates input TIN1 input 01 Rising edge processing selection 10 Falling edge 11 Both edges 14 15 TIN0S 00 Invalidates i...

Page 293: ...000 Invalidates input TIN7 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 8 No functions assigned 0 9 11 TIN6S 000 Invalidates input TIN6 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 12 No functions assigned 0 13 15 TIN5S 000 Invalidates input TIN5 input 001 Rising edge processing se...

Page 294: ...e 011 Both edges 10X Low level 11X High level 8 No functions assigned 0 9 11 TIN10S 000 Invalidates input TIN10 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 12 No functions assigned 0 13 15 TIN9S 000 Invalidates input TIN9 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level Note This regi...

Page 295: ...cessing selection Note This register must always be accessed in halfwords TIN Input Processing Control Register 4 TINCR4 Address H 0080 021A TIN Input Processing Control Register 3 TINCR3 Address H 0080 0218 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TIN33S TIN32S TIN31S TIN30S TIN23S TIN22S TIN21S TIN20S When reset H 0000 D Bit Name Function R W 0 1 TIN33S TIN33 input processing selection 00 Invalid...

Page 296: ...F Source Select Register 1 FFS1 F F Protect Register 0 FFP0 F F Protect Register 1 FFP1 F F Protect Register 2 FFP2 F F Protect Register 3 FFP3 F F Protect Register 4 FFP4 F F Data Register 0 FFD0 F F Data Register 1 FFD1 F F Data Register 2 FFD2 F F Data Register 3 FFD3 F F Data Register 4 FFD4 Timings at which signals are generated to the output flip flop by each timer are shown in Table 10 2 5 ...

Page 297: ...underflows Delayed single shot output mode When counter underflows Continuous output mode When counter is enabled and when underflows TMS 16 bit measure input No signal generation function TML 32 bit measure input No signal generation function TID Fixed period count mode No signal generation function Event count mode No signal generation function Multiply by 4 event count mode No signal generation...

Page 298: ...of Multijunction Timer Output event bus 0 Dn F F protect FPn WR Dn Output control ON OFF TOn Internal edge signal Port operation mode register PnMOD F Fn output data FDn TOP TIO TOD TOM udf F F source selection FFn Output event bus 1 Output event bus 2 Output event bus 3 Note Dn denotes the data bus F F F F F F ...

Page 299: ...urce selection 0 TIO1 output 1 Output event bus 2 7 FF11 F F11 source selection 0 TIO0 output 1 Output event bus 1 8 9 FF10 F F10 source selection 0X TOP10 output 10 Output event bus 0 11 Output event bus 1 10 11 FF9 F F9 source selection 0X TOP9 output 10 Output event bus 0 11 Output event bus 1 12 13 FF8 F F8 source selection 00 TOP8 output 01 Output event bus 0 10 Output event bus 1 11 Output e...

Page 300: ...0 11 FF18 F F18 source selection 0X TIO7 output 10 Output event bus 0 11 Output event bus 1 12 13 FF17 F F17 source selection 0X TIO6 output 10 Output event bus 0 11 Output event bus 1 14 15 FF16 F F16 source selection 00 TIO5 output 01 Output event bus 0 10 Output event bus 1 11 Output event bus 3 The registers FFS0 and FFS1 are used to select the signal sources fed to each output F F flip flop F...

Page 301: ...tect 3 FP12 F F12 protect 4 FP11 F F11 protect 5 FP10 F F10 protect 6 FP9 F F9 protect 7 FP8 F F8 protect 8 FP7 F F7 protect 9 FP6 F F6 protect 10 FP5 F F5 protect 11 FP4 F F4 protect 12 FP3 F F3 protect 13 FP2 F F2 protect 14 FP1 F F1 protect 15 FP0 F F0 protect Note This register must always be accessed in halfwords This register controls write to each output F F flip flop by enabling or disabli...

Page 302: ...ddress H 0080 07D5 F F Protect Register 1 FFP1 Address H 0080 0229 D8 9 10 11 12 13 14 D15 FP21 FP22 FP23 FP24 FP25 FP26 FP27 FP28 When reset H 00 D Bit Name Function R W 8 FP21 F F21 protect 0 Enables write to F F output bit 9 FP22 F F22 protect 1 Disables write to F F output bit 10 FP23 F F23 protect 11 FP24 F F24 protect 12 FP25 F F25 protect 13 FP26 F F26 protect 14 FP27 F F27 protect 15 FP28 ...

Page 303: ...Protect Register 4 FFP4 Address H 0080 0CD5 F F Protect Register 3 FFP3 Address H 0080 0BD5 D8 9 10 11 12 13 14 D15 FP37 FP38 FP39 FP40 FP41 FP42 FP43 FP44 When reset H 00 D Bit Name Function R W 8 FP37 F F37 protect 0 Enables write to F F output bit 9 FP38 F F38 protect 1 Disables write to F F output bit 10 FP39 F F39 protect 11 FP40 F F40 protect 12 FP41 F F41 protect 13 FP42 F F42 protect 14 FP...

Page 304: ... FD8 F F8 output data 8 FD7 F F7 output data 9 FD6 F F6 output data 10 FD5 F F5 output data 11 FD4 F F4 output data 12 FD3 F F3 output data 13 FD2 F F2 output data 14 FD1 F F1 output data 15 FD0 F F0 output data Note This register must always be accessed in halfwords This register is used to set data in each output F F flip flop Normally the data output from F F changes with timer output but by se...

Page 305: ...2 13 14 D15 FD21 FD22 FD23 FD24 FD25 FD26 FD27 FD28 When reset H 00 D Bit Name Function R W 8 FD21 F F21 output data 0 F F output data 0 9 FD22 F F22 output data 1 F F output data 1 10 FD23 F F23 output data 11 FD24 F F24 output data 12 FD25 F F25 output data 13 FD26 F F26 output data 14 FD27 F F27 output data 15 FD28 F F28 output data This register is used to set data in each output F F flip flop...

Page 306: ...ddress H 0080 0BD7 D8 9 10 11 12 13 14 D15 FD37 FD38 FD39 FD40 FD41 FD42 FD43 FD44 When reset H 00 D Bit Name Function R W 8 FD37 F F37 output data 0 F F output data 0 9 FD38 F F38 output data 1 F F output data 1 10 FD39 F F39 output data 11 FD40 F F40 output data 12 FD41 F F41 output data 13 FD42 F F42 output data 14 FD43 F F43 output data 15 FD44 F F44 output data This register is used to set da...

Page 307: ...INIR1 TIN Interrupt Control Register 2 TINIR2 TIN Interrupt Control Register 3 TINIR3 TIN Interrupt Control Register 4 TINIR4 TIN Interrupt Control Register 5 TINIR5 TIN Interrupt Control Register 6 TINIR6 TIN Interrupt Control Register 7 TINIR7 TOD0 Interrupt Mask Register TOD0IMA TOD0 Interrupt Status Register TOD0IST TOD1 Interrupt Mask Register TOD1IMA TOD1 Interrupt Status Register TOD1IST TO...

Page 308: ...atus bit is cleared by writing a 0 but not affected by writing a 1 in which case the bit holds the status intact Because the status bit is unaffected by interrupt mask bits it can also be used to check the operation of peripheral function In interrupt processing make sure that among grouped interrupt flags only the flag for the serviced interrupt is cleared Clearing flags for unserviced interrupts...

Page 309: ...Example for Clearing the Interrupt Status b4 5 6 b7 Interrupt status flag Initial state b6 event occurred Interrupt request b4 event occurred Only b6 cleared b4 data retained b4 5 6 b7 1 1 0 1 Write to the interrupt status Example for clearing the interrupt status 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 ...

Page 310: ...7 TMS0 TMS1 MJT output interrupt 7 2 IRQ8 TIN7 TIN8 TIN9 TIN10 TIN11 MJT input interrupt 0 5 IRQ9 TIN0 TIN1 TIN2 MJT input interrupt 1 3 IRQ10 TIN12 TIN13 TIN14 TIN15 TIN16 MJT input interrupt 2 8 TIN17 TIN18 TIN19 IRQ11 TIN20 TIN21 TIN22 TIN23 MJT input interrupt 3 4 IRQ12 TIN3 TIN4 TIN5 TIN6 MJT input interrupt 4 4 IRQ13 TOD0_0 TOD0_1 TOD0_2 TOD0_3 TOD0 output interrupt 8 TOD0_4 TOD0_5 TOD0_6 TO...

Page 311: ...tus 7 TOPIS0 TOP0 interrupt status W Only writing a 0 is effective when you write a 1 the previous value is retained TOP Interrupt Control Register 1 TOPIR1 Address H 0080 0231 TOP Interrupt Control Register 0 TOPIR0 Address H 0080 0230 D8 9 10 11 12 13 14 D15 TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0 When reset H 00 D Bit Name Function R W 8 9 No functions assigned 0 10 TOPIM5 TOP5 interrupt mask...

Page 312: ...errupt 2 MJT output interrupt 2 IRQ2 Data bus b2 TOPIS5 F F TOPIM5 F F b10 b3 TOPIS4 F F TOPIM4 F F b11 b4 TOPIS3 F F TOPIM3 F F b12 b5 TOPIS2 F F TOPIM2 F F b13 b6 TOPIS1 F F TOPIM1 F F b14 b7 TOPIS0 F F TOPIM0 F F b15 Level 6 source inputs TOPIR0 H 0080 0230 TOPIR1 H 0080 0231 TOP5udf TOP4udf TOP3udf TOP2udf TOP1udf TOP0udf ...

Page 313: ...nerated 4 5 No functions assigned 0 6 TOPIM7 TOP7 interrupt mask 0 Enables interrupt request 7 TOPIM6 TOP6 interrupt mask 1 Masks disables interrupt request W Only writing a 0 is effective when you write a 1 the previous value is retained TOP Interrupt Control Register 2 TOPIR2 Address H 0080 0232 Figure 10 2 8 Block Diagram of MJT Output Interrupt 1 b2 TOPIS7 F F TOPIM7 F F b6 b3 TOPIS6 F F TOPIM...

Page 314: ...IM8 TOP8 interrupt mask 1 Masks disables interrupt request W Only writing a 0 is effective when you write a 1 the previous value is retained Note For TOP10 there are no interrupt status and mask bits in MJT interrupt control registers because it only has one source of interrupt in the group It is controlled directly by the interrupt controller TOP Interrupt Control Register 3 TOPIR3 Address H 0080...

Page 315: ...3 interrupt mask 0 Enables interrupt request 5 TIOIM2 TIO2 interrupt mask 1 Masks disables interrupt request 6 TIOIM1 TIO1 interrupt mask 7 TIOIM0 TIO0 interrupt mask W Only writing a 0 is effective when you write a 1 the previous value is retained TIO Interrupt Control Register 0 TIOIR0 Address H 0080 0234 Figure 10 2 10 Block Diagram of MJT Output Interrupt 0 b0 TIOIS3 F F TIOIM3 F F b4 b1 TIOIS...

Page 316: ... interrupt mask 0 Enables interrupt request 13 TIOIM6 TIO6 interrupt mask 1 Masks disables interrupt request 14 TIOIM5 TIO5 interrupt mask 15 TIOIM4 TIO4 interrupt mask W Only writing a 0 is effective when you write a 1 the previous value is retained TIO Interrupt Control Register 1 TIOIR1 Address H 0080 0235 Figure 10 2 11 Block Diagram of MJT Output Interrupt 4 b8 TIOIS7 F F TIOIM7 F F b12 b9 TI...

Page 317: ...nerated 4 5 No functions assigned 0 6 TIOIM9 TIO9 interrupt mask 0 Enables interrupt request 7 TIOIM8 TIO8 interrupt mask 1 Masks disables interrupt request W Only writing a 0 is effective when you write a 1 the previous value is retained TIO Interrupt Control Register 2 TIOIR2 Address H 0080 0236 Figure 10 2 12 Block Diagram of MJT Output Interrupt 3 b2 TIOIS9 F F TIOIM9 F F b6 b3 TIOIS8 F F TIOI...

Page 318: ...generated 12 13 No functions assigned 0 14 TMSIM1 TMS1 interrupt mask 0 Enables interrupt request 15 TMSIM0 TMS0 interrupt mask 1 Masks disables interrupt request W Only writing a 0 is effective when you write a 1 the previous value is retained TMS Interrupt Control Register TMSIR Address H 0080 0237 Figure 10 2 13 Block Diagram of MJT Output Interrupt 7 b10 TMSIS1 F F TMSIM1 F F b14 b11 TMSIS0 F ...

Page 319: ...o functions assigned 0 5 TINIM2 TIN2 interrupt mask 0 Enables interrupt request 6 TINIM1 TIN1 interrupt mask 1 Masks disables interrupt request 7 TINIM0 TIN0 interrupt mask W Only writing a 0 is effective when you write a 1 the previous value is retained TIN Interrupt Control Register 0 TINIR0 Address H 0080 0238 Figure 10 2 14 Block Diagram of MJT Input Interrupt 1 b1 TINIS2 F F TINIM2 F F b5 b2 ...

Page 320: ... interrupt mask 0 Enables interrupt request 13 TINIM5 TIN5 interrupt mask 1 Masks disables interrupt request 14 TINIM4 TIN4 interrupt mask 15 TINIM3 TIN3 interrupt mask W Only writing a 0 is effective when you write a 1 the previous value is retained TIN Interrupt Control Register 1 TINIR1 Address H 0080 0239 Figure 10 2 15 Block Diagram of MJT Input Interrupt 4 b8 TINIS6 F F TINIM6 F F b12 b9 TIN...

Page 321: ...us 7 TINIS7 TIN7 interrupt status W Only writing a 0 is effective when you write a 1 the previous value is retained TIN Interrupt Control Register 3 TINIR3 Address H 0080 023B TIN Interrupt Control Register 2 TINIR2 Address H 0080 023A D8 9 10 11 12 13 14 D15 TINIM11 TINIM10 TINIM9 TINIM8 TINIM7 When reset H 00 D Bit Name Function R W 8 9 10 No functions assigned 0 11 TINIM11 TIN11 interrupt mask ...

Page 322: ...of Multijunction Timer b3 TINIS11 F F TINIM11 F F b11 b4 TINIS10 F F TINIM4 F F b12 b5 TINIS9 F F TINIM9 F F b13 b6 TINIS8 F F TINIM8 F F b14 b7 TINIS7 F F TINIM7 F F b15 TINIR2 H 0080 023A TINIR3 H 0080 023B TIN11edge TIN10edge TIN9edge TIN8edge TIN7edge Data bus MJT input interrupt 0 IRQ8 Level 5 source inputs ...

Page 323: ...tus 7 TINIS12 TIN12 interrupt status W Only writing a 0 is effective when you write a 1 the previous value is retained TIN Interrupt Control Register 5 TINIR5 Address H 0080 023D TIN Interrupt Control Register 4 TINIR4 Address H 0080 023C D8 9 10 11 12 13 14 D15 TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12 When reset H 00 D Bit Name Function R W 8 TINIM19 TIN19 interrupt mask 0 ...

Page 324: ...F TINIM18 F F b9 b2 TINIS17 F F TINIM17 F F b10 b3 TINIS16 F F TINIM16 F F b11 b4 TINIS15 F F TINIM15 F F b12 TINIR4 H 0080 023C TINIR5 H 0080 023D TIN19edge TIN18edge TIN17edge TIN16edge TIN15edge b5 TINIS14 F F TINIM14 F F b13 b6 TINIS13 F F TINIM13 F F b14 b7 TINIS12 F F TINIM12 F F b15 TIN14edge TIN13edge TIN12edge Data bus MJT input interrupt 2 IRQ10 Level 8 source inputs ...

Page 325: ...interrupt mask 0 Enables interrupt request 5 TINIM22 TIN22 interrupt mask 1 Masks disables interrupt request 6 TINIM21 TIN21 interrupt mask 7 TINIM20 TIN20 interrupt mask W Only writing a 0 is effective when you write a 1 the previous value is retained Figure 10 2 18 Block Diagram of MJT Input Interrupt 3 TIN Interrupt Control Register 6 TINIR6 Address H 0080 023E b0 TINIS23 F F TINIM23 F F b4 b1 ...

Page 326: ...request 14 TINIM31 TIN31 interrupt mask 15 TINIM30 TIN30 interrupt mask W Only writing a 0 is effective when you write a 1 the previous value is retained Note For TIN24 TIN29 there are no interrupt status and mask bits in MJT interrupt control registers because they do not have interrupt functions TIN Interrupt Control Register 7 TINIR7 Address H 0080 023F Figure 10 2 19 Block Diagram of TML1 Inpu...

Page 327: ...7 TOD00IMA TOD0_0 interrupt mask TOD0 Interrupt Status Register TOD0IST Address H 0080 07D3 TOD0 Interrupt Mask Register TOD0IMA Address H 0080 07D2 D8 9 10 11 12 13 14 D15 TOD07IST TOD06IST TOD05IST TOD04IST TOD03IST TOD02IST TOD01IST TOD00IST When reset H 00 D Bit Name Function R W 8 TOD07IST TOD0_7 interrupt status 0 No interrupt request 9 TOD06IST TOD0_6 interrupt status 1 Interrupt request ge...

Page 328: ...OD06IMA F F b1 b10 TOD05IST F F TOD05IMA F F b2 b11 TOD04IST F F TOD04IMA F F b3 b12 TOD03IST F F TOD03IMA F F b4 TOD0IMA H 0080 07D2 TOD0IST H 0080 07D3 TOD07udf TOD06udf TOD05udf TOD04udf TOD03udf b13 TOD02IST F F TOD02IMA F F b5 b14 TOD01IST F F TOD01IMA F F b6 b15 TOD00IST F F TOD00IMA F F b7 TOD02udf TOD01udf TOD00udf Data bus TOD0 output interrupt 2 IRQ13 Level 8 source inputs ...

Page 329: ...7 TOD10IMA TOD1_0 interrupt mask TOD1 Interrupt Status Register TOD1IST Address H 0080 08D3 TOD1 Interrupt Mask Register TOD1IMA Address H 0080 08D2 D8 9 10 11 12 13 14 D15 TOD17IST TOD16IST TOD15IST TOD14IST TOD13IST TOD12IST TOD11IST TOD10IST When reset H 00 D Bit Name Function R W 8 TOD17IST TOD1_7 interrupt status 0 No interrupt request 9 TOD16IST TOD1_6 interrupt status 1 Interrupt request ge...

Page 330: ...7 TOM00IMA TOM0_0 interrupt mask TOM0 Interrupt Status Register TOM0IST Address H 0080 0CD3 TOM0 Interrupt Mask Register TOM0IMA Address H 0080 0CD2 D8 9 10 11 12 13 14 D15 TOM07IST TOM06IST TOM05IST TOM04IST TOM03IST TOM02IST TOM01IST TOM00IST When reset H 00 D Bit Name Function R W 8 TOM07IST TOM0_7 interrupt status 0 No interrupt request 9 TOM06IST TOM0_6 interrupt status 1 Interrupt request ge...

Page 331: ...10 TOD15IST F F TOD15IMA F F b2 b11 TOD14IST F F TOD14IMA F F b3 b12 TOD13IST F F TOD13IMA F F b4 TOD1IMA H 0080 0BD2 TOD1IST H 0080 0BD3 TOD17udf TOD16udf TOD15udf TOD14udf TOD13udf b13 TOD12IST F F TOD12IMA F F b5 b14 TOD11IST F F TOD11IMA F F b6 b15 TOD10IST F F To 8 input sources in the next page F F b7 TOD12udf TOD11udf TOD10udf TOD10IMA Data bus TOD1 TOM0 output interrupt IRQ16 Level 16 sour...

Page 332: ...0 b9 TOM06IST F F TOM06IMA F F b1 b10 TOM05IST F F TOM05IMA F F b2 b11 TOM04IST F F TOM04IMA F F b3 b12 TOM03IST F F TOM03IMA F F b4 TOM0IMA H 0080 0CD2 TOM0IST H 0080 0CD3 TOM07udf TOM06udf TOM05udf TOM04udf TOM03udf b13 TOM02IST F F TOM02IMA F F b5 b14 TOM01IST F F TOM01IMA F F b6 b15 TOM00IST F F F F b7 TOM02udf TOM01udf TOM00udf TOM00IMA To the preceding page Data bus ...

Page 333: ...m in the next page shows a block diagram of TOP Table 10 3 1 Specifications of TOP Output related 16 bit Timer Item Specification Number of channels 11 channels Counter 16 bit down counter Reload register 16 bit reload register Correction register 16 bit correction register Timer startup Started by writing to enable bit in software or by enabling with external input rising or falling edge or both ...

Page 334: ... udf TOP 4 clk en udf TOP 5 TCLK0 TIN0 S S TIN0S clk en udf TOP 6 clk en udf TOP 7 S S S IRQ9 TIN1 IRQ9 TIN2 S S clk en udf TOP 8 clk en udf TOP 9 clk en udf TOP 10 F F0 F F1 F F2 F F3 F F4 F F5 F F6 F F7 F F8 F F9 F F10 S Selector F F Output flip flop S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 TO 2 TO 3 TO 4 TO 5 TO 6 TO 7 TO 8 TO 9 TO 10 IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 3 2 1 0 0 1 2 3 TIN1S TIN2S Reload r...

Page 335: ...ad register set value 1 only once with the output delayed by an amount of time equal to counter set value 1 and then stops without performing any operation When after setting the counter and reload register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock The first time the cou...

Page 336: ...ount is reached generates an underflow This underflow causes the counter to be reloaded with the content of the reload register and start counting over again Thereafter this operation is repeated each time an underflow occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted at startup and upon underflow generat...

Page 337: ...80 0256 H 0080 0260 H 0080 0262 H 0080 0264 H 0080 0266 H 0080 0270 H 0080 0272 H 0080 0274 H 0080 0276 TOP0 Counter TOP0CT TOP0 Reload Register TOP0RL TOP0 Correction Register TOP0CC Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TOP1 Counter TOP1CT TOP1 Reload Register TOP1RL TOP1 Correction Register TOP1CC TOP2 Counter TOP2CT TOP2 R...

Page 338: ...rol Register 0 TOP05CR0 TOP0 5 Control Register 1 TOP05CR1 H 0080 02AA H 0080 02A8 Address 0 Address 1 Address TOP4 Counter TOP4CT TOP4 Reload Register TOP4RL TOP4 Correction Register TOP4CC TOP5 Counter TOP5CT TOP5 Reload Register TOP5RL TOP5 Correction Register TOP5CC TOP6 7 Control Register TOP67CR TOP6 Counter TOP6CT TOP6 Reload Register TOP6RL TOP6 Correction Register TOP6CC TOP7 Counter TOP7...

Page 339: ... Control Register TOP810CR H 0080 02E8 TOP0 10 Enable Protect Register TOPPRO TOP0 10 Count Enable Register TOPCEN Address 0 Address 1 Address TOP8 Counter TOP8CT TOP8 Reload Register TOP8RL TOP8 Correction Register TOP8CC Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TOP9 Counter TOP9CT TOP9 Reload Register TOP9RL TOP9 Correction Reg...

Page 340: ...t operation modes of TOP0 10 single shot delayed single shot or continuous mode as well as select the counter enable and counter clock sources Following four TOP control registers are provided for each timer group TOP0 5 Control Register 0 TOP05CR0 TOP0 5 Control Register 1 TOP05CR1 TOP6 7 Control Register TOP67CR TOP8 10 Control Register TOP810CR ...

Page 341: ...utput mode 2 3 TOP2M TOP2 operation mode selection 01 Delayed single shot output mode 4 5 TOP1M TOP1 operation mode selection 1X Continuous output mode 6 7 TOP0M TOP0 operation mode selection 8 No functions assigned 0 9 10 TOP05ENS 0XX External TIN0 input TOP0 5 enable source selection 100 Input event bus 0 101 Input event bus 1 110 Input event bus 2 111 Input event bus 3 12 13 No functions assign...

Page 342: ...P0 5 Clock Enable Inputs When reset H 00 D Bit Name Function R W 8 11 No functions assigned 0 12 13 TOP5M TOP5 operation mode selection 00 Single shot output mode 14 15 TOP4M TOP4 operation mode selection 01 Delayed single shot output mode 1X Continuous output mode clk en TOP 0 Clock bus Input event bus clk en TOP 1 clk en TOP 2 clk en TOP 3 3 2 1 0 clk en TOP 4 clk en TOP 5 S S Selector TIN0 S TI...

Page 343: ...by TOP67ENS bit TOP7 enable source selection 1 TOP6 output 2 3 TOP7M TOP7 operation mode selection 00 Single shot output mode 01 Delayed single shot output mode 1X Continuous output mode 4 5 No functions assigned 0 6 7 TOP6M TOP6 operation mode selection 00 Single shot output mode 01 Delayed single shot output mode 1X Continuous output mode 8 No functions assigned 0 9 11 TOP67ENS 0XX External TIN1...

Page 344: ...it Timer Figure 10 3 6 Outline Diagram of TOP6 TOP7 Clock Enable Inputs 3 2 1 0 clk en udf TOP 6 clk en udf TOP 7 S S TIN1S TIN1 S 3 2 1 0 S Clock bus Input event bus Selector Note This diagram is shown for the explanation of TOP control registers and is partly omitted ...

Page 345: ...OP810CKS TOP 810 ENS When reset H 0000 D Bit Name Function R W 0 1 No functions assigned 0 2 3 TOP10M TOP10 operation mode selection 00 Single shot output mode 4 5 TOP9M TOP9 operation mode selection 01 Delayed single shot output mode 6 7 TOP8M TOP8 operation mode selection 1X Continuous output mode 8 10 No functions assigned 0 11 TOP810ENS 0 External TIN2 input TOP8 10 enable source selection 1 I...

Page 346: ...t Timer Figure 10 3 7 Outline Diagram of TOP8 10 Clock Enable Inputs 3 2 1 0 TIN2 TIN2S S S clk en TOP 8 clk en TOP 9 clk en TOP 10 S 3 2 1 0 Clock bus Input event bus Selector Note This diagram is shown for the explanation of TOP control registers and is partly omitted ...

Page 347: ...dress H 0080 02A0 TOP7 Counter TOP7CT Address H 0080 02B0 TOP8 Counter TOP8CT Address H 0080 02C0 TOP9 Counter TOP9CT Address H 0080 02D0 TOP10 Counter TOP10CT Address H 0080 02E0 Note This register must always be accessed in halfwords The TOP counters are a 16 bit down counter After the timer is enabled by writing to the enable bit in software or by external input the counter starts counting sync...

Page 348: ...2 TOP10 Reload Register TOP10RL Address H 0080 02E2 Note This register must always be accessed in halfwords The TOP reload registers are used to load data into the TOP counter registers TOP0CT TOP10CT It is in the following cases that the content of the reload register is loaded in the counter When the counter is enabled in single shot mode When the counter underflowed in delayed single shot or co...

Page 349: ... Note This register must always be accessed in halfwords The TOP correction registers are used to correct the TOP counter value by adding or subtracting it in the middle of operation To increase or reduce the counter value write a value to this correction register the value by which you want to be increased or reduced from the initial count set in the counter To add write the value you want to add...

Page 350: ...d 0 5 TOP10EEN TOP10 external enable permit 0 Disables external enable 6 TOP9EEN TOP9 external enable permit 1 Enables external enable 7 TOP8EEN TOP8 external enable permit 8 TOP7EEN TOP7 external enable permit 9 TOP6EEN TOP6 external enable permit 10 TOP5EEN TOP5 external enable permit 11 TOP4EEN TOP4 external enable permit 12 TOP3EEN TOP3 external enable permit 13 TOP2EEN TOP2 external enable pe...

Page 351: ...11 12 13 14 D15 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO When reset H 0000 D Bit Name Function R W 0 4 No functions assigned 0 5 TOP10PRO TOP10 enable protect 0 Enables rewrite 6 TOP9PRO TOP9 enable protect 1 Disables rewrite 7 TOP8PRO TOP8 enable protect 8 TOP7PRO TOP7 enable protect 9 TOP6PRO TOP6 enable protect 10 TOP5PRO TOP5 enable pr...

Page 352: ...o an occurrence of underflow the count enable bit is automatically reset to 0 Therefore what you get by reading the TOP0 10 Count Enable Register is the status that indicates the counter s operating status active or idle When reset H 0000 D Bit Name Function R W 0 4 No functions assigned 0 5 TOP10CEN TOP10 count enable 0 Stops count 6 TOP9CEN TOP9 count enable 1 Enables count 7 TOP8CEN TOP8 count ...

Page 353: ... 3 TOP Output related 16 bit Timer Figure 10 3 8 Configuration of the TOP Enable Circuit WR Dn TOPm enable protect TOPmPRO WR EN ON TOPm external enable TOPmEEN TINnS TOPm enable TOPmCEN TOP enable control Edge selection F F F F F F Event bus ...

Page 354: ...vice versa at startup and upon underflow generating a single shot pulse waveform in width of reload register set value 1 only once Also an interrupt can be generated when the counter underflows The count value is reload register set value 1 In the case shown below for example if the reload register value 7 then the count value 8 Because all internal circuits operate synchronously with the count cl...

Page 355: ...inues counting down clock pulses until it underflows after reaching the minimum count Figure 10 3 10 Typical Operation in TOP Single shot Output Mode AAAAAAAAAAA AAAAAAAAAAA Count clock Correction register H FFFF H 0000 Enabled by writing to enable bit or by external input F F output Disabled by underflow Not used TOP interrupt due to underflow Enable bit Starts counting down from the reload regis...

Page 356: ...correction register In this case one down count in the clock period during which the correction was performed is canceled Therefore note that the counter value actually is corrected by correction register value 1 For example if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3 then the counter underflows after a total of 12 cou...

Page 357: ...ce of overflow In the example below the reload register has the initial value H 8000 set in it When the timer starts the reload register value is loaded into the counter causing it to start counting down In the example diagram here H 4000 is written to the correction register when the counter has counted down to H 5000 As a result of this correction the count has been increased to H 9000 so that t...

Page 358: ...determinate H 8000 Write to correction register H 4000 H 5000 H 5000 H 4000 H 8000 H FFFF Count clock Correction register Enabled by writing to enable bit or by external input F F output Disabled by underflow TOP interrupt due to underflow Enable bit Note This diagram does not show detail timing information Reload register Data inverted by enable Counter Data inverted by underflow ...

Page 359: ...ual to a prescaler delay is included before F F starts operating after the timer is enabled Figure 10 3 13 Prescaler Delay When writing to the correction register be careful not to cause the counter to overflow Even when the counter overflows due to correction of counts no interrupt is generated for the occurrence of overflow When the counter underflows in the subsequent down count after overflow ...

Page 360: ...te H FFF8 Write to correction register H FFF0 0014 H 0004 H FFF0 H 0014 Overflow occurs Actual count after overflow H FFF8 H FFFF Count clock Correction register Enabled by writing to enable bit or by external input F F output Disabled by underflow TOP interrupt due to underflow Enable bit Note This diagram does not show detail timing information Reload register Data inverted by enable Counter Dat...

Page 361: ... F F output levels change from low to high or vice versa when the counter underflows first time and next generating a single shot pulse waveform in width of reload register set value 1 only once with the output delayed by an amount of time equal to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next The valid count values are the counter ...

Page 362: ...ter underflows next time while continuing down count it stops Figure 10 3 16 Typical Operation in TOP Delayed Single shot Output AAAAAAAAAAAAAA Correction register H FFFF H 0000 Underflow first time Down count starting from counter s set value H A000 Underflow second time H F000 Down count starting from reload register s set value H F000 1 Data inverted by underflow Not used H FFFF H F000 Count cl...

Page 363: ...is canceled Therefore note that the counter value actually is corrected by correction register value 1 For example if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3 then the counter underflows after a total of 12 counts after reload Figure 10 3 17 Example of Counting in TOP Delayed Single shot Output Mode When Count is Corre...

Page 364: ...FFF H 0000 Underflow first time Indeterminate Counter corrected H F000 H A000 Underflow second time H F000 H F000 0008 1 H 0008 Write to correction register Correction register Data inverted by underflow Count clock F F output TOP interrupt due to underflow Enable bit Reload register Counter Data inverted by underflow Note This diagram does not show detail timing information ...

Page 365: ...he enable bit the latter has priority so that count is disabled Even when the counter overflows due to correction of counts no interrupt is generated for the occurrence of overflow When the counter underflows in the subsequent down count after overflow a false underflow interrupt is generated due to overcounting When you read the counter immediately after reloading it pursuant to underflow the val...

Page 366: ...oad register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock and when the minimum count is reached generates an underflow This underflow causes the counter to be reloaded with the content of the reload register and start counting over again Thereafter this operation is repeate...

Page 367: ... after enable is the previous counter value and not 4 Note 2 What you actually see in the cycle immediately after reload is H FFFF underflow value and not 5 Note 3 This diagram does not show detail timing information Figure 10 3 20 Example of Counting in TOP Continuous Output Mode 4 3 2 1 1 2 3 4 5 H FFFF Count value 5 0 3 2 1 0 4 5 3 2 1 0 5 5 4 5 1 2 3 4 5 6 Count value 6 Count value 6 1 2 3 4 5...

Page 368: ... Typical Operation in TOP Continuous Output Mode AAAAAAAAAAAAAA AAAAAAAAAAAAAA H FFFF H 0000 H E000 H A000 H E000 H E000 1 Data inverted by enable H E000 1 H FFFF H FFFF Correction register Underflow first time Down count starting from counter s set value Underflow second time Down count starting from reload register set value Data inverted by underflow Not used Count clock Enabled by writing to e...

Page 369: ...ty so that count is disabled When you read the counter immediately after reloading it pursuant to underflow the value you get is temporarily H FFFF But this counter value immediately changes to reload value 1 at the next clock edge Because the internal circuit operation is synchronized to the count clock prescaler output a finite time equal to a prescaler delay is included before F F starts operat...

Page 370: ...pecifications of TIO The diagram in the next page shows a block diagram of TIO Table 10 4 1 Specifications of TIO Input Output related 16 bit Timer Item Specification Number of channels 10 channels Counter 16 bit down counter Reload register 16 bit reload register Measure register 16 bit capture register Timer startup Started by writing to enable bit in software or by enabling with external input ...

Page 371: ...TCLK2 clk en cap udf TIO 6 S TCLK2S S TIN8S IRQ8 TIN9 clk en cap udf TIO 7 S S TIN9S IRQ8 TIN10 S S TIN10S clk en cap udf TIO 8 clk en cap udf TIO 9 IRQ8 TIN11 S S TIN11S F F11 F F12 F F13 F F14 F F15 S F F16 F F17 F F18 F F19 S F F PSC0 2 Prescaler S S S S S S S S S TO 11 TO 12 TO 13 TO 14 TO 15 IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 TO 17 TO 18 TO 19 TO 20 IRQ4 IRQ4 IRQ4 DRQ0 IRQ3 3 2 1 0 0 1 2 3 0 1 2 ...

Page 372: ...counting down again To stop the counter disable count by writing to the enable bit in software Note that an interrupt can be generated by a counter underflow or execution of measure operation 2 Noise processing input mode In noise processing input mode the timer detects the status of an input signal that it remained in the same state for over a predetermined time In noise processing input mode the...

Page 373: ...0 register into the counter synchronously with the count clock letting the counter start counting The counter counts down clock pulses and stops when it underflows after reaching the minimum count The F F output waveform in single shot output mode is inverted at startup and upon underflow generating a single shot pulse waveform in width of reload 0 register set value 1 only once Also an interrupt ...

Page 374: ...er the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock and when the minimum count is reached generates an underflow This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again Thereafter this operation is repeated each time ...

Page 375: ...332 H 0080 0334 H 0080 0336 TIO0 Reload 0 Measure Register TIO0RL0 H 0080 0318 H 0080 031A H 0080 031C TIO0 3 Control Register 0 TIO03CR0 TIO0 3 Control Register 1 TIO03CR1 Address TIO0 Counter TIO0CT TIO0 Reload 1 Register TIO0RL Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TIO1 Reload 0 Measure Register TIO1RL0 TIO1 Counter TIO1CT ...

Page 376: ...8 TIO4 Control Register TIO4CR H 0080 036A H 0080 0368 0 Address 1 Address TIO4 Reload 0 Measure Register TIO4RL0 TIO5 Control Register TIO5CR Address TIO4 Counter TIO4CT TIO4 Reload 1 Register TIO4RL Blank addresses are reserved TIO5 Reload 0 Measure Register TIO5RL0 TIO5 Counter TIO5CT TIO5 Reload 1 Register TIO5RL TIO6 Reload 0 Measure Register TIO6RL0 TIO6 Counter TIO6CT TIO6 Reload 1 Register...

Page 377: ... 038A H 0080 0388 0 Address 1 Address TIO8 Reload 0 Measure Register TIO8RL0 TIO9 Control Register TIO9CR Address TIO8 Counter TIO8CT TIO8 Reload 1 Register TIO8RL Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TIO8 Control Register TIO8CR TIO9 Reload 0 Measure Register TIO9RL0 TIO9 Counter TIO9CT TIO9 Reload 1 Register TIO9RL1 TIO0 9 ...

Page 378: ...t output delayed single shot output or continuous output mode as well as select the counter enable and counter clock sources Following eight TIO control registers are provided for each timer group TIO0 3 Control Register 0 TIO03CR0 TIO0 3 Control Register 1 TIO03CR1 TIO4 Control Register TIO4CR TIO5 Control Register TIO5CR TIO6 Control Register TIO6CR TIO7 Control Register TIO7CR TIO8 Control Regi...

Page 379: ...No selection measure input source selection 1 External input TIN4 TIO0 3 Control Register 0 TIO3CR0 Address H 0080 031A Note 1 To select the TIO3 enable measure input source use the TIO4 Control Register s TIO34ENS TIO3 TIO4 enable measure input source selection bit Note 2 During measure free run clear input mode even if this bit is set to 0 external input disabled when a capture signal is entered...

Page 380: ...re clear input mode 101 Measure free run input mode 11X Noise processing input mode 12 TIO0ENS TIO0 enable 0 No selection measure input source selection 1 External input TIN3 13 15 TIO0M 000 Single shot output mode TIO0 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise p...

Page 381: ...6 bit Timer TIO0 3 Control Register 1 TIO03CR1 Address H 0080 031D When reset H 00 D Bit Name Function R W 8 13 No functions assigned 0 14 15 TIO03CKS 00 Clock bus 0 TIO0 3 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 D8 9 10 11 12 13 14 D15 TIO03CKS ...

Page 382: ...measure clear input mode Note 2 Always make sure the counter has stopped and is idle before setting or changing operation modes D0 1 2 3 4 5 6 D7 TIO4CKS TIO4EEN TIO34ENS TIO4M When reset H 00 D Bit Name Function R W 0 1 TIO4CKS 00 Clock bus 0 TIO4 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 2 TIO4EEN Note 1 0 Disables external input TIO4 external input enable 1 Enables ext...

Page 383: ...s clk en cap S TCLK2S S TIN8S 3 2 1 0 TIN7 TCLK1 clk en cap TIO 5 S TCLK1S S TIN7S TIN8 TCLK2 TIO 6 TIN9 clk en cap TIO 7 S S TIN9S TIN10 S S TIN10S clk en cap TIO 8 clk en cap TIO 9 TIN11 S S TIN11S S 3 2 1 0 3 2 1 0 3 2 1 0 Clock bus Input event bus Selector Note This is an outline diagram shown for the explanation of TIO Control Register ...

Page 384: ...TCLK1 TIO5 clock source selection 100 Clock bus 0 101 Clock bus 1 110 Clock bus 2 111 Clock bus 3 11 12 TIO5ENS 0X No selection TIO5 enable measure 10 External input TIN7 input source selection 11 Input event bus 3 13 15 TIO5M 000 Single shot output mode TIO5 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101...

Page 385: ... W 0 2 TIO6CKS 0XX External input TCLK2 TIO6 clock source selection 100 Clock bus 0 101 Clock bus 1 110 Clock bus 2 111 Clock bus 3 3 4 TIO6ENS 00 No selection TIO6 enable measure 01 External input TIN8 input source selection 10 Input event bus 2 11 Input event bus 3 5 7 TIO6M 000 Single shot output mode TIO6 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 0...

Page 386: ... Clock bus 0 TIO7 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 11 12 TIO7ENS 00 No selection TIO7 enable measure 01 External input TIN9 input source selection 10 Input event bus 0 11 Input event bus 3 13 15 TIO7M 000 Single shot output mode TIO7 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input...

Page 387: ...k source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 2 4 TIO8ENS 0XX No selection TIO8 enable measure 100 External input TIN10 input source selection 101 Input event bus 1 110 Input event bus 2 111 Input event bus 3 5 7 TIO8M 000 Single shot output mode TIO8 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear inpu...

Page 388: ... Clock bus 0 TIO9 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 11 12 TIO9ENS 00 No selection TIO9 enable measure 01 External input TIN1 input source selection 10 Input event bus 1 11 Input event bus 3 13 15 TIO9M 000 Single shot output mode TIO9 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input...

Page 389: ...TIO5CT Address H 0080 0350 TIO6 Counter TIO6CT Address H 0080 0360 TIO7 Counter TIO7CT Address H 0080 0370 TIO8 Counter TIO8CT Address H 0080 0380 TIO9 Counter TIO9CT Address H 0080 0390 W Write to this register is not accepted is disabled in PWM output mode Note This register must always be accessed in halfwords The TIO Counters are a 16 bit down counter After the timer is enabled by writing to t...

Page 390: ...L0 W Write to this register is not accepted is disabled in PWM output mode Note This register must always be accessed in halfwords The TIO Reload 0 Measure Registers serve dual purposes as a register for reloading TIO Count Registers TIO0CT TIO9CT with data and as a measure register during measure input mode These registers are disabled against write during measure input mode It is in the followin...

Page 391: ...L1 Address H 0080 0354 TIO6 Reload 1 Register TIO6RL1 Address H 0080 0364 TIO7 Reload 1 Register TIO7RL1 Address H 0080 0374 TIO8 Reload 1 Register TIO8RL1 Address H 0080 0384 TIO9 Reload 1 Register TIO9RL1 Address H 0080 0394 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TIO0RL1 TIO9RL1 Note This register must always be accessed in halfwords The TIO Reload 1 Registers are used to reload the TIO Counter...

Page 392: ...nable Protect 12 TIO3PRO TIO3 Enable Protect 13 TIO2PRO TIO2 Enable Protect 14 TIO1PRO TIO1 Enable Protect 15 TIO0PRO TIO0 Enable Protect 10 4 8 TIO Enable Control Registers TIO0 9 Enable Protect Register TIOPRO Address H 0080 03BC Note This register must always be accessed in halfwords The TIO0 9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by ...

Page 393: ... 13 14 D15 TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN Note This register must always be accessed in halfwords The TIO0 9 Count Enable Register controls operation of TIO counters To enable the counter in software enable the relevant TIO0 9 Enable Protect Register for write and set the count enable bit by writing a 1 To stop the counter enable the TIO0 ...

Page 394: ...nput Output related 16 bit Timer Figure 10 4 7 Configuration of the TIO Enable Circuit WR Dn TIOm enable protect TIOmPRO WR EN ON TIOm external enable TIOmEEN or TIOmENS TINnS TIOm enable TIOmCEN TIO enable control Edge selection F F F F F F Event bus ...

Page 395: ... software the counter starts counting down synchronously with the count clock When a capture signal is entered from an external device the counter value at that point in time is written to the measure register Especially in measure clear input mode the counter value is initialized to H FFFF upon capture from which the counter starts counting down again When the counter underflows after reaching th...

Page 396: ...r H FFFF H 0000 Enabled by writing to enable bit TIO interrupt Measure event capture occurs Indeterminate Enable bit Note This diagram does not show detail timing information Measure register H 7000 TIN interrupt by external event input TIO interrupt by underflow H 9000 H 7000 H 9000 Measure event capture occurs TIN interrupt by external event input TIN interrupt ...

Page 397: ...ure Clear Input Mode H FFFF H 0000 H 7000 H 7000 Count clock Counter Enabled by writing to enable bit TIO interrupt Measure event capture occurs Indeterminate Enable bit Note This diagram does not show detail timing information Measure register TIN interrupt by external event input TIO interrupt by underflow TIN interrupt ...

Page 398: ...O measure free run clear input modes The following describes precautions to be observed when using TIO measure free run clear input modes If measure event input and write to the counter occur simultaneously in the same clock period the write value is set in the counter while at the same time latched into the measure register ...

Page 399: ...s to an invalid level before the counter underflows the counter temporarily stops counting and when a valid level signal is entered again it is reloaded with the initial count and restarts counting The valid count value is reload 0 register set value 1 The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit An interrupt can be generated by a counte...

Page 400: ...ows the reload 1 register value is loaded into the counter letting it continue counting Thereafter the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs The valid count values are reload 0 register set value 1 and reload 1 register set value 1 The timer stops at the same time count is disabled by writing to the enable bit and not in synchr...

Page 401: ...from reload 1 register set value H C000 1 Data inverted by underflow Data inverted by enable H A000 1 Reload 1 register H C000 Down count starting from reload 0 register set value Down count starting from reload 0 register set value H A000 PWM output period H C000 H A000 Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does no...

Page 402: ...ith PWM periods from which the timer starts operating again This operation can normally be performed collectively by accessing register addresses wordwise in 32 bits beginning with that of reload 1 register Data are automatically written to reload 1 and then reload 0 registers in succession If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register...

Page 403: ...ad 0 reload 1 data latched H 1000 H 2000 H 8000 H 9000 Enlarged view New PWM output period Old PWM output period F F output H 7FFE H 0000 PWM period latched Reload 1 buffer H 2000 H 9000 H 000 1 H FFFF H 1000 H 0FFF H 2000 H 800 0 H 9000 b When reload register updates take effect in the next period reflected one period later H 1000 H 2000 H 8000 H 9000 H 0FFE H 000 0 H 2000 H 9000 Note This diagra...

Page 404: ...0 register set value 1 only once Also an interrupt can be generated when the counter underflows The count value is reload 0 register set value 1 For details about count operation also refer to Section 10 3 9 Operation in TOP Single shot Output Mode with Correction Function 2 Precautions to be observed when using TIO single shot output mode The following describes precautions to be observed when us...

Page 405: ...AAAA H FFFF H 0000 Disabled by underflow Not used Counts down starting from reload 0 register set value H A000 H A000 F F output TIO interrupt by underflow Data inverted by underflow Data inverted by enable Reload 1 register Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information ...

Page 406: ...f reload 0 register set value 1 only once with the output delayed by an amount of time equal to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next The valid count values are the counter set value 1 and reload 0 register set value 1 For details about count operation also see Section 10 3 10 Operation in TOP Delayed Single shot Output Mode...

Page 407: ... first time Down count starting from counter set value H F000 H A000 Underflow second time H F000 Down count starting from reload 0 register set value H EFFF Not used F F output TIO interrupt by underflow Data inverted by underflow Reload 1 register Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing i...

Page 408: ...iting to the enable bit in software The F F output waveform in continuous output mode is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows The valid count values are the counter set value 1 and reload 0 register set value 1 Fo...

Page 409: ...second time Down count starting from reload 0 register set value Not used F F output TIO interrupt by underflow Data inverted by underflow Reload 1 register Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information Down count starting from reload 0 register set value Figure 10 4 16 Typical Operat...

Page 410: ...a 16 bit up counter where when a measure signal is entered from an external device the counter value is latched into each measure register The counter stops counting at the same time count is disabled by writing to the enable bit in software A TIN interrupt can be generated by entering an external measure signal Also a TMS interrupt can be generated by a counter overflow Item Specification Number ...

Page 411: ...TCLK3S TIN12S DRQ3 TIN13S IRQ10 TIN12 TIN13 TIN14S TIN14 TIN15S TIN15 clk TMS 1 ovf cap3 cap2 cap1 cap0 S S S S S TIN16S DRQ5 TIN17S TIN16 TIN17 TIN18S TIN18 TIN19S TIN19 DRQ6 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 0 1 2 3 IRQ7 IRQ7 S 3 2 1 0 3 2 1 0 0 1 2 3 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter 16 bits Clock bus Input event bus Output event bus Sel...

Page 412: ...C8 TMS0 Control Register TMS0CR TMS0 Measure 3 Register TMS0MR3 TMS0 Measure 0 Register TMS0MR0 H 0080 03D0 H 0080 03D2 H 0080 03D4 H 0080 03D6 H 0080 03D8 0 Address 1 Address Address TMS Counter TMS0CT Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TMS1 Measure 2 Register TMS1MR2 TMS1 Measure 1 Register TMS1MR1 TMS1 Measure 3 Register...

Page 413: ...ure 0 source selection 1 Input event bus 0 1 TMS0SS1 0 External input TIN14 TMS0 measure 1 source selection 1 Input event bus 1 2 TMS0SS2 0 External input TIN13 TMS0 measure 2 source selection 1 Input event bus 2 3 TMS0SS3 0 External input TIN12 TMS0 measure 3 source selection 1 Input event bus 3 4 5 TMS0CKS 00 External input TCLK3 TMS0 clock source selection 01 Clock bus 0 10 Clock bus 1 11 Clock...

Page 414: ... TMS1SS2 0 External input TIN17 TMS1 measure 2 source selection 1 Input event bus 2 11 TMS1SS3 0 External input TIN16 TMS1 measure 3 source selection 1 Input event bus 3 12 No functions assigned 0 13 TMS1CKS 0 Clock bus 0 TMS1 clock source selection 1 Clock bus 3 14 No functions assigned 0 15 TMS1CEN 0 Count stops TMS1 count enable 1 Count starts D8 9 10 11 12 13 14 D15 TMS1CKS TMS1CEN TMS1 TMS1 T...

Page 415: ...n R W 0 15 TMS0CT TMS1CT 16 bit counter value Note This register must always be accessed in halfwords The TMS counters are a 16 bit up counter which starts counting when the timer is enabled by writing to the enable bit in software The counter can be read on the fly D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TMS0CT TMS1CT MULTIJUNCTION TIMERS 10 5 TMS Input related 16 bit Timer ...

Page 416: ...3D4 TMS1 Measure 1 Register TMS1MR1 Address H 0080 03D6 TMS1 Measure 0 Register TMS1MR0 Address H 0080 03D8 Note 1 This register is a read only register Note 2 This register can be accessed in either byte or halfword The TMS measure registers are used to latch counter contents upon event input The TMS measure registers are a read only register When reset Indeterminate D Bit Name Function R W 0 15 ...

Page 417: ...signal from an external device Also when the counter overflows a TMS interrupt can be generated Figure 10 5 3 Typical Operation in TMS Measure Input Count clock Counter H FFFF H 0000 Enabled by writing to enable bit Measure event 1 occurs Initial value indeterminate Enable bit Note This diagram does not show detail timing information Measure 0 register H 8000 Overflow occurs TIN15 interrupt H C000...

Page 418: ...s precautions to be observed when using TMS measure input If measure event input and write to the counter occur simultaneously in the same clock period the write value is set in the counter while at the same time latched to the measure register MULTIJUNCTION TIMERS 10 5 TMS Input related 16 bit Timer ...

Page 419: ... TML Table 10 6 1 Specifications of TML Input related 32 bit Timer Item Specification Number of channels 8 channels 2 circuit blocks consisting of 4 channels each 8 channels in total Input clock Divided by 2 frequency of the internal peripheral operating clock e g 10 0 MHz when using 20 MHz internal peripheral operating clock or clock bus 1 input Counter 32 bit up counter 2 Measure register 32 bit...

Page 420: ...the device remains reset A TIN interrupt can be generated by entering an external measure signal However no TML counter overflow interrupts are available MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 3 2 1 0 3 2 1 0 S S S S TIN20S TIN21S TIN20 TIN21 TIN22S TIN22 TIN23S TIN23 IRQ11 IRQ11 IRQ11 IRQ11 1 2 internal peripheral clock 0 1 2 3 S 3 2 1 0 3 2 1 0 0 1 2 3 clk TML0 cap3 cap2 cap1 c...

Page 421: ...FFC H 0080 0FFE TML0 Control Register TML0CR 0 Address 1 Address Address Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TML0 Measure 2 Register Low TML0MR2L TML0 Measure 2 Register High TML0MR2H TML0 Measure 1 Register Low TML0MR1L TML0 Measure 1 Register High TML0MR1H TML0 Measure 0 Register Low TML0MR0L TML0 Measure 0 Register High T...

Page 422: ...nter When reset H 00 D Bit Name Function R W 8 TML0SS0 0 External input TIN23 TML0 measure 0 source selection 1 Input event bus 0 9 TML0SS1 0 External input TIN22 TML0 measure 1 source selection 1 Input event bus 1 10 TML0SS2 0 External input TIN21 TML0 measure 2 source selection 1 Input event bus 2 11 TML0SS3 0 External input TIN20 TML0 measure 3 source selection 1 Input event bus 3 12 14 No func...

Page 423: ...n 1 Input event bus 2 11 TML1SS3 0 External input TIN30 TML1 measure 3 source selection 1 Input event bus 3 12 14 No functions assigned 0 15 TML1CKS 0 1 2 internal peripheral clock TML1 clock source selection 1 Clock bus 1 The TML1 Control Register is used to select TML1 input event and the counter clock source Note The counter can be written to normally only when the selected clock source is a 1 ...

Page 424: ...et The TML0CTH register accommodates the 16 high order bits and the TML0CTL register accommodates the 16 low order bits of the 32 bit counter The counter can be read on the fly D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0CTH 16 high order bits D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML0CTL 16 low order bits When reset Indeterminate D Bit Name Function R W 0 15 TML0CTH 32 bit counter value 16 high...

Page 425: ...1CTH register accommodates the 16 high order bits and the TML1CTL register accommodates the 16 low order bits of the 32 bit counter The counter can be read on the fly D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1CTH 16 high order bits D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TML1CTL 16 low order bits When reset Indeterminate D Bit Name Function R W 0 15 TML1CTH 32 bit counter value 16 high order bit...

Page 426: ...ts beginning with a word boundary The TML0 Measure Registers are used to latch counter contents upon event input The TML0 Measure Registers are configured with 32 bits the TML0MR3H 0H accommodating the 16 high order bits and the TML0MR3L 0L accommodating the 16 low order bits The TML0 Measure Registers are a read only register These registers must always be accessed in words 32 bits beginning with...

Page 427: ...th a word boundary The TML1 Measure Registers are used to latch counter contents upon event input The TML1 Measure Registers are configured with 32 bits the TML1MR3H 0H accommodating the 16 high order bits and the TML1MR3L 0L accommodating the 16 low order bits The TML1 Measure Registers are a read only register These registers must always be accessed in words 32 bits beginning with a word boundar...

Page 428: ... Measure event 1 occurs Measure event 0 occurs Measure 1 register TIN22 interrupt Initial value indeterminate 10 6 7 Operation of TML Measure Input 1 Outline of TML measure input In TML measure input the counter starts counting up clock pulses upon deassertion of reset When event input is entered to measure registers 0 3 the counter value is latched into the measure registers A TIN interrupt can b...

Page 429: ...do not write to the counter If the timer operates with any clock other than the 1 2 internal peripheral clock while clock bus 1 is selected for the count clock the captured value is one that leads the actual counter value by one clock period However during the 1 2 internal peripheral clock interval from the count clock this problem does not occur and the counter value is captured at exact timing T...

Page 430: ...of TID The diagram in the next page shows a block diagram of TID Table 10 7 1 Specifications of TID Input related 16 bit Timer Item Specification Number of channels 3 channels Counter 16 bit up down counter Reload register 16 bit reload register Timer startup Started by writing to enable bit in software Mode selection Input mode Fixed period count mode Event count mode Multiply by 4 event count mo...

Page 431: ...l circuit CLK1 CLK2 TOD0_0 7 Reload register clk TID1 AD1TRG To A D1 converter PSC4 TIN26 TIN27 S CLK1 CLK2 TOD1_0 7 clk TOD1_0 TOD1_7 Enable signal IRQ15 PSC5 TOM0_0 TOM0_7 Enable signal IRQ17 PSC3 5 Prescaler 1 2 internal peripheral clock Up down counter Built in edge control circuit Reload register TID2 S CLK1 CLK2 TOM0_0 7 clk Up down counter Built in edge control circuit Reload register TIN28...

Page 432: ...rds H 0080 078C H 0080 0B8E H 0080 0BD0 H 0080 0B8C H 0080 0CD0 H 0080 0C8C H 0080 0C8E Blank addresses are reserved TID0 Counter TID0CT TID0 Reload Register TID0RL Prescaler Register 3 PRS3 TID0 Control Prescaler 3 Enable Register TID0PRS3EN H 0080 078E H 0080 07D0 TID1 Counter TID1CT TID1 Reload Register TID1RL Prescaler Register 4 PRS4 TID1 Control Prescaler 4 Enable Register TID1PRS4EN TID2 Co...

Page 433: ...eriod count mode TID0 operation mode selection 10 Multiply by 4 event count mode 11 Event count mode 11 TID0CEN 0 Count stops TID0 count enable 1 Count starts 12 14 No functions assigned 0 15 PRS3EN 0 Count stops Prescaler 3 enable 1 Count starts Note Always make sure the counter has stopped and is idle before setting or changing operation modes The TID0 Control Prescaler 3 Enable Register selects...

Page 434: ...ent count mode 11 TID1CEN 0 Count stops TID1 count enable 1 Count starts 12 No functions assigned 0 13 TID1ENO 0 Disables enable output to TOD1_0 7 TID1 enable output enable 1 Enables enable output to TOD1_0 7 14 No functions assigned 0 15 PRS4EN 0 Count stops Prescaler 4 enable 1 Count starts Note Always make sure the counter has stopped and is idle before setting or changing operation modes The ...

Page 435: ...ent count mode 11 TID2CEN 0 Count stops TID2 count enable 1 Count starts 12 No functions assigned 0 13 TID2ENO 0 Disables enable output to TOM0_0 7 TID2 enable output enable 1 Enables enable output to TOM0_0 7 14 No functions assigned 0 15 PRS5EN 0 Count stops Prescaler 5 enable 1 Count starts Note Always make sure the counter has stopped and is idle before setting or changing operation modes The ...

Page 436: ...D2CT Address H 0080 0C8C D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TID0CT TID1CT TID2CT When reset Indeterminate D Bit Name Function R W 0 15 TID0CT TID1CT TID2CT 16 bit counter value Note This register must always be accessed in halfwords The TID counters are a 16 bit up down counter After the timer is enabled by writing to the enable bit in software the counter starts counting synchronously with t...

Page 437: ...te D Bit Name Function R W 0 15 TID0RL TID1RL TID2RL 16 bit reload register value Note This register must always be accessed in halfwords The TID reload registers are used to reload the TID counter registers TID0CT TID1CT or TID2CT with data It is in the following cases that the content of the reload register is loaded into the counter When the counter underflowed in fixed period count mode When t...

Page 438: ... count the counter is reloaded with the content of the reload register again and continues counting To stop the counter disable count by writing to the enable bit Also an interrupt can be generated each time the counter underflows The valid count value is the reload register set value 1 Figure 10 7 3 Typical Operation in TID Fixed Period Count Mode MULTIJUNCTION TIMERS 10 7 TID Input related 16 bi...

Page 439: ...lock When after setting the counter the timer is enabled by writing to the enable bit in software the counter starts counting up from the set count value synchronously with the generated clock An interrupt can be generated by a counter overflow To stop the counter disable count by writing to the enable bit in software or fix the external input signal high or low Figure 10 7 4 Typical Operation in ...

Page 440: ...nd falling edges as the timer generates clock pulses synchronized to the internal clock When after setting the counter the timer is enabled by writing to the enable bit in software the counter starts counting up synchronously with the generated clock For details on whether the counter counts up or counts down see Table 10 7 2 below An interrupt can be generated by a counter overflow and or underfl...

Page 441: ...ation Count Enabled and Disabled TIN24 TIN25 Up count Down count 8000 8001 8002 8001 8000 8003 7FFE 8003 Counter value Counter 8002 7FFF 7FFE 7FFF 7FFE Switched over 8000 8001 8000 7FFF 7FFE Timer enable Count disabled Count enabled 7FFF Enable TIN24 TIN25 8001 7FFE Counter value Counter Switched over Up count Down count Count disabled Count disabled Count enabled ...

Page 442: ...S 10 7 TID Input related 16 bit Timer Figure 10 7 8 Up Down Count Operation Interrupt Timing TID Interrupt FFFF 0000 0001 0000 FFFF 0002 0001 FFFE FFFD FFFE FFFD TIN24 TIN25 Up count Down count FFFF 0000 Counter value Counter Switched over ...

Page 443: ...specifications of TOD The diagram in the next page shows a block diagram of TOD Table 10 8 1 Specifications of TOD Output related 16 bit Timer Item Specification Number of channels 16 channels two circuit blocks consisting of 8 channels each 16 channels in total Counter 16 bit down counter x 2 Reload register 16 bit reload register x 2 Timer startup TOD0 Started by writing to enable bit in softwar...

Page 444: ...C3 4 IRQ13 TO 21 TO 22 TO 23 TO 24 TO 25 TO 26 TO 27 TO 28 PSC3 clk udf TOD1_0 clk udf TOD1_1 clk udf TOD1_2 clk udf TOD1_3 clk udf TOD1_4 clk udf TOD1_5 clk udf TOD1_6 clk udf TOD1_7 F F29 F F30 F F31 F F32 F F33 F F34 F F35 F F36 IRQ16 TO 29 TO 30 TO 31 TO 32 TO 33 TO 34 TO 35 TO 36 PSC4 en en en en en en en en clk udf TID1 ovf IRQ15 AD1TRG To A D1 converter CLK1 CLK2 TIN26 TIN27 Prescaler Outpu...

Page 445: ...M output mode is inverted at count startup and upon each underflow The timer stops at the same time count is disabled by writing to the enable bit and not in synchronism with PWM output period An interrupt can be generated when the counter underflows every other time second time fourth time and so on after being enabled 2 Single shot output mode without correction function In single shot output mo...

Page 446: ...delayed by an amount of time equal to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next 4 Continuous output mode without correction function In continuous output mode the timer counts down clock pulses starting from the set value of the counter and when the counter underflows reloads it with the reload 0 register value Thereafter this o...

Page 447: ...CT TOD0_0 Reload 1 Register TOD00RL1 H 0080 0796 TOD0_0 Reload 0 Register TOD00RL0 H 0080 079C TID0_2 Counter TOD02CT TOD0_1 Reload 1 Register TOD01RL1 H 0080 079E TOD0_1 Reload 0 Register TOD01RL0 H 0080 079A H 0080 07A8 TID0_3 Counter TOD03CT TOD0_2 Reload 1 Register TOD02RL1 TOD0_2 Reload 0 Register TOD02RL0 H 0080 07A2 H 0080 07AC H 0080 07AE H 0080 07B0 H 0080 07B2 H 0080 07B4 H 0080 07B6 H 0...

Page 448: ...eload 1 Register TOD07RL1 H 0080 07CE TOD0_7 Reload 0 Register TOD07RL0 H 0080 07CA H 0080 07D8 H 0080 07D2 H 0080 07DC H 0080 07DE H 0080 0B90 H 0080 0B92 H 0080 0B94 H 0080 0B96 H 0080 0B98 H 0080 0B9A H 0080 0B9C H 0080 0B9E H 0080 0BA0 H 0080 0BA2 H 0080 0BA4 H 0080 0BA6 Note 1 TOD0 Interrupt Status Register TOD0IST TOD0 Interrupt Mask Register TOD0IMA F F Protect Register 2 FFP2 F F Data Regi...

Page 449: ...Prescaler 4 Enable Register TOD1PRS4EN TOD1_4 Reload 1 Register TOD14RL1 H 0080 0BB6 TOD1_4 Reload 0 Register TOD14RL0 H 0080 0BBC TID1_6 Counter TOD16CT TOD1_5 Reload 1 Register TOD15RL1 H 0080 0BBE TOD1_5 Reload 0 Register TOD15RL0 H 0080 0BBA H 0080 0BC8 TID1_7 Counter TOD17CT TOD1_6 Reload 1 Register TOD16RL1 TOD1_6 Reload 0 Register TOD16RL0 H 0080 0BC2 H 0080 0BCC H 0080 0BCE H 0080 0BD0 H 0...

Page 450: ...n mode selection 01 Delayed single shot output mode 2 3 TOD01M 10 Continuous output mode TOD0_1 operation mode selection 11 PWM output mode 4 5 TOD02M TOD0_2 operation mode selection 6 7 TOD03M TOD0_3 operation mode selection 8 9 TOD04M TOD0_4 operation mode selection 10 11 TOD05M TOD0_5 operation mode selection 12 13 TOD06M TOD0_6 operation mode selection 14 15 TOD07M TOD0_7 operation mode select...

Page 451: ...1 Delayed single shot output mode 2 3 TOD11M 10 Continuous output mode TOD1_1 operation mode selection 11 PWM output mode 4 5 TOD12M TOD1_2 operation mode selection 6 7 TOD13M TOD1_3 operation mode selection 8 9 TOD14M TOD1_4 operation mode selection 10 11 TOD15M TOD1_5 operation mode selection 12 13 TOD16M TOD1_6 operation mode selection 14 15 TOD17M TOD1_7 operation mode selection The TOD1 Contr...

Page 452: ...ter TOD06CT Address H 0080 07C0 TOD0_7 Counter TOD07CT Address H 0080 07C8 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOD00CT TOD07CT When reset Indeterminate D Bit Name Function R W 0 15 TOD00CT TOD07CT 16 bit counter value W Write to this register is accepted in all but PWM output mode Note This register must always be accessed in halfwords The TOD0 Counter is a 16 bit down counter After the timer ...

Page 453: ...BC0 TOD1_7 Counter TOD17CT Address H 0080 0BC8 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOD10CT TOD17CT When reset Indeterminate D Bit Name Function R W 0 15 TOD10CT TOD17CT 16 bit counter value W Write to this register is accepted in all but PWM output mode Note This register must always be accessed in halfwords The TOD1 Counter is a 16 bit down counter After the timer is enabled by writing to the...

Page 454: ... 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOD00RL0 TOD07RL0 When reset Indeterminate D Bit Name Function R W 0 15 TOD00RL0 TOD07RL0 16 bit reload register value Note This register must always be accessed in halfwords The TOD0 Reload 0 Register is used to reload the TOD0 Counter Registers TOD00CT TOD07CT with data It is in the following cases that the content of reload 0 register is loaded into the cou...

Page 455: ...8 9 10 11 12 13 14 D15 TOD10RL0 TOD17RL0 When reset Indeterminate D Bit Name Function R W 0 15 TOD10RL0 TOD17RL0 16 bit reload register value Note This register must always be accessed in halfwords The TOD1 Reload 0 Register is used to reload the TOD1 Counter Registers TOD10CT TOD17CT with data It is in the following cases that the content of reload 0 register is loaded into the counter When the c...

Page 456: ... Address H 0080 07C4 TOD0_7 Reload 1 Register TOD07RL1 Address H 0080 07CC D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOD00RL1 TOD07RL1 When reset Indeterminate D Bit Name Function R W 0 15 TOD00RL1 TOD07RL1 16 bit reload register value Note This register must always be accessed in halfwords The TOD0 Reload 1 Register is used to reload the TOD0 Counter Registers TOD00CT TOD07CT with data It is in the...

Page 457: ... 0BC4 TOD1_7 Reload 1 Register TOD17RL1 Address H 0080 0BCC D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TOD10RL1 TOD17RL1 When reset Indeterminate D Bit Name Function R W 0 15 TOD10RL1 TOD17RL1 16 bit reload register value Note This register must always be accessed in halfwords The TOD1 Reload 1 Register is used to reload the TOD1 Counter Registers TOD10CT TOD17CT with data It is in the following case...

Page 458: ... D Bit Name Function R W 8 TOD00PRO 0 Enables rewrite TOD0_0 enable protect 1 Disables rewrite 9 TOD01PRO TOD0_1 enable protect 10 TOD02PRO TOD0_2 enable protect 11 TOD03PRO TOD0_3 enable protect 12 TOD04PRO TOD0_4 enable protect 13 TOD05PRO TOD0_5 enable protect 14 TOD06PRO TOD0_6 enable protect 15 TOD07PRO TOD0_7 enable protect The TOD0 Enable Protect Register controls rewriting of the TOD0 coun...

Page 459: ...on R W 8 TOD10PRO 0 Enables rewrite TOD1_0 enable protect 1 Disables rewrite 9 TOD11PRO TOD1_1 enable protect 10 TOD12PRO TOD1_2 enable protect 11 TOD13PRO TOD1_3 enable protect 12 TOD14PRO TOD1_4 enable protect 13 TOD15PRO TOD1_5 enable protect 14 TOD16PRO TOD1_6 enable protect 15 TOD17PRO TOD1_7 enable protect The TOD1 Enable Protect Register controls rewriting of the TOD1 counter enable bit des...

Page 460: ...0_5 count enable 14 TOD06CEN TOD0_6 count enable 15 TOD07CEN TOD0_7 count enable The TOD0 Count Enable Register controls operation of TOD0 counters To enable the counter in software enable the relevant TOD0 Enable Protect Register for write and set the count enable bit by writing a 1 To stop the counter enable the TOD0 Enable Protect Register for write and reset the count enable bit by writing a 0...

Page 461: ... 14 TOD16CEN TOD1_6 count enable 15 TOD17CEN TOD1_7 count enable The TOD1 Count Enable Register controls operation of TOD1 counters To enable the counter in software enable the relevant TOD1 Enable Protect Register for write and set the count enable bit by writing a 1 To stop the counter enable the TOD1 Enable Protect Register for write and reset the count enable bit by writing a 0 In single shot ...

Page 462: ...f TOD0 Enable Circuit WR Dn WR F F F F TOD0m enable protect TOD0mPRO TOD0m enable TOD0mCEN TOD0m enable control Figure 10 8 6 Configuration of TOD1 Enable Circuit WR Dn WR EN ON F F F F F F TID1 enable output enable TID1EN0 TID1 output TOD1m enable protect TOD1mPRO TOD1m enable TOD1mCEN TOD1m enable control ...

Page 463: ...derflows the reload 1 register value is loaded into the counter letting it continue counting Thereafter the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs The valid count values are reload 0 register set value 1 and reload 1 register set value 1 The timer stops at the same time count is disabled by writing to the enable bit and not in s...

Page 464: ...Underflow second time Down count starting from reload 1 register set value Data inverted by underflow Data inverted by enable Reload 1 register Down count starting from reload 0 register set value Down count starting from reload 0 register set value PWM output period Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not sh...

Page 465: ...riods from which the timer starts operating again This operation can normally be performed collectively by accessing register addresses wordwise in 32 bits beginning with that of reload 1 register Data are automatically written to reload 1 and then reload 0 registers in succession If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register only relo...

Page 466: ...ad 1 register F F output Write to reload 1 Write to reload 0 reload 1 data latched Enlarged view New PWM output period Old PWM output period F F output PWM period latched Reload 1 buffer H 0001 H FFFF H 1000 H 0FFF H 2000 H 8000 H 9000 H 1000 H 2000 H 8000 H 9000 H 0FFE H 0000 H 2000 H 9000 b When reload register updates take effect in the next period reflected one period later Note This diagram d...

Page 467: ...load 0 register set value 1 only once Also an interrupt can be generated when the counter underflows The count value is reload 0 register set value 1 For details about count operation also refer to Section 10 3 11 Operation in TOP Single shot Output Mode with Correction Function 2 Precautions to be observed when using TOD single shot output mode The following describes precautions to be observed w...

Page 468: ...AAAAAA H FFFF H 0000 H A000 H A000 Disabled by underflow Not used Counts down starting from reload 0 register set value F F output TOD interrupt by underflow Data inverted by underflow Data inverted by enable Reload 1 register Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information ...

Page 469: ...qual to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next The valid count values are the counter set value 1 and reload 0 register set value 1 For details about count operation also see Section 10 3 12 Operation in TOP Delayed Single shot Output Mode With Correction Function 2 Precautions to be observed when using TOD delayed single sho...

Page 470: ...00 H F000 H EFFF F F output Underflow first time TOD interrupt by underflow Underflow second time Down count starting from reload 0 register set value Data inverted by underflow Reload 1 register Down count starting from counter set value Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information ...

Page 471: ...count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows The valid count values are the counter set value 1 and reload 0 register set...

Page 472: ...output Underflow first time Underflow second time Data inverted by underflow Data inverted by enable Reload 1 register Down count starting from reload 0 register set value Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Note This diagram does not show detail timing information Data inverted by underflow Down count starting from counter set value Down cou...

Page 473: ...us output mode The table below shows specifications of TOM The diagram in the next page shows a block diagram of TOM Table 10 9 1 Specifications of TOM Output related 16 bit Timer Item Specification Number of channels 8 channels Counter 16 bit down counter Reload register 16 bit reload register Timer startup Started by writing to enable bit in software or by TID2 timer underflow overflow signal Mo...

Page 474: ...OM0_0 clk udf TOM0_1 clk udf TOM0_2 clk udf TOM0_3 clk udf TOM0_4 clk udf TOM0_5 clk udf TOM0_6 clk udf TOM0_7 F F37 F F38 F F39 F F40 F F41 F F42 F F43 F F44 IRQ16 TO 37 TO 38 TO 39 TO 40 TO 41 TO 42 TO 43 TO 44 PSC5 en clk udf TID2 ovf IRQ17 CLK1 CLK2 TIN28 TIN29 Prescaler Output flip flop 1 2 internal peripheral clock en en en en en en en ...

Page 475: ...utput mode is inverted at count startup and upon each underflow The timer stops at the same time count is disabled by writing to the enable bit and not in synchronism with PWM output period An interrupt can be generated when the counter underflows every other time second time fourth time and so on after being enabled 2 Single shot output mode without correction function In single shot output mode ...

Page 476: ...each underflow Unlike in PWM output mode F F output is not inverted at counter startup An interrupt can be generated when the counter underflows second time after being enabled 4 Continuous output mode without correction function In continuous output mode the timer counts down clock pulses starting from the set value of the counter and when the counter underflows reloads it with the reload 0 regis...

Page 477: ..._0 Reload 1 Register TOM00RL1 TOM0_0 Counter TOM00CT TOM0_5 Reload 0 Register TOM05RL0 TOM0_5 Reload 1 Register TOM05RL1 H 0080 0C9C H 0080 0C9E H 0080 0CA8 H 0080 0CAA H 0080 0CAC H 0080 0CAE 0 Address 1 Address Address Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved TOM0_2 Counter TOM02CT TOM0_1 Reload 0 Register TOM01RL0 TOM0_1 Reloa...

Page 478: ...M0IST F F Protect Register 4 FFP4 F F Data Register 4 FFD4 Note 1 Prescaler Register 5 is shared with TOM0_0 7 and TID2 and TID2 Control Prescaler 5 Enable Register is used in TID2 control H 0080 0CDA H 0080 0CDC H 0080 0CDE TOM0 Control Register TOM0CR TOM0 Enable Protect Register TOM0PRO TOM0 Count Enable Register TOM0CEN Blank addresses are reserved Note2 The registers enclosed in thick frames ...

Page 479: ...tion 6 7 TOM03M TOM0_3 operation mode selection 8 9 TOM04M TOM0_4 operation mode selection 10 11 TOM05M TOM0_5 operation mode selection 12 13 TOM06M TOM0_6 operation mode selection 14 15 TOM07M TOM0_7 operation mode selection 10 9 4 TOM Control Registers TOM0 Control Register TOM0CR Address H 0080 0CDA The TOM0 Control Register is used to select TOM0_0 7 operation modes PWM output single shot outp...

Page 480: ..._7 Counter TOM07CT Address H 0080 0CC8 W Write to this register is not accepted is disabled in PWM output mode Note This register must always be accessed in halfwords The TOM0 Counter is a 16 bit down counter After the timer is enabled by writing to the enable bit in software or by TID2 underflow overflow signal it starts counting synchronously with the count clock During PWM output and single sho...

Page 481: ...Note This register must always be accessed in halfwords The TOM0 Reload 0 Registers are used to reload the TOM0 Counter Registers TOM00CT TOM07CT with data It is in the following cases that the content of reload 0 register is loaded into the counter When the counter is enabled in single shot output PWM output or single shot PWM output mode When the counter underflowed in continuous output mode Whe...

Page 482: ...Address H 0080 0CC4 TOM0_7 Reload 1 Register TOM07RL1 Address H 0080 0CCC Note This register must always be accessed in halfwords The TOM0 Reload 1 Registers are used to reload the TOM0 Counter Registers TOM00CT TOM07CT with data It is in the following cases that the content of reload 1 register is loaded into the counter When the count value set by reload 1 register underflowed in PWM output mode...

Page 483: ...ge by enabling or disabling rewrite When reset H 00 D Bit Name Function R W 8 TOM00PRO 0 Enables rewrite TOM0_0 enable protect 1 Disables rewrite 9 TOM01PRO TOM0_1 enable protect 10 TOM02PRO TOM0_2 enable protect 11 TOM03PRO TOM0_3 enable protect 12 TOM04PRO TOM0_4 enable protect 13 TOM05PRO TOM0_5 enable protect 14 TOM06PRO TOM0_6 enable protect 15 TOM07PRO TOM0_7 enable protect D8 9 10 11 12 13 ...

Page 484: ...TOM0_5 count enable 14 TOM06CEN TOM0_6 count enable 15 TOM07CEN TOM0_7 count enable The TOM0 Count Enable Register controls operation of TOM0 counters To enable the counter in software enable the relevant TOM0 Enable Protect Register for write and set the count enable bit by writing a 1 To stop the counter enable the TOM0 Enable Protect Register for write and reset the count enable bit by writing ...

Page 485: ...RS 10 9 TOM Output related 16 bit Timer Figure 10 9 4 Configuration of the TOM Enable Circuit WR Dn WR EN ON TID2 enable output enable TID2EN0 F F F F F F TID2 output TOM0m enable protect TOM0mPRO TOM0m enable TOM0mCEN TOM0m enable control ...

Page 486: ...derflows the reload 1 register value is loaded into the counter letting it continue counting Thereafter the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs The valid count values are reload 0 register set value 1 and reload 1 register set value 1 The timer stops at the same time count is disabled by writing to the enable bit and not in s...

Page 487: ...Underflow second time Down count starting from reload 1 register set value Data inverted by underflow Data inverted by enable Reload 1 register Down count starting from reload 0 register set value PWM output period Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information Data inverted by underfl...

Page 488: ...PWM periods from which the timer starts operating again This operation can normally be performed collectively by accessing register addresses wordwise in 32 bits beginning with that of reload 1 register Data are automatically written to reload 1 and then reload 0 registers in succession If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register onl...

Page 489: ...oad 1 register F F output Write to reload 1 Write to reload 0 reload 1 data latched Enlarged view New PWM output period Old PWM output period F F output PWM period latched Reload 1 buffer H 0001 H FFFF H 1000 H 0FFF H 2000 H 8000 H 9000 H 1000 H 2000 H 8000 H 9000 H 0FFE H 0000 H 2000 H 9000 b When reload register updates take effect in the next period reflected one period later Note This diagram ...

Page 490: ...oad 0 register set value 1 only once Also an interrupt can be generated when the counter underflows The count value is reload 0 register set value 1 For details about count operation also refer to Section 10 3 11 Operation in TOP Single shot Output Mode with Correction Function 2 Precautions to be observed when using TOM single shot output mode The following describes precautions to be observed wh...

Page 491: ...AAAAAA H FFFF H 0000 H A000 H A000 Disabled by underflow Not used Counts down starting from reload 0 register set value F F output TOM interrupt by underflow Data inverted by underflow Data inverted by enable Reload 1 register Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information ...

Page 492: ...The first time the counter underflows the reload 1 register value is loaded into the counter letting it continue counting Then when the counter underflows next time it stops The valid count values are the reload 0 register set value 1 and reload 1 register set value 1 each To stop the timer in software disable count by writing to the enable bit The timer stops at the same time count is disabled an...

Page 493: ... F F output Underflow first time TOM interrupt by underflow Underflow second time Down count starting from reload 1 register set value Data inverted by underflow Reload 1 register Down count starting from reload 0 register set value PWM output period Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing ...

Page 494: ...count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows The valid count values are the counter set value 1 and reload 0 register set...

Page 495: ...irst time TOM interrupt by underflow Underflow second time Data inverted by underflow Data inverted by enable Reload 1 register Enabled by writing to enable bit or by external input Reload 0 register Count clock Counter Enable bit Note This diagram does not show detail timing information Data inverted by underflow Down count starting from counter set value Down count starting from reload 0 registe...

Page 496: ... easily by storing waveform data only when the data needs to be rewritten Note that the high low transistor shorting prevention time can be provided by changing the set time of TOM in software Figure 10 9 11 System Configuration Diagram Figure 10 9 12 Timer Connections When Used for Three phase Motor Control Circuit board M32R E 4 Power MOS Motor U U V V W W TMS TMS TMS TOM TOM TOM TOM TOM TOM clk...

Page 497: ...0 MULTIJUNCTION TIMERS 10 9 TOM Output related 16 bit Timer Figure 10 9 13 Diagram of Control Image Single shot U V W 20KHz TOM start TOM U TOM U TOM V TOM V TOM W TOM W Delay Delay Single shot Shorting prevention time ...

Page 498: ...10 10 228 Ver 0 10 MULTIJUNCTION TIMERS 10 9 TOM Output related 16 bit Timer This is a blank page ...

Page 499: ...CHAPTER 11 A D CONVERTERS 11 1 Outline of A D Converters 11 2 A D Converter Related Registers 11 3 Functional Description of A D Converters 11 4 Precautions on Using A D Converters ...

Page 500: ...tially A D converted 3 Types of scan modes Single shot scan mode Scan operation is performed for one machine cycle Continuous scan mode Scan operation is performed repeatedly until stopped 4 Special operation mode Forcible single mode execution during scan mode Conversion is forcibly executed in single mode during scan operation Scan mode start after single mode execution Scan operation is started...

Page 501: ...ed by external ADTRG pin input Conversion rate During single mode Normal rate 299 1 f BCLK Note 3 f BCLK shortest time Double rate 173 1 f BCLK Internal peripheral clock During comparator mode Normal rate 47 1 f BCLK operating frequency shortest time Double rate 29 1 f BCLK Interrupt request generation function Generated at completion of A D conversion comparate operation single shot scan operatio...

Page 502: ...N14 AD0IN15 AD0CMP AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request Successive Approximation type A D Converter Unit Internal data bus A D0 Scan Mode Register P67 ADTRG AD0SCM0 1 AD0SIM0 1 AVCC0 Output event bus 3 multijunction timer 10 bit readout 8 bit readout Shifter 10 bit A D0 Data Register 2 10 bit A D0...

Page 503: ...al data bus A D1 Scan Mode Register 10 bit readout Shifter 10 bit A D1 Data Register 2 10 bit A D1 Data Register 3 10 bit A D1 Data Register 4 10 bit A D1 Data Register 5 10 bit A D1 Data Register 6 10 bit A D1 Data Register 7 10 bit A D1 Data Register 8 10 bit A D1 Data Register 9 10 bit A D1 Data Register 10 10 bit A D1 Data Register 11 10 bit A D1 Data Register 12 10 bit A D1 Data Register 13 1...

Page 504: ...ersion interrupt request or a DMA transfer request for the A D0 converter only can be generated at completion of A D conversion when in single mode or when operating in scan mode at completion of one cycle of scan loop 2 Comparator mode In comparator mode the analog input voltage in a specified channel is comparated compared with the Successive Approximation Register value and the result relative ...

Page 505: ...sion start Software trigger Started by setting A D1 conversion start bit to 1 ____________ Hardware trigger Started by TID1 overflow underflow or ADTRG signal input Note 2 DMA transfer request Can be generated for only the A D0 converter Note 1 Comparate start Started by writing a comparison value to the successive approximation register ADiSAR Note 2 DMA transfer request Can be generated for only...

Page 506: ...hannel scan and 16 channel scan respectively An A D conversion interrupt request or a DMA transfer request for the A D0 converter only can be generated at completion of one cycle of scan operation Figure 11 1 5 Operation of A D Conversion in Scan Mode for 4 channel Scan Note 1 A D0 conversion start Software trigger Started by setting A D0 conversion start bit to 1 ____________ Hardware trigger Sta...

Page 507: ...1 1 Outline of A D Converters ADiIN0 ADiDT0 ADiIN1 ADiIN2 ADiIN3 ADiDT1 ADiDT2 ADiDT3 ADiIN4 ADiDT4 ADiIN5 ADiIN6 ADiIN7 ADiDT5 ADiDT6 ADiDT7 ADiIN0 ADiDT0 ADiIN1 ADiIN2 ADiIN3 ADiDT1 ADiDT2 ADiDT3 ADiIN4 ADiDT4 ADiIN5 ADiIN6 ADiIN7 ADiDT5 ADiDT6 ADiDT7 ADiIN8 ADiDT8 ADiIN9 ADiIN10 ADiIN11 ADiDT9 ADiDT10 ADiDT11 ADiIN12 ADiDT12 ADiIN13 ADiIN14 ADiIN15 ADiDT13 ADiDT14 ADiDT15 i 0 1 Completed here w...

Page 508: ...it A Di Data Register 6 ADiIN7 ADiIN7 10 bit A Di Data Register 7 Completed ADiIN0 10 bit A Di Data Register 0 Repeated until forcibly halted 16 channel scan ADiIN0 ADiIN0 10 bit A Di Data Register 0 ADiIN1 ADiIN1 10 bit A Di Data Register 1 ADiIN2 ADiIN2 10 bit A Di Data Register 2 ADiIN3 ADiIN3 10 bit A Di Data Register 3 ADiIN4 ADiIN4 10 bit A Di Data Register 4 ADiIN5 ADiIN5 10 bit A Di Data R...

Page 509: ... To start single mode conversion during scan mode operation in hardware choose a hardware trigger using the Single Mode Register 0 A D conversion start trigger select bit Then enter the ____________ hardware trigger selected with the said register ADTRG signal or output event bus 3 for the A D0 ____________ converter or ADTRG signal or TID1 overflow underflow for the A D1 converter An A D conversi...

Page 510: ...____ Mode Register 0 and Scan Mode Register 0 you enter a hardware trigger ADTRG signal or ____________ output event bus 3 for the A D0 converter or ADTRG signal or TID1 overflow underflow for the A D1 converter the device first performs single mode conversion and then scan mode conversion subsequently after executing the single mode conversion An A D conversion interrupt request or a DMA transfer...

Page 511: ...g scan or comparate operation and the channel being converted is canceled and A D conversion is reexecuted beginning with channel 0 Figure 11 1 9 Restarting Conversion during Single Mode Operation Figure 11 1 10 Restarting Conversion during Scan Operation Note DMA transfer request Can be generated for only the A D0 converter A D CONVERTERS 11 1 Outline of A D Converters AA AA Single mode ADiIN5 co...

Page 512: ...est for the A D0 converter only Note For the A D1 converter this bit selects to enable or disable interrupt requests and cannot select DMA transfer requests Figure 11 1 11 Selecting between Interrupt Request and DMA Transfer Request A D CONVERTERS 11 1 Outline of A D Converters Scan mode when one cycle of scan completed Single mode when A D conversion or comparate operation completed A D0 conversi...

Page 513: ...H 0080 00AC H 0080 00AE A D0 Successive Approximation Register AD0SAR A D0 Comparate Data Register AD0CMP Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved A D0 Single Mode Register 1 AD0SIM1 A D0 Scan Mode Register 1 AD0SCM1 10 bit A D0 Data Register 1 AD0DT1 10 bit A D0 Data Register 2 AD0DT2 10 bit A D0 Data Register 3 AD0DT3 10 bit A ...

Page 514: ...ter 15 AD08DT15 Blank addresses are reserved 8 bit A D0 Data Register 14 AD08DT14 8 bit A D0 Data Register 13 AD08DT13 8 bit A D0 Data Register 12 AD08DT12 8 bit A D0 Data Register 11 AD08DT11 8 bit A D0 Data Register 10 AD08DT10 8 bit A D0 Data Register 9 AD08DT9 8 bit A D0 Data Register 8 AD08DT8 8 bit A D0 Data Register 7 AD08DT7 8 bit A D0 Data Register 6 AD08DT6 8 bit A D0 Data Register 5 AD0...

Page 515: ...ion Register AD1SAR A D1 Comparate Data Register AD1CMP Note The registers enclosed in thick frames must always be accessed in halfwords Blank addresses are reserved A D1 Single Mode Register 1 AD1SIM1 A D1 Scan Mode Register 1 AD1SCM1 10 bit A D1 Data Register 1 AD1DT1 10 bit A D1 Data Register 2 AD1DT2 10 bit A D1 Data Register 3 AD1DT3 10 bit A D1 Data Register 4 AD1DT4 10 bit A D1 Data Registe...

Page 516: ...ter 15 AD18DT15 Blank addresses are reserved 8 bit A D1 Data Register 14 AD18DT14 8 bit A D1 Data Register 13 AD18DT13 8 bit A D1 Data Register 12 AD18DT12 8 bit A D1 Data Register 11 AD18DT11 8 bit A D1 Data Register 10 AD18DT10 8 bit A D1 Data Register 9 AD18DT9 8 bit A D1 Data Register 8 AD18DT8 8 bit A D1 Data Register 7 AD18DT7 8 bit A D1 Data Register 6 AD18DT6 8 bit A D1 Data Register 5 AD1...

Page 517: ...nsfer request selection 1 DMA transfer request 5 AD0SCMP 0 A D0 conversion comparate in progress A D0 conversion comparate completed 1 A D0 conversion comparate completed 6 AD0SSTP 0 Performs no operation 0 A D0 conversion stop 1 Stops A D0 conversion 7 AD0SSTT 0 Performs no operation 0 A D0 conversion start 1 Starts A D0 conversion A D0 Single Mode Register 0 is used to control operation of the A...

Page 518: ...w underflow 3 AD1SSEL 0 Software trigger A D1 conversion start trigger selection 1 Hardware trigger 4 AD1SREQ 0 Enables A D1 interrupt request Interrupt request 1 Disables A D1 interrupt request 5 AD1SCMP 0 A D1 conversion comparate in progress A D1 conversion comparate completed 1 A D1 conversion comparate completed 6 AD1SSTP 0 Performs no operation 0 A D1 conversion stop 1 Stops A D1 conversion ...

Page 519: ...r AD1SIM0 this bit selects whether to enable or disable an A D0 conversion interrupt when single mode operation A D conversion or comparate is completed 4 ADnSCMP A Dn conversion comparate completion bit D5 This is a read only bit which when reset is 1 This bit is 0 when the A Dn converter is performing single mode operation A D conversion or comparate and set to 1 when the operation is completed ...

Page 520: ...t are set to 1 at the same time the A Dn conversion stop bit has priority If this bit is set to 1 again during single mode conversion special operation mode Forcible single mode execution during scan mode is entered into so that the channel being converted in scan mode is canceled and single mode conversion is performed When the single mode conversion finishes scan mode A D conversion is restarted...

Page 521: ...nversion mode A D0 conversion mode selection 1 Comparator mode 9 AD0SSPD 0 Normal rate A D0 conversion rate selection 1 Double rate 10 11 No functions assigned 0 12 15 AN0SEL 0000 Selects AD0IN0 Analog input pin selection 0001 Selects AD0IN1 0010 Selects AD0IN2 0011 Selects AD0IN3 0100 Selects AD0IN4 0101 Selects AD0IN5 0110 Selects AD0IN6 0111 Selects AD0IN7 1000 Selects AD0IN8 1001 Selects AD0IN...

Page 522: ...1 conversion mode selection 1 Comparator mode 9 AD1SSPD 0 Normal rate A D1 conversion rate selection 1 Double rate 10 11 No functions assigned 0 12 15 AN1SEL 0000 Selects AD1IN0 Analog input pin selection 0001 Selects AD1IN1 0010 Selects AD1IN2 0011 Selects AD1IN3 0100 Selects AD1IN4 0101 Selects AD1IN5 0110 Selects AD1IN6 0111 Selects AD1IN7 1000 Selects AD1IN8 1001 Selects AD1IN9 1010 Selects AD...

Page 523: ... conversion rate for the A Dn converter during single mode Setting this bit to 0 selects a normal speed and setting this bit to 1 selects a x2 speed two times normal speed 3 ANsSEL analog input pin selection bits D12 D15 These bits select analog input pins for the A Dn converter during single mode It is the channels selected by these bits that are operated on for A D conversion or comparate operat...

Page 524: ...selection 1 Output event bus 3 3 AD0CSEL 0 Software trigger A D0 conversion start trigger selection 1 Hardware trigger 4 AD0CREQ 0 Requests A D0 interrupt Interrupt request DMA request selection 1 Requests DMA transfer 5 AD0CCMP 0 A D0 conversion in progress A D0 conversion completed 1 A D0 conversion completed 6 AD0CSTP 0 Performs no operation 0 A D0 conversion stop 1 Stops A D0 conversion 7 AD0C...

Page 525: ... trigger 4 AD1CREQ 0 Enables A D1 interrupt request Interrupt request selection 1 Disables A D1 interrupt request 5 AD1CCMP 0 A D1 conversion in progress A D1 conversion completed 1 A D1 conversion completed 6 AD1CSTP 0 Performs no operation 0 A D1 conversion stop 1 Stops A D1 conversion 7 AD1CSTT 0 Performs no operation 0 A D1 conversion start 1 Starts A D1 conversion A D1 Scan Mode Register 0 is...

Page 526: ..._________ ADTRG pin for a start trigger not that if A D conversion is completed while the ADTRG pin input is held low new A D conversion is not started 3 ADnCSEL A Dn conversion start trigger selection bit D3 This bit selects whether to use a software or hardware trigger to start A D conversion of the A Dn converter during scan mode When you choose a software trigger A D conversion is started by s...

Page 527: ...tart bit D7 This bit is used to start scan mode operation of the A Dn converter in software This bit is effective only when a software trigger has been selected by the ADnCSEL A Dn conversion start trigger selection bit and starts A D conversion when it is set to 1 If the A Dn conversion start bit and A Dn conversion stop bit are set to 1 at the same time the A Dn conversion stop bit has priority ...

Page 528: ...loop selection 01XX 4 channel scan 10XX 8 channel scan 11XX 16 channel scan 00XX 16 channel scan When read during conversion 0000 Converting AD0IN0 0001 Converting AD0IN1 0010 Converting AD0IN2 0011 Converting AD0IN3 0100 Converting AD0IN4 0101 Converting AD0IN5 0110 Converting AD0IN6 0111 Converting AD0IN7 1000 Converting AD0IN8 1001 Converting AD0IN9 1010 Converting AD0IN10 1011 Converting AD0IN...

Page 529: ... scan 00XX 16 channel scan When read during conversion 0000 Converting AD1IN0 0001 Converting AD1IN1 0010 Converting AD1IN2 0011 Converting AD1IN3 0100 Converting AD1IN4 0101 Converting AD1IN5 0110 Converting AD1IN6 0111 Converting AD1IN7 1000 Converting AD1IN8 1001 Converting AD1IN9 1010 Converting AD1IN10 1011 Converting AD1IN11 1100 Converting AD1IN12 1101 Converting AD1IN13 1110 Converting AD1...

Page 530: ... when read during scan operation show the status of the A Dn converter indicating the channel it is converting The value read from these bits during single mode are always B 0000 If A D conversion is halted by setting Scan Mode Register 0 ADnCSTP A Dn conversion stop bit to 1 during scan mode execution the bits when read at this time show the value of the channel in which the A D conversion has be...

Page 531: ...rresponding to the converted channel When you read this register in the middle of A D conversion you see the result in the middle of conversion In comparator mode write a comparison value the value to be compared in comparate operation to this register Simultaneously with a write to this register comparate operation with the analog input pin that has been set by Single Mode Register 1 starts After...

Page 532: ...erted channel When you read this register in the middle of A D conversion you see the result in the middle of conversion In comparator mode write a comparison value the value to be compared in comparate operation to this register Simultaneously with a write to this register comparate operation with the analog input pin that has been set by Single Mode Register 1 starts After comparate operation th...

Page 533: ...mpared with the value written to the A D0 Successive Approximation Register with the result stored in the corresponding bit of this comparate data register The bit is 0 when the analog input voltage comparison voltage and is 1 when the analog input voltage comparison voltage When reset Indeterminate D Bit Name Function R W 0 15 AD0CMP0 AD0CMP15 Note 2 0 Analog input voltage comparison voltage A D0...

Page 534: ...ister with the result stored in the corresponding bit of this comparate data register The bit is 0 when the analog input voltage comparison voltage and is 1 when the analog input voltage comparison voltage D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 AD1 CMP12 AD1 CMP11 AD1 CMP9 AD1 CMP8 AD1 CMP7 AD1 CMP5 AD1 CMP4 AD1 CMP3 AD1 CMP2 AD1 CMP1 AD1 CMP0 AD1 CMP15 AD1 CMP14 AD1 CMP13 AD1 CMP10 AD1 CMP6 When...

Page 535: ...Register 13 AD0DT13 Address H 0080 00AA 10 bit A D0 Data Register 14 AD0DT14 Address H 0080 00AC 10 bit A D0 Data Register 15 AD0DT15 Address H 0080 00AE Note This register must always be accessed in halfwords In single mode of the A D0 converter the result of A D conversion is stored in the 10 bit A D0 Data Register for each corresponding channel In single shot and continuous scan modes the conte...

Page 536: ...13 Address H 0080 0AAA 10 bit A D1 Data Register 14 AD1DT14 Address H 0080 0AAC 10 bit A D1 Data Register 15 AD1DT15 Address H 0080 0AAE Note This register must always be accessed in halfwords In single mode of the A D1 converter the result of A D conversion is stored in the 10 bit A D1 Data Register for each corresponding channel In single shot and continuous scan modes the content of the A D1 Su...

Page 537: ...a Register 13 AD08DT13 Address H 0080 00EB 8 bit A D0 Data Register 14 AD08DT14 Address H 0080 00ED 8 bit A D0 Data Register 15 AD08DT15 Address H 0080 00EF This A D data register stores the 8 bit conversion data from the A D0 converter In single mode of the A D0 converter the result of A D conversion is stored in the 8 bit A D0 Data Register for each corresponding channel In single shot and conti...

Page 538: ...8DT13 Address H 0080 0AEB 8 bit A D1 Data Register 14 AD18DT14 Address H 0080 0AED 8 bit A D1 Data Register 15 AD18DT15 Address H 0080 0AEF This A D data register stores the 8 bit conversion data from the A D1 converter In single mode of the A D1 converter the result of A D conversion is stored in the 8 bit A D1 Data Register for each corresponding channel In single shot and continuous scan modes ...

Page 539: ... supply and ground AVCC AVSS are separated from those of the digital circuit with sufficient noise prevention measures incorporated For details about the conversion accuracy refer to Section 11 3 5 Accuracy of A D Conversion Analog input voltage V Figure 11 3 1 Outline Block Diagram of the Successive Approximation type A D Converter Unit A D conversion result x VREF input voltage V 1024 A D CONVER...

Page 540: ... the A D Successive Approximation Register at completion of the comparison of D15 is the final A D conversion result Figure 11 3 2 Changes of the A D Successive Approximation Register during A D Convert Operation Note The comparison voltage Vref the voltage fed from the D A converter into the comparator is determined according to changes of the content of the A D Successive Approximation Register ...

Page 541: ...d channel is completed the content of the A D Successive Approximation Register is transferred to the corresponding 10 bit A D Data Registers 0 15 and convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted In single shot scan mode the convert operation stops when A D conversion for one specified scan loop is completed 3 Continuous scan mode When comparison of ...

Page 542: ...ref and the analog input voltage VIN are compared with the comparison result stored in the comparate result flag A D Comparate Data Register s D15 If Vref VIN then the comparate result flag 0 If Vref VIN then the comparate result flag 1 The comparate operation stops after storing the comparison result The comparison result is stored in the A D Comparate Data Register AD0CMP AD1CMP s corresponding ...

Page 543: ... to when the CPU can stably read out this conversion result from the A D data register Scan to scan dummy time A time during single shot or continuous scan mode from when the A D converter finished A D conversion in a channel to when it starts A D conversion in the next channel The equation to calculate the A D conversion time is as follows A D conversion time Start dummy time Execution cycle time...

Page 544: ...es to a hardware triggered case Note 3 This applies to a comparator mode case where a value is written to the A D Successive Approximation Register Note 4 This applies to only scan mode and is added to the execution time for each channel A D CONVERTERS 11 3 Functional Description of A D Converters Start dummy Execution cycle A D conversion start trigger Convert operation begins Transferred to A D ...

Page 545: ...channel scan 689 Continuous 8 channel scan 1377 16 channel scan 2753 Comparator mode 27 Note 1 For single and comparator modes this shows the time for A D conversion in one channel or for comparate operation For single shot and continuous scan modes this shows the time for A D conversion in one scan loop Note 2 This shows the time from when a write to register cycle is completed to when an A D con...

Page 546: ... converter s ideal conversion line Figure 11 3 6 4 Full scale error Refers to an amount of dislocation by which the analog input voltage at which the digital output code reached the full scale value is dislocated from the nominal value Figure 11 3 7 Figure 11 3 4 Ideal A D Conversion Characteristics Relative to the 10 bit A D Converter s Analog Input Voltages A D CONVERTERS 11 3 Functional Descrip...

Page 547: ...scale Ideal conversion line Figure 11 3 5 A D Converter s Nonlinearity Error Figure 11 3 6 A D Converter s Offset Error A D CONVERTERS 11 3 Functional Description of A D Converters Conversion line offset to the negative side Conversion line offset to the positive side Offset error A D conversion result Along input level Full scale Full scale Ideal conversion line ...

Page 548: ...ters Conversion line where the output code reaches the full scale for analog inputs lower than the fullscale Full scale error Conversion line where the output code does not reach the full scale even for full scale equivalent analog inputs A D conversion result Along input level Full scale Full scale Ideal conversion line ...

Page 549: ...terrupt Control Register each Single and Scan Mode Register or A D Successive Approximation Register except for the A D conversion stop bit do your change while A D conversion is inactive or be sure to restart A D conversion after you changed the register contents If the contents of these registers are changed in the middle of A D conversion the conversion results cannot be guaranteed Handling of ...

Page 550: ...11 11 52 Ver 0 10 A D CONVERTERS 11 4 Precautions on Using A D Converters This is a blank page ...

Page 551: ...ted Registers 12 3 Transmit Operation in CSIO Mode 12 4 Receive Operation in CSIO Mode 12 5 Precautions on Using CSIO Mode 12 6 Transmit Operation in UART Mode 12 7 Receive Operation in UART Mode 12 8 Fixed Period Clock Output Function 12 9 Precautions on Using UART Mode ...

Page 552: ...k using the same clock on both transmit and receive sides The transfer data is 8 bits long fixed UART mode asynchronous serial I O Communication is performed asynchronously The transfer data length can be selected from 7 bits 8 bits and 9 bits Serial I O0 3 each have a transmit DMA transfer and a receive DMA transfer request These transfer requests when combined with the internal DMAC allow serial...

Page 553: ...B first fixed UART mode Start bit 1 bit Character length 7 8 or 9 bits Parity bit Added or not added when added selectable between odd and even parity Stop bit 1 or 2 bits Order of transfer LSB first fixed Baud rate CSIO mode 152 bits sec to 2M bits sec at f BCLK 20 MHz UART mode 19 bits sec to 156K bits sec at f BCLK 20 MHz Error detection CSIO mode Overrun error only UART mode Overrun error pari...

Page 554: ...ished SIO2 3 transmit receive interrupt group interrupt or receive error interrupt selectable SIO4 transmit buffer empty interrupt SIO4 5 transmit receive interrupt group interrupt SIO4 receive finished SIO4 5 transmit receive interrupt group interrupt or receive error interrupt selectable SIO5 transmit buffer empty interrupt SIO4 5 transmit receive interrupt group interrupt SIO5 receive finished ...

Page 555: ...D3 To interrupt controller To DMAC4 SIO4 RXD4 TXD4 SIO5 RXD5 TXD5 SCLKI4 SCLKO4 SCLKI5 SCLKO5 Receive interrupt Transmit receive control circuit Receive DMA transfer request Transmit interrupt Transmit DMA transfer request SCLKI1 SCLKO1 To DMAC6 To interrupt controller To DMAC3 SIO2 Transmit Shift Register SIO2 Receive Shift Register Receive interrupt Transmit receive control circuit Receive DMA t...

Page 556: ...B SIO1 Transmit Control Register S1TCNT SIO1 Receive Buffer Register S1RXB SIO1 Receive Control Register S1RCNT SIO1 Baud Rate Register S1BAUR SIO1 Transmit Receive Mode Register S1MOD SIO2 Transmit Buffer Register S2TXB SIO2 Transmit Control Register S2TCNT SIO2 Receive Buffer Register S2RXB SIO2 Receive Control Register S2RCNT SIO2 Baud Rate Register S2BAUR SIO2 Transmit Receive Mode Register S2...

Page 557: ...mprise one interrupt group so do SIO4 and SIO5 2 Precautions on using transmit interrupts Transmit interrupts are generated when the corresponding TEN transmit enable bit is enabled while the SIO Interrupt Mask Register is set to enable interrupts 3 About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a receive finished DMA transfer request These DMA transfer requ...

Page 558: ...A transfer request DMA transfer request is generated when the receive buffer is filled Figure 12 2 3 Receive finished DMA Transfer Request Receive DMA transfer request RFIN receive completed bit Note When a receive error occurs no receive finished DMA transfer requests are generated ...

Page 559: ...ctive when you write a 1 the previous value is retained Transmit receive interrupt requests from SIO2 and SIO3 are described below Setting the interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the interrupt request status bit This bit is cleared by writing a 0 in software Note If the status bit is set in hardware at the same time it is cleared...

Page 560: ... writing a 0 is effective when you write a 1 the previous value is retained Transmit receive interrupt requests from SIO4 and SIO5 are described below Setting the interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the interrupt request status bit This bit is cleared by writing a 0 in software Note If the status bit is set in hardware at the sam...

Page 561: ...ks disables interrupt request interrupt mask bit 1 Enables interrupt request 12 T2MASK SIO2 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 13 R2MASK SIO2 receive 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 14 T3MASK SIO3 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 15 R3M...

Page 562: ... interrupt mask bit 1 Enables interrupt request 10 T5MASK SIO5 transmit 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 11 R5MASK SIO5 receive 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 12 15 No functions assigned 0 This register enables or disables interrupt requests generated by each SIO Interrupt requests from an SIO are e...

Page 563: ...rupt 7 ISR3 SIO3 receive interrupt 0 Receive finished interrupt cause select bit 1 Receive error interrupt This register selects the cause of an interrupt generated at completion of receive operation When set to 0 Receive finished interrupt receive buffer full is selected Receive finished interrupts occur for receive errors except an overrun error as well as for completion of receive operation Whe...

Page 564: ...ns assigned 0 This register selects the cause of an interrupt generated at completion of receive operation When set to 0 Receive finished interrupt receive buffer full is selected Receive finished interrupts occur for receive errors except an overrun error as well as for completion of receive operation When set to 1 Receive error interrupt is selected The following lists the types of errors detect...

Page 565: ... ISR2 RXD2 receive finished RXD2 receive error b6 F F ISR3 RXD3 receive finished RXD3 receive error b7 b5 IRQR2 F F R2MASK F F b13 b6 IRQT3 F F T2MASK F F b14 TXD3 b7 IRQR3 F F R2MASK F F b15 SIO4 5 transmit receive interrupts Data bus b0 IRQT4 F F T4MASK F F b8 Level 4 source inputs SI45STAT H 0080 0A00 TXD4 SI45MASK H 0080 0A01 F F ISR4 RXD4 receive finished RXD4 receive error b4 F F ISR5 RXD5 r...

Page 566: ...ster 1 Transmit in progress or data exists in transmit buffer register 6 TBE 0 Data exists in transmit buffer register Transmit buffer empty bit 1 No data in transmit buffer register 7 TEN 0 Disables transmit Transmit enable bit 1 Enables transmit 12 2 3 SIO Transmit Control Registers SIO0 Transmit Control Register S0TCNT Address H 0080 0110 SIO1 Transmit Control Register S1TCNT Address H 0080 012...

Page 567: ... cleared to 0 when transmit is idle no data in the Transmit Shift Register and no data exists in the Transmit Buffer Register This bit also is cleared by clearing the transmit enable bit 3 TBE transmit buffer empty bit D6 Set condition This bit is set to 1 when data is transferred from the Transmit Buffer Register to the Transmit Shift Register and the Transmit Buffer Register becomes empty This b...

Page 568: ...ity Note 3 14 PEN Parity enable bit 0 Disables parity UART mode only 1 Enables parity Note 3 15 SEN Sleep select bit 0 Disables sleep function UART mode only 1 Enables sleep function Note 3 Note 1 For SIO2 and 3 the D8 bit is fixed to 0 in hardware You cannot set the D8 bit to 1 to choose clock synchronous serial I O Note 2 Has no effect when UART mode is selected Note 3 D12 to D15 have no effect ...

Page 569: ...ransmit Setting this bit to 0 selects one stop bit and setting this bit to 1 selects two stop bits During clock synchronous mode the content of this bit has no effect 4 PSEL parity odd even select bit D13 This bit is effective during UART mode When parity is enabled D14 1 use this bit to select the parity attribute whether odd or even Setting this bit to 0 selects an odd parity and setting this bi...

Page 570: ... a parity error is assumed Note 1 Shown above is an example of data format in 8 bit UART mode Note 2 The data bit numbers Dn above indicate bit numbers in a data list and not the register bit numbers Dn 9 bit UART mode 8 bit UART mode D6 D5 D4 D3 D2 D1 D0 PAR SP ST Note 1 Note 2 7 bit UART mode D7 D6 D5 D4 D3 D2 D1 Clock synchronous mode D0 Note 1 Whether or not to add a parity bit is selectable N...

Page 571: ...Control Register TEN transmit enable bit by setting it to 1 Writing data to this register while the TEN bit is disabled cleared to 0 has no effect When data is written to the Transmit Buffer Register while transmit is enabled the data is transferred from the SIO Transmit Buffer Register to the SIO Transmit Shift Register upon which the serial I O starts transmitting the data Note For 7 bit and 8 b...

Page 572: ...0 After reception is completed you may read out the content of the SIO Receive Buffer Register but if the serial I O finishes receiving the next data before you read the previous data an overrun error occurs In this case the data received thereafter is not transferred to the Receive Buffer Register To restart reception normally clear the Receive Control Register s REN receive enable bit to 0 Note ...

Page 573: ...n error Overrun error bit 1 Overrun error occurred 5 PTY 0 No parity error Parity error bit UART mode only 1 Parity error occurred 6 FLM 0 No framing error Framing error bit UART mode only 1 Framing error occurred 7 ERS 0 No error Error sum bit 1 Error occurred 12 2 7 SIO Receive Control Registers SIO0 Receive Control Register S0RCNT Address H 0080 0116 SIO1 Receive Control Register S1RCNT Address...

Page 574: ...ase clear the REN receive enable bit 3 REN receive enable bit D3 Receive is enabled by setting this bit to 1 and is disabled by clearing this bit to 0 at which time the receive unit is initialized Accordingly the receive status flag receive completed flag bit overrun error flag framing error flag parity error flag and error sum flag all are cleared The receive operation stops when the receive enab...

Page 575: ...bit D6 This bit is effective in only UART mode During CSIO mode this bit is fixed to 0 Set condition The FLM framing error bit is set to 1 when the number of received bits does not agree with one that has been selected by the SIO Transmit Receive Mode Register However if an overrun error occurs this bit cannot be cleared by reading the lower byte from the Receive Buffer Register In this case clear...

Page 576: ...ect in the next cycle after the BRG counter finished counting When using the internal clock to output the SCLKO signal in CSIO mode the serial I O divides the internal BCLK using the clock divider Next it divides the resulting clock by BRG set value 1 according to the BRG set value and then by 2 which results in generating a transmit receive shift clock When using an external clock in CSIO mode th...

Page 577: ...it receive shift clock When using SIO0 SIO1 SIO4 or SIO5 in UART mode you can choose the relevant port P84 P87 P65 or P66 to function as the SCLKO pin so that a divided by 2 BRG output clock can be output from the SCLKO pin When using the internal clock internally clocked CSIO or UART mode with f BCLK selected as the BRG count source make sure that during CSIO mode the transfer rate does not excee...

Page 578: ...selected from 1 8 32 or 256 by using the CDIV baud rate generator count source select bits Transmit Control Register D2 D3 bits The baud rate generator divides the clock divider output by baud rate register set value 1 and then by 2 which results in generating a transmit receive shift clock When the internal clock is selected in CSIO mode the baud rate is calculated using the equation below 1 BCLK...

Page 579: ...tion 12 3 1 Setting the CSIO Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable the transmit buffer empty interrupt SIO Interrupt Mask Register 5 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit buffer empty interrupt during transmission set its priority level 6 Setting DMAC When you issue DMA transfer requests to the internal DMAC whe...

Page 580: ... Transmit Receive Mode Register Initial settings for CSIO transmission Set register to CSIO mode Select internal or external clock When using DMAC Set DMAC When using interrupt Set the Interrupt Controller Enable disable transmit buffer empty interrupt Set SIO Interrupt Mask Register Divide by ratio H 00 to H FF Note 2 Set SIO Baud Rate Register Select clock divider s divide by ratio Note 1 Set SI...

Page 581: ...the lower byte of the transmit buffer register in Note 1 above triggers a start of transmission Note 3 The transmit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register When transmission starts the serial I O transmits data following the procedure below Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register Set th...

Page 582: ...ated at the time data is transferred from the transmit buffer register to the transmit shift register Also a transmit buffer empty interrupt is generated when the TEN transmit enable bit is set to 1 enabled after being disabled while a transmit buffer empty interrupt has been enabled You must set the Interrupt Controller ICU before you can use transmit interrupts 12 3 7 Transmit DMA Transfer Reque...

Page 583: ...egister The following processing is automatically executed in hardware Transfer content of transmit buffer to transmit shift register Set transmit buffer empty bit to 1 Transmit data Y Successive transmission Transmit conditions met Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request Note CSIO transmit operation starts CSIO transmit operation completed Tra...

Page 584: ...quest is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied 12 3 8 Typical CSIO Transmit Operation The following shows a typical transmit operation in CSIO mode Processing by software Interrupt generation Internal clock selected External clock selected CSIO on receive side SCLKO TXD SCLKI RXD Transmit clock SCLK...

Page 585: ... the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Interrupt generation First data Next data Note 2 Note 3 Note 2 Upon transmit buffer empty interrupt next data is written First data Next data Note 4 Processing by software Internal clock selected External cloc...

Page 586: ...ernal clock selected 3 Setting SIO Baud Rate Register When the internal clock is selected set a baud rate generator value Refer to Section 12 3 1 Setting the CSIO Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable the transmit buffer empty interrupt SIO Interrupt Mask Register Select the cause of receive interrupt receive finished error Cause of Receive Interrupt Select Register 5 S...

Page 587: ...and Pin Functions Set SIO Transmit Receive Mode Register Initial settings for CSIO reception Set to CSIO mode Select internal or external clock When using DMAC Set DMAC When using interrupt Set the Interrupt Controller Enable disable transmit buffer empty interrupt Set SIO Interrupt Mask Register Divide by ratio H 00 to H FF Note 2 Set SIO Baud Rate Register Select clock divider s divide by ratio ...

Page 588: ...t serial data LSB first synchronously with the receive shift clock 12 4 3 Processing at End of CSIO Reception When data reception is completed the following operation is automatically performed in hardware 1 When reception is completed normally The receive finished receive buffer full bit is set to 1 Note 1 If a receive finished receive buffer full interrupt has been enabled an interrupt request i...

Page 589: ...n data may be received successively The receive enable bit is set to 1 Transmit conditions are met No overrun error has occurred Receive data Set SIO Receive Control Register s receive finished bit to 1 Store received data in Receive Buffer Register Set SIO Receive Control Register s overrun error and receive sum error bits to 1 Overrun error Receive conditions met Y N CSIO receive operation start...

Page 590: ... the next data before you read an overrun error occurs In this case the data received thereafter is not transferred to the SIO Receive Buffer Register To restart reception temporarily clear the receive enable bit to 0 and initialize the receive control block before you restart The said receive enable bit can be cleared when there are no receive errors note encountered by reading the lower byte fro...

Page 591: ...ation The following shows a typical receive operation in CSIO mode SIO receive interrupt Note 1 When receive finished interrupt is selected Clock stopped Automatically cleared for each receive operation performed Receive finished bit Read from receive buffer When receive error interrupt is selected Receive finished interrupt Note 2 Interrupt request accepted Note 3 No interrupt request Internal cl...

Page 592: ... cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared Note 4 Receive error interrupt Note 3 Internal clock selected External clock selected CSIO on transmit side SCLKO RXD SCLKI TXD Transmit clock SCLKO Set Receive enable bit CSIO on receive side CSIO on receive side Cleared D7 D6 D0 D7 D6 D0 RXD Set SIO receive interrupt N...

Page 593: ...Register before transmission of the preceding data is completed About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit you need to execute transmit operation by sending dummy data even when you only want to receive data In this case note that if the port function is set for TXD pin by setting the operation mode register to 1 dummy data is...

Page 594: ...us bit 1 To restart reception normally you need to temporarily clear the receive enable bit before you restart This is the only way you can clear the overrun error flag About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty the transmit buffer empty flag 1 while the transmit enable bit is set to 1 transmit enabled an SIO transmit buffer empty DM...

Page 595: ...k The clock divider s divide by value is selected from 1 8 32 or 256 note using the SIO Transmit Control Register s CDIV baud rate generator count source select bits D2 D3 The Baud Rate Generator divides the clock it received from the clock divider by baud rate register set value 1 and further divides the resulting clock by 16 to produce a transmit receive shift clock During UART mode in which the...

Page 596: ...iately before the transmit data D0 D8 character bits Transmit receive data transferred via serial I O In UART mode data in 7 8 or 9 bits can be transmitted received PAR parity bit Added to the transmit receive characters When parity is enabled parity is automatically set in such a way that the number of 1 s in characters including the parity bit itself is always even or odd as selected by the even...

Page 597: ...5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB D8 D8 D8 D8 Start bit Character data bits Parity bit Stop bit D0 D7 D8 D15 SIO Transmit Buffer Register SIO Receive Buffer Register ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB ST D7 D6 D5 D4 D3 D2 D1 PAR SP ...

Page 598: ...trol Register Select the clock divider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value Refer to Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable SIO transmit interrupt 5 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit interrupt set its priority level 6 Setting DMAC W...

Page 599: ...for UART transmission Set register to UART mode Set parity when enabled select odd even When using DMAC Set DMAC related registers When using interrupt Set the Interrupt Controller Enable disable transmit interrupt Set SIO Interrupt Related Registers Divide by ratio H 00 to H FF Note Set SIO Baud Rate Register Select clock divider s divide by ratio Set SIO Transmit Control Register Set input outpu...

Page 600: ... SIO Transmit Buffer Register to the SIO Transmit Shift Register Set the transmit buffer empty bit to 1 Note Start sending data synchronously with the shift clock beginning with the LSB Note A transmit buffer empty interrupt request and or a DMA transfer request can be generated when the transmit buffer is emptied 12 6 5 Successive UART Transmission Once data is transferred from the transmit buffe...

Page 601: ...ated at the time data is transferred from the transmit buffer register to the transmit shift register Also a transmit buffer empty interrupt is generated when the TEN transmit enable bit is set to 1 enabled after being disabled while a transmit buffer empty interrupt has been enabled You must set the Interrupt Controller ICU before you can use transmit interrupts 12 6 8 Transmit DMA Transfer Reque...

Page 602: ...egister The following processing is automatically executed in hardware Transfer content of transmit buffer to transmit shift register Set transmit buffer empty bit to 1 Transmit data Y Successive transmission Transmit conditions met Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request Note UART transmit operation starts UART transmit operation completed Tra...

Page 603: ...ter transmit data is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied 12 6 9 Typical UART Transmit Operation The following shows a typical transmit operation in CSIO mode Processing by software Interrupt generation UART on receive side TXD RXD Set ...

Page 604: ...ata is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Interrupt generation First data Next data Note 2 Note 4 Note 2 Upon transmit interrupt next data is written First data Next data Note 5 Processing by software UART on receive side TXD RXD Set ...

Page 605: ...ivider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value Refer to Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO interrupt related registers Cause of Receive Interrupt Select Register Select the cause of receive interrupt receive finished receive error Interrupt Mask Register Enable disable receive interrupts 5 Setting the Interrupt Controller When you use...

Page 606: ...ed select odd even When using DMAC Set DMAC related registers When using interrupt Set the interrupt controller SIO Receive Interrupt Control Register Set SIO Interrupt Related Registers Divide by ratio H 00 to H FF Note Set SIO Baud Rate Register Select clock divider s divide by ratio Set SIO Transmit Control Register Set input output port Operation Mode Register Serial I O related registers Init...

Page 607: ...is automatically performed in hardware 1 When reception is completed normally The receive finished receive buffer full bit is set to 1 Note 1 If a receive finished receive buffer full interrupt has been enabled an interrupt request is generated Note 2 A DMA transfer request is generated 2 When error occurs during reception When an error occurs during reception the corresponding error bit OE FE or ...

Page 608: ...ister s receive finished bit to 1 Set receive status bit to 1 Overrun error Parity error or framing error Start bit detected normally Set SIO Receive Control Register s overrun error bit and error sum bit to 1 Set SIO Receive Control Register s corresponding error bit and receive error sum bit to 1 N UART reception completed The following processing is automatically executed in hardware Transmit c...

Page 609: ...eared 12 7 4 Typical UART Receive Operation The following shows a typical receive operation in UART mode SIO receive interrupt Note 1 When receive finished interrupt is selected Automatically cleared for each receive operation performed Receive finished bit Read from receive buffer When receive error interrupt is selected Receive finished interrupt Note 2 Interrupt request accepted Note 3 No inter...

Page 610: ... Control Register interrupt request bit cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared Note 4 Receive error interrupt Note 3 UART on transmit side RXD TXD Set UART on receive side UART on receive side ST D7 SP ST D7 SP RXD Set SIO receive interrupt Note 1 When receive finished interrupt is selected When receive error ...

Page 611: ...1 SCLKO4 or SCLKO5 pin In this way a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin Note This clock is output all the time not just during data transfer Figure 12 8 1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmit receive ST SP Data ST SP Data 50 50 BRG period Internal BRG output SCLKO output 1 Configuration ...

Page 612: ...the next period after the BRG counter finished counting However when transmit and receive operations are disabled the register value can be changed at the same time you write to the register Transmit receive operations using DMA To transmit receive data in DMA request mode enable the DMAC to accept transfer requests by setting the DMA Mode Register before you start serial communication About overr...

Page 613: ...eceive Control Register overrun error bit SIO Receive Control Register parity error bit SIO Receive Control Register framing error bit The manner in which the receive finished bit and various error bit flags are cleared varies depending on whether an overrun error has occurred or not as described below When no overrun error has occurred Said bits can be cleared by reading the lower byte from the r...

Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...

Page 615: ... 13 1 Outline of the CAN Module 13 2 CAN Module Related Registers 13 3 CAN Protocol 13 4 Initializing the CAN Module 13 5 Transmitting Data Frames 13 6 Receiving Data Frames 13 7 Transmitting Remote Frames 13 8 Receiving Remote Frames ...

Page 616: ...scaler set value BRP 1 255 0 Inhibited Number of Tq s for one bit Synchronization Segment Propagation Segment Phase Segment 1 Phase Segment 2 Progagation Segment 1 8Tq Phase Segment 1 1 8Tq Phase Segment 2 2 8Tq IPT 2 Remote frame automatic A slot which received a remote frame automatically sends a data frame response function Time stamp function Time stamp function implemented by a 16 bit counter...

Page 617: ...13 1 1 Block Diagram of the CAN Module CTX CRX Data bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0 15 Control Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Control Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B Message Memory 1 Message ID 2 Data length code 3 Message data 4 Time stamp CAN0 Slot Status...

Page 618: ...gister Extended ID0 C0GMSKE0 CAN0 Local Mask Register A Extended ID0 C0LMSKAE0 Blank addresses are reserved CAN0 Slot Interrupt Mask Register CAN0SLIMK CAN0 Global Mask Register Standard ID1 C0GMSKS1 CAN0 Global Mask Register Extended ID1 C0GMSKE1 CAN0 Global Mask Register Extended ID2 C0GMSKE2 CAN0 Local Mask Register A Standard ID1 C0LMSKAS1 CAN0 Local Mask Register A Extended ID1 C0LMSKAE1 CAN0...

Page 619: ...ta 6 C0MSL1DT6 CAN0 Message Slot 1 Data 7 C0MSL1DT7 CAN0 Message Slot 2 Extended ID0 C0MSL2EID0 CAN0 Message Slot 2 Data 0 C0MSL2DT0 CAN0 Message Slot 2 Data Length Register C0MSL2DLC CAN0 Message Slot 2 Time Stamp C0MSL2TSP CAN0 Message Slot 2 Standard ID0 C0MSL2SID0 CAN0 Message Slot 2 Standard ID1 C0MSL2SID1 CAN0 Message Slot 2 Extended ID2 C0MSL2EID2 CAN0 Message Slot 2 Extended ID1 C0MSL2EID1...

Page 620: ...DLC CAN0 Message Slot 7 Time Stamp C0MSL7TSP CAN0 Message Slot 7 Standard ID0 C0MSL7SID0 CAN0 Message Slot 7 Standard ID1 C0MSL7SID1 CAN0 Message Slot 7 Extended ID2 C0MSL7EID2 CAN0 Message Slot 7 Extended ID1 C0MSL7EID1 CAN0 Message Slot 7 Data 1 C0MSL7DT1 CAN0 Message Slot 7 Data 2 C0MSL7DT2 CAN0 Message Slot 7 Data 3 C0MSL7DT3 CAN0 Message Slot 7 Data 4 C0MSL7DT4 CAN0 Message Slot 7 Data 5 C0MS...

Page 621: ...SL12EID1 CAN0 Message Slot 12 Data 1 C0MSL12DT1 CAN0 Message Slot 12 Data 2 C0MSL12DT2 CAN0 Message Slot 12 Data 3 C0MSL12DT3 CAN0 Message Slot 12 Data 4 C0MSL12DT4 CAN0 Message Slot 12 Data 5 C0MSL12DT5 CAN0 Message Slot 12 Data 6 C0MSL12DT6 CAN0 Message Slot 12 Data 7 C0MSL12DT7 CAN0 Message Slot 13 Extended ID0 C0MSL13EID0 CAN0 Message Slot 13 Data 0 C0MSL13DT0 CAN0 Message Slot 13 Data Length ...

Page 622: ...s count by setting H 0000 6 7 TSP D6 D7 Time stamp prescaler 0 0 Selects CAN bus bit clock 0 1 Selects CAN bus bit clock divided by 2 1 0 Selects CAN bus bit clock divided by 3 1 1 Selects CAN bus bit clock divided by 4 8 9 No functions assigned 0 10 No functions assigned Always write a 0 0 11 FRST 0 Negates rest Forcible reset 1 Forcibly resets 12 BCM 0 Disables BasicCAN function BasicCAN mode 1 ...

Page 623: ...Reset bit D11 When the FRST bit is set to 1 the CAN module is separated from the CAN bus regardless of whether or not the CAN module is communicating and the protocol control unit is reset Note 1 To restart CAN communication the FRST and RST bits must be cleared to 0 Note 2 If the FRST bit is set to 1 during communication the CTX pin output goes high immediately after that Therefore setting the FR...

Page 624: ...by the CAN module itself then the frame can be received Note 1 No ACK is returned for the transmit frame Note 2 Do not change settings of LBM bit when CAN is operating CAN Status Register CRS bit 0 7 RST CAN Reset bit D15 When the RST bit is cleared to 0 the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits Also the CAN Time St...

Page 625: ...BasicCAN status 1 BasicCAN mode 5 No functions assigned 0 6 LBS 0 Normal mode Loopback status 1 Loopback mode 7 CRS 0 Operating CAN reset status 1 Reset 8 RSB 0 Not receiving Receive status 1 Receiving 9 TSB 0 Not transmitting Transmit status 1 Transmitting 10 RSC 0 Reception not completed yet Receive complete status 1 Reception completed 11 TSC 0 Transmission not completed yet Transmit complete s...

Page 626: ... in an error passive state Set condition This bit is set to 1 when the transmit or receive error counter value exceeded 127 and an error passive state is entered Clear condition This bit is cleared when restored from the error passive state D Bit Name Function R W 12 15 MSN Number of message slot which has finished sending or receiving Message slot number 0000 Slot0 0001 Slot1 0010 Slot2 0011 Slot...

Page 627: ...data frame reception Clear condition This bit is cleared by clearing the BCM bit to 0 5 LBS Loopback Status bit D6 When LBS bit 1 it means that the CAN module is operating in loopback mode Set condition This bit is set to 1 by setting the CAN Control Register LBM loopback mode bit to 1 Clear condition This bit is cleared by clearing the LBM bit to 0 6 CRS CAN Reset Status bit D7 When CRS bit 1 it ...

Page 628: ...te Status bit D10 Set condition This bit is set to 1 when the CAN module finished receiving normally regardless of whether any slot exists that meets receive conditions Clear condition This bit is cleared when the CAN module finished transmitting normally 10 TSC Transmit Complete Status bit D11 Set condition This bit is set to 1 when the CAN module finished transmitting normally Clear condition Th...

Page 629: ...t does not have transmit or receive requests set When reset H 0000 D Bit Name Function R W 0 IDE0 Extended ID0 0 Standard ID format 1 IDE1 Extended ID1 1 Extended ID format 2 IDE2 Extended ID2 3 IDE3 Extended ID3 4 IDE4 Extended ID4 5 IDE5 Extended ID5 6 IDE6 Extended ID6 7 IDE7 Extended ID7 8 IDE8 Extended ID8 9 IDE9 Extended ID9 10 IDE10 Extended ID10 11 IDE11 Extended ID11 12 IDE12 Extended ID1...

Page 630: ...0 Settings inhibited 001 Phase Segment2 2Tq 010 Phase Segment2 3Tq 011 Phase Segment2 4Tq 100 Phase Segment2 5Tq 101 Phase Segment2 6Tq 110 Phase Segment2 7Tq 111 Phase Segment2 8Tq 5 7 PH1 Sets Phase Segment1 Phase Segment1 000 Phase Segment1 1Tq 001 Phase Segment1 2Tq 010 Phase Segment1 3Tq 011 Phase Segment1 4Tq 100 Phase Segment1 5Tq 101 Phase Segment1 6Tq 110 Phase Segment1 7Tq 111 Phase Segm...

Page 631: ...Tq 001 Propagation Seqment 2Tq 010 Propagation Seqment 3Tq 011 Propagation Seqment 4Tq 100 Propagation Seqment 5Tq 101 Propagation Seqment 6Tq 110 Propagation Seqment 7Tq 111 Propagation Seqment 8Tq 11 SAM 0 Samples once Number of times sampled 1 Samples three times 12 15 No functions assigned 0 CAN MODULE 13 2 CAN Module Related Registers ...

Page 632: ... bit is sampled When SAM 0 the value sampled at the end of Phase Segment1 is assumed to be the value of the bit When SAM 1 the value of the bit is determined by a majority circuit from values sampled at three points one sampled at the end of Phase Segment1 one sampled before 1Tq and one sampled before 2Tq Table 13 2 1 Typical Settings of Bit Timing when CPU Clock 40 MHz Baud Rate BRP Set Value Tq ...

Page 633: ... The counter is made to start counting by clearing the CAN Control Register CAN0CNT s RST bit to 0 Note 1 The protocol control unit is reset and the counter is initialized to H 0000 by setting the CAN Control Register CAN0CNT s RST CAN Reset bit to 1 Also the counter can be initialized to H 0000 while the CAN module is operating by setting TSR Time Stamp Counter Reset bit to 1 Note 2 During loopba...

Page 634: ...terminate value is stored in this register The count is reset to H 00 upon returning to an error active state CAN0 Transmit Error Count Register CAN0TEC Address H 0080 100B In an error active error passive state a transmit error count is stored in this register When transmitted normally the counter counts down when an error occurs the counter counts up In a bus off state an indeterminate value is ...

Page 635: ...D7 CANBRP This register sets the Tq period of CAN The CAN baud rate is determined by Tq period x number of Tq s for 1 bit Tq period CANBRP 1 CPU clock Number of Tq s for 1 bit Synchronization Segment Progagation Segment Phase Segment 1 Phase Segment 2 Note Setting H 00 divided by 1 is inhibited CAN transfer baud rate 1 Tq period number of Tq s for 1 bit CAN MODULE 13 2 CAN Module Related Registers...

Page 636: ...rrupt request status 1 Interrupt requested 2 SSB2 Slot 2 interrupt request status 3 SSB3 Slot 3 interrupt request status 4 SSB4 Slot 4 interrupt request status 5 SSB5 Slot 5 interrupt request status 6 SSB6 Slot 6 interrupt request status 7 SSB7 Slot 7 interrupt request status 8 SSB8 Slot 8 interrupt request status 9 SSB9 Slot 9 interrupt request status 10 SSB10 Slot 10 interrupt request status 11 ...

Page 637: ...he bits you want to clear are set to 0 and all other bits are set to 1 The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write Note 1 If the automatic response function is enabled for remote frame receive slots the status is set after the CAN module received a remote frame and when it transmitted a data frame Note 2 For remote frame transmit slot...

Page 638: ... IRB12 IRB13 IRB14 IRB15 When reset H 0000 D Bit Name Function R W 0 IRB0 Slot 0 interrupt request mask 0 Masks disables interrupt request 1 IRB1 Slot 1 interrupt request mask 1 Enables interrupt request 2 IRB2 Slot 2 interrupt request mask 3 IRB3 Slot 3 interrupt request mask 4 IRB4 Slot 4 interrupt request mask 5 IRB5 Slot 5 interrupt request mask 6 IRB6 Slot 6 interrupt request mask 7 IRB7 Slot...

Page 639: ... to an error passive state This bit is cleared by writing a 0 in software 3 OIS Bus Off Interrupt Status bit D7 This bit is set to 1 when the CAN module goes to a bus off state This bit is cleared by writing a 0 in software When writing to the CAN error interrupt status make sure the bits you want to clear are set to 0 and all other bits are set to 1 The bits thus set to 1 are unaffected by writin...

Page 640: ...state by enabling or disabling them Error passive interrupt requests are enabled by setting this bit to 1 3 OIM Bus Off Interrupt Mask bit D7 This bit controls interrupt requests generated when the CAN module enters a bus off state by enabling or disabling them Bus off interrupt requests are enabled by setting this bit to 1 D8 9 10 11 12 13 14 D15 EIM PIM OIM When reset H00 D Bit Name Function R W...

Page 641: ...F F SSB4 F F b4 Level 19 source inputs CAN0SLIST H 0080 100C CAN0SLIMK H 0080 1010 Slot 0 transmit receive completed b5 IRB5 F F SSB5 F F b5 b6 IRB6 F F SSB6 F F b6 b7 IRB7 F F To remaining 11 source inputs in the next page F F b7 SSB7 Slot 1 transmit receive completed Slot 2 transmit receive completed Slot 3 transmit receive completed Slot 4 transmit receive completed Slot 5 transmit receive comp...

Page 642: ...IST H 0080 100C CAN0SLIMK H 0080 1010 b13 IRB13 F F SSB13 F F b13 b14 IRB14 F F SSB14 F F b14 b15 IRB15 F F F F b15 SSB15 Data bus Level 19 source inputs Slot 8 transmit receive completed To remaining 3 source inputs in the next page Slot 9 transmit receive completed Slot 10 transmit receive completed Slot 11 transmit receive completed Slot 12 transmit receive completed Slot 13 transmit receive co...

Page 643: ... CAN MODULE 13 2 CAN Module Related Registers b5 EIM F F EIS F F b13 b6 PIM F F PIS F F b14 b7 OIM F F OIS F F b15 CAN0ERIST H 0080 1014 CAN0ERIMK H 0080 1015 CAN bus error occurs Go to error passive state Go to bus off state To preceding page Data bus Level 19 source inputs ...

Page 644: ...dard ID1 C0LMSKAS1 Address H 0080 1031 CAN0 Local Mask Register B Standard ID1 C0LMSKBS1 Address H 0080 1039 When reset H 00 D Bit Name Function R W 0 2 No functions assigned 0 3 7 SID0M SID4M 0 ID not checked Standard ID0 to standard ID4 1 ID checked D0 1 2 3 4 5 6 D7 SID0M SID1M SID2M SID3M SID4M When reset H 00 D Bit Name Function R W 8 9 No functions assigned 0 10 15 SID5M SID10M 0 ID not chec...

Page 645: ...n a bit in this register is set to 1 its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot the received data is stored in it Note 1 SID0M corresponds to the MSB of standard ID Note 2 The Global Mask Register can only be changed when none of slots 0 13 have receive requests set Note 3 The Local Mask Register A can on...

Page 646: ...ed ID0 C0LMSKAE0 Address H 0080 1032 CAN0 Local Mask Register B Extended ID0 C0LMSKBE0 Address H 0080 103A When reset H 00 D Bit Name Function R W 0 3 No functions assigned 0 4 7 EID0M EID3M 0 ID not checked Extended ID0 to extended ID3 1 ID checked D0 1 2 3 4 5 6 D7 EID0M EID1M EID2M EID3M D8 9 10 11 12 13 14 D15 EID4M EID5M EID6M EID7M EID8M EID9M EID10M EID11M When reset H 00 D Bit Name Functio...

Page 647: ...n a bit in this register is set to 1 its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot the received data is stored in it Note 1 EID0M corresponds to the MSB of extended ID Note 2 The Global Mask Register can only be changed when none of slots 0 13 have receive requests set Note 3 The Local Mask Register A can on...

Page 648: ... Slot11 Control Registers COMSL11CNT Address H 0080 105B CAN0 Message Slot12 Control Registers COMSL12CNT Address H 0080 105C CAN0 Message Slot13 Control Registers COMSL13CNT Address H 0080 105D CAN0 Message Slot14 Control Registers COMSL14CNT Address H 0080 105E CAN0 Message Slot15 Control Registers COMSL15CNT Address H 0080 105F When reset H 00 D Bit Name Function R W 0 TR 0 Does not use message...

Page 649: ... or remote frame transmit slot set this bit to 0 If both TR Transmit Request and RR Receive Request bits are set to 1 device operation is indeterminate D Bit Name Function R W 5 ML 0 Message lost not occurred Message slot 1 Message lost occurred 6 TRSTAT For transmit slots Transmit receive status 0 Transmission idle 1 Transmit request accepted For receive slots 0 Reception idle 1 Storing received ...

Page 650: ...slot automatically changes to a transmit slot after receiving a remote frame and transmits the data set in it as a data frame When this bit is set to 1 the message slot stops operating after receiving a remote frame Note Always set this bit to 0 unless the message slot is set for remote frame reception 5 RA Remote Active bit D4 This bit functions differently for slots 0 13 and slots 14 and 15 Slot...

Page 651: ...inished transmitting or receiving When set for transmit slots This bit is set to 1 when the CAN module finished transmitting the data stored in the message slot This bit is cleared by writing a 0 in software However it cannot be cleared when TRSTAT Transmit Receive Status bit 1 When set for receive slots This bit is set to 1 when the CAN module finished receiving normally the data to be stored in ...

Page 652: ...0MSL8SID0 Address H 0080 1180 CAN0 Message Slot 9 Standard ID0 C0MSL9SID0 Address H 0080 1190 CAN0 Message Slot 10 Standard ID0 C0MSL10SID0 Address H 0080 11A0 CAN0 Message Slot 11 Standard ID0 C0MSL11SID0 Address H 0080 11B0 CAN0 Message Slot 12 Standard ID0 C0MSL12SID0 Address H 0080 11C0 CAN0 Message Slot 13 Standard ID0 C0MSL13SID0 Address H 0080 11D0 CAN0 Message Slot 14 Standard ID0 C0MSL14S...

Page 653: ...80 1181 CAN0 Message Slot 9 Standard ID1 C0MSL9SID1 Address H 0080 1191 CAN0 Message Slot 10 Standard ID1 C0MSL10SID1 Address H 0080 11A1 CAN0 Message Slot 11 Standard ID1 C0MSL11SID1 Address H 0080 11B1 CAN0 Message Slot 12 Standard ID1 C0MSL12SID1 Address H 0080 11C1 CAN0 Message Slot 13 Standard ID1 C0MSL13SID1 Address H 0080 11D1 CAN0 Message Slot 14 Standard ID1 C0MSL14SID1 Address H 0080 11E...

Page 654: ...s H 0080 1192 CAN0 Message Slot 10 Extended ID0 C0MSL10EID0 Address H 0080 11A2 CAN0 Message Slot 11 Extended ID0 C0MSL11EID0 Address H 0080 11B2 CAN0 Message Slot 12 Extended ID0 C0MSL12EID0 Address H 0080 11C2 CAN0 Message Slot 13 Extended ID0 C0MSL13EID0 Address H 0080 11D2 CAN0 Message Slot 14 Extended ID0 C0MSL14EID0 Address H 0080 11E2 CAN0 Message Slot 15 Extended ID0 C0MSL15EID0 Address H ...

Page 655: ...H 0080 1193 CAN0 Message Slot 10 Extended ID1 C0MSL10EID1 Address H 0080 11A3 CAN0 Message Slot 11 Extended ID1 C0MSL11EID1 Address H 0080 11B3 CAN0 Message Slot 12 Extended ID1 C0MSL12EID1 Address H 0080 11C3 CAN0 Message Slot 13 Extended ID1 C0MSL13EID1 Address H 0080 11D3 CAN0 Message Slot 14 Extended ID1 C0MSL14EID1 Address H 0080 11E3 CAN0 Message Slot 15 Extended ID1 C0MSL15EID1 Address H 00...

Page 656: ...94 CAN0 Message Slot 10 Extended ID2 C0MSL10EID2 Address H 0080 11A4 CAN0 Message Slot 11 Extended ID2 C0MSL11EID2 Address H 0080 11B4 CAN0 Message Slot 12 Extended ID2 C0MSL12EID2 Address H 0080 11C4 CAN0 Message Slot 13 Extended ID2 C0MSL13EID2 Address H 0080 11D4 CAN0 Message Slot 14 Extended ID2 C0MSL14EID2 Address H 0080 11E4 CAN0 Message Slot 15 Extended ID2 C0MSL15EID2 Address H 0080 11F4 T...

Page 657: ... Slot 10 Data Length Register C0MSL10DLC Address H 0080 11A5 CAN0 Message Slot 11 Data Length Register C0MSL11DLC Address H 0080 11B5 CAN0 Message Slot 12 Data Length Register C0MSL12DLC Address H 0080 11C5 CAN0 Message Slot 13 Data Length Register C0MSL13DLC Address H 0080 11D5 CAN0 Message Slot 14 Data Length Register C0MSL14DLC Address H 0080 11E5 CAN0 Message Slot 15 Data Length Register C0MSL...

Page 658: ...t 9 Data 0 C0MSL9DT0 Address H 0080 1196 CAN0 Message Slot 10 Data 0 C0MSL10DT0 Address H 0080 11A6 CAN0 Message Slot 11 Data 0 C0MSL11DT0 Address H 0080 11B6 CAN0 Message Slot 12 Data 0 C0MSL12DT0 Address H 0080 11C6 CAN0 Message Slot 13 Data 0 C0MSL13DT0 Address H 0080 11D6 CAN0 Message Slot 14 Data 0 C0MSL14DT0 Address H 0080 11E6 CAN0 Message Slot 15 Data 0 C0MSL15DT0 Address H 0080 11F6 These...

Page 659: ...Data 1 C0MSL9DT1 Address H 0080 1197 CAN0 Message Slot 10 Data 1 C0MSL10DT1 Address H 0080 11A7 CAN0 Message Slot 11 Data 1 C0MSL11DT1 Address H 0080 11B7 CAN0 Message Slot 12 Data 1 C0MSL12DT1 Address H 0080 11C7 CAN0 Message Slot 13 Data 1 C0MSL13DT1 Address H 0080 11D7 CAN0 Message Slot 14 Data 1 C0MSL14DT1 Address H 0080 11E7 CAN0 Message Slot 15 Data 1 C0MSL15DT1 Address H 0080 11F7 These reg...

Page 660: ...t 9 Data 2 C0MSL9DT2 Address H 0080 1198 CAN0 Message Slot 10 Data 2 C0MSL10DT2 Address H 0080 11A8 CAN0 Message Slot 11 Data 2 C0MSL11DT2 Address H 0080 11B8 CAN0 Message Slot 12 Data 2 C0MSL12DT2 Address H 0080 11C8 CAN0 Message Slot 13 Data 2 C0MSL13DT2 Address H 0080 11D8 CAN0 Message Slot 14 Data 2 C0MSL14DT2 Address H 0080 11E8 CAN0 Message Slot 15 Data 2 C0MSL15DT2 Address H 0080 11F8 These...

Page 661: ...Data 3 C0MSL9DT3 Address H 0080 1199 CAN0 Message Slot 10 Data 3 C0MSL10DT3 Address H 0080 11A9 CAN0 Message Slot 11 Data 3 C0MSL11DT3 Address H 0080 11B9 CAN0 Message Slot 12 Data 3 C0MSL12DT3 Address H 0080 11C9 CAN0 Message Slot 13 Data 3 C0MSL13DT3 Address H 0080 11D9 CAN0 Message Slot 14 Data 3 C0MSL14DT3 Address H 0080 11E9 CAN0 Message Slot 15 Data 3 C0MSL15DT3 Address H 0080 11F9 These reg...

Page 662: ...t 9 Data 4 C0MSL9DT4 Address H 0080 119A CAN0 Message Slot 10 Data 4 C0MSL10DT4 Address H 0080 11AA CAN0 Message Slot 11 Data 4 C0MSL11DT4 Address H 0080 11BA CAN0 Message Slot 12 Data 4 C0MSL12DT4 Address H 0080 11CA CAN0 Message Slot 13 Data 4 C0MSL13DT4 Address H 0080 11DA CAN0 Message Slot 14 Data 4 C0MSL14DT4 Address H 0080 11EA CAN0 Message Slot 15 Data 4 C0MSL15DT4 Address H 0080 11FA These...

Page 663: ...Data 5 C0MSL9DT5 Address H 0080 119B CAN0 Message Slot 10 Data 5 C0MSL10DT5 Address H 0080 11AB CAN0 Message Slot 11 Data 5 C0MSL11DT5 Address H 0080 11BB CAN0 Message Slot 12 Data 5 C0MSL12DT5 Address H 0080 11CB CAN0 Message Slot 13 Data 5 C0MSL13DT5 Address H 0080 11DB CAN0 Message Slot 14 Data 5 C0MSL14DT5 Address H 0080 11EB CAN0 Message Slot 15 Data 5 C0MSL15DT5 Address H 0080 11FB These reg...

Page 664: ...t 9 Data 6 C0MSL9DT6 Address H 0080 119C CAN0 Message Slot 10 Data 6 C0MSL10DT6 Address H 0080 11AC CAN0 Message Slot 11 Data 6 C0MSL11DT6 Address H 0080 11BC CAN0 Message Slot 12 Data 6 C0MSL12DT6 Address H 0080 11CC CAN0 Message Slot 13 Data 6 C0MSL13DT6 Address H 0080 11DC CAN0 Message Slot 14 Data 6 C0MSL14DT6 Address H 0080 11EC CAN0 Message Slot 15 Data 6 C0MSL15DT6 Address H 0080 11FC These...

Page 665: ... Data 7 C0MSL9DT7 Address H 0080 119D CAN0 Message Slot 10 Data 7 C0MSL10DT7 Address H 0080 11AD CAN0 Message Slot 11 Data 7 C0MSL11DT7 Address H 0080 11BD CAN0 Message Slot 12 Data 7 C0MSL12DT7 Address H 0080 11CD CAN0 Message Slot 13 Data 7 C0MSL13DT7 Address H 0080 11DD CAN0 Message Slot 14 Data 7 C0MSL14DT7 Address H 0080 11ED CAN0 Message Slot 15 Data 7 C0MSL15DT7 Address H 0080 11FD These re...

Page 666: ...Time Stamp C0MSL9TSP Address H 0080 119E CAN0 Message Slot 10 Time Stamp C0MSL10TSP Address H 0080 11AE CAN0 Message Slot 11 Time Stamp C0MSL11TSP Address H 0080 11BE CAN0 Message Slot 12 Time Stamp C0MSL12TSP Address H 0080 11CE CAN0 Message Slot 13 Time Stamp C0MSL13TSP Address H 0080 11DE CAN0 Message Slot 14 Time Stamp C0MSL14TSP Address H 0080 11EE CAN0 Message Slot 15 Time Stamp C0MSL15TSP A...

Page 667: ...terframe space SOF Arbitration field Control field Data field CRC field ACK field EOF 11 1 6 0 64 16 2 7 11 1 1 1 18 6 0 64 16 2 7 SOF EOF 11 1 6 16 2 7 11 1 1 1 18 6 16 2 7 Data frame Remote frame Standard format Extended format Numbers in each field denote the number of bits Standard format Extended format Arbitration field Control field CRC field ACK field 1 1 1 1 Figure 13 3 1 CAN Protocol Fra...

Page 668: ...load frame Interframe space Intermission Bus idle SOF of next frame In an error active state 3 0 SOF Suspend transmission In an error passive state 3 8 0 SOF Numbers in each field denote the number of bits Interframe space or overload flag Intermission Bus idle SOF of next frame Figure 13 3 2 CAN Protocol Frames 2 CAN MODULE 13 3 CAN Protocol ...

Page 669: ...ounter values 1 Error active state This is a state where almost no errors have occurred When an error is detected an active error flag is transmitted Immediately after being initialized the CAN controller is in this state 2 Error passive state This is a state where many errors have occurred When an error is detected a passive error flag is transmitted 3 Bus off state This is a state where a large ...

Page 670: ... off interrupts or CAN slot interrupts set each corresponding bit to 1 to enable interrupt requests 4 Setting bit timing and the number of times sampled Using the CAN Configuration Register and CAN Baud Rate Prescaler set the bit timing and the number of times the CAN bus is sampled Setting the bit timing Determine the period Tq that is the base of bit timing the configuration of Propagation Segme...

Page 671: ... message slots 14 and 15 Set the Message Control Registers 14 and 15 for data frame reception H 40 7 Setting CAN module operation mode Using the CAN Control Register CAN0CNT select the CAN module s operation mode BasicCAN or loopback mode and the clock source for the time stamp counter 8 Releasing the CAN module from reset After you finished settings 1 through 7 above clear the CAN Control Registe...

Page 672: ...ompleted Set interrupt priority Enable disable CAN error passive interrupt Enable disable CAN bus error interrupt Enable disable CAN bus off interrupt Set the number of times sampled Set bit timing baud rate Set ID mask bit Set BasicCAN mode Release CAN module from reset Enable disable interrupt to be generated at completion of transmission or reception in the slot Set CAN Error Interrupt Mask Reg...

Page 673: ...ion has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting transmit data Set the transmit ID and transmit data in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the data as a standard frame or 1 when you want...

Page 674: ...rocedure Initialize CAN Message Slot Control Register Set ID and data in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H 00 Standard ID or extended ID Write H 80 transmit request Read CAN Message Slot Control Register TRSTAT bit 0 YES NO Verify that transmission is idle ...

Page 675: ...arbitration or a CAN bus error occurs while transmitting the CAN module clears the CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 0 If the CAN module requested a transmit abort the transmit abort is accepted and writing to the message slot is enabled 4 Completion of data frame transmission When data frame transmission is completed the CAN Message Slot Control Register s ...

Page 676: ...e message slot The following shows conditions under which transmit abort is accepted Conditions When the target message is waiting for transmission When a CAN bus error occurs during transmission When the CAN module lost bus arbitration CAN MODULE 13 5 Transmitting Data Frames B 1000 0010 B 0000 0001 Note B 1000 0001 B 0000 0000 Note B 1000 0000 Write H 80 Transmit aborted Transmit request accepte...

Page 677: ...TRSTAT Transmit Receive Status bit to see that reception has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting the receive ID Set the ID you want to receive in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a...

Page 678: ...e receive procedure Initialize CAN Message Slot Control Register Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Read CAN Message Slot Control Register TRSTAT bit 0 Write H 00 Standard ID or extended ID Write H 40 receive request Verify that reception is idle ...

Page 679: ...ter s TRSTAT Transmit Receive Status and TRFIN Transmit Receive Finished bits to 1 while at the same time writing the received data to the message slot If the TRFIN Transmit Receive Finished bit is already 1 the CAN module also sets the ML Message Lost bit to 1 indicating that the message slot has been overwritten The message slot has its ID field and DLC field both overwritten and an indeterminat...

Page 680: ...r receive request Finished storing received data Finished storing received data Clear receive request B 0000 0011 B 0100 0111 Store received data B 0100 0101 Finished storing received data Clear receive request B 0000 0111 Store received data Clear receive request Clear receive request B 0000 0101 Finished storing received data Clear receive request Clear receive request Store received data Wait f...

Page 681: ...e C0MSLnCNT register as you clear the TRFIN bit Note 2 If you clear the TRFIN bit by writing H 4E H 40 or H 00 it is possible that new data will be stored in the slot while still reading a message from the slot 2 Reading out from the message slot Read out a message from the message slot 3 Checking the TRFIN Transmit Receive Finished bit Read the CAN Message Control Register to check the TRFIN Tran...

Page 682: ...dure for Reading Out Received Data CAN MODULE 13 6 Receiving Data Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Finished reading out received data Read CAN Message Slot Control Register TRFIN bit 0 YES NO ...

Page 683: ... Receive Status bit to see that transmission has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting transmit ID Set the ID to be transmitted in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the frame as a st...

Page 684: ...it procedure Initialize CAN Message Slot Control Register Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H 00 Standard ID or extended ID Write H A0 transmit request remote Read CAN Message Slot Control Register TRSTAT bit 0 YES NO Verify that transmission is idle ...

Page 685: ...on or a CAN bus error occurs while transmitting the CAN module clears the CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 0 If the CAN module requested a transmit abort the transmit abort is accepted and writing to the message slot is enabled 5 Completion of remote frame transmission When remote frame transmission is completed a time stamp count value at the time transmis...

Page 686: ...he message slot has been overwritten The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area e g extended ID field for standard frame reception and an unused data field Furthermore a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp C0MSLnTSP along with the received data When the ...

Page 687: ...ved data Clear receive request Store received data Clear receive request Finished storing received data B 1010 0001 B 1010 0111 B 0000 0111 B 0000 0101 Finished storing received data Clear receive request Store received data Clear receive request Finished storing received data Finished transmitting remote frame B 1010 0000 Wait for receive data B 1010 1011 B 0000 1011 B 0000 0001 Finished storing ...

Page 688: ...ing H AE or H 00 it is possible that new data will be stored in the slot while still reading a message from the slot Note 3 The received data frame cannot be read out by writing H A0 to the register If you clear the TRFIN bit by writing H A0 the slot performs remote frame transmit operation 2 Reading out from the message slot Read out a message from the message slot 3 Checking the TRFIN Transmit R...

Page 689: ...eceived Data when Set for Remote Frame Transmission CAN MODULE 13 7 Transmitting Remote Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Finished reading out received data Read CAN Message Slot Control Register TRFIN bit 0 YES NO ...

Page 690: ...Set the ID you want to receive in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame 5 Setting the CAN Message Slot Control Register When automatic response data frame transmission for remote frame reception is desired Write H 60 to the CAN Message S...

Page 691: ...ntrol Register Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H 00 Standard ID or extended ID Write H 60 receive request remote automatic response enable Write H 70 receive request remote automatic response disable Read CAN Message Slot Control Register TRSTAT bit 0 YES NO Verify that reception is idle ...

Page 692: ...bit The standard and extended frame types are the same 3 When receive conditions are met When receive conditions in 2 above are met the CAN module sets the CAN Message Slot Control Register s TRSTAT Transmit Receive Status and TRFIN Transmit Receive Finished bits to 1 while at the same time writing the received data to the message slot Furthermore a time stamp count value at the time the message w...

Page 693: ...it slot the CAN module sets the corresponding CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 1 thereby starting transmission If the CAN module failed to gain control of the bus or a CAN bus error occurs If the CAN module failed to gain control of the bus or a CAN bus error occurs while transmitting the CAN module clears the CAN Message Slot Control Register s TRSTAT Tran...

Page 694: ...ed storing received data Clear receive request B 0110 0001 B 0110 0000 B 0111 1000 B 0000 1010 B 0000 0000 Wait for receive data Transmit data frame Clear receive request Finished transmitting data frame Finished transmitting data frame Transmit data frame Finished storing received data Store received data B 0111 1010 B 0111 0000 Finished storing received data Finished storing received data Clear ...

Page 695: ...CHAPTER 14 CHAPTER 14 REAL TIME DEBUGGER RTD 14 1 Outline of the Real Time Debugger RTD 14 2 Pin Function of the RTD 14 3 Functional Description of the RTD 14 4 Typical Connection with the Host ...

Page 696: ...ransfer clock Generated by external host RAM access area Entire area of internal RAM controlled by A16 A29 Transmit receive data length 32 bits fixed Bit transfer sequence LSB first Maximum transfer rate 2 Mbits second Input output pins 4 lines RTDTXD RTDRXD RTDACK RTDCLK Number of commands Following five functions Monitors continuously Outputs real time RAM contents Forcibly rewrites RAM contents...

Page 697: ...pulse synchronously with the beginning clock edge of the output data word The width of the low level pulse thus output indicates the type of instruction data that the RTD received 1 clock period VER continuous monitor command 1 clock period VEI RTD interrupt request command 2 clock periods RDR real time RAM content output command 3 clock periods WRR RAM content forcible rewrite command or the data...

Page 698: ...0 1 0 1 0 1 1 0 VEI VErify Interrupt request RTD interrupt request 0 0 1 0 RDR ReaD RAM Real time RAM content output 0 0 1 1 WRR WRite RAM RAM content forcibly rewrite with verify 1 1 1 1 RCV ReCoVer Recover from runaway Note 2 Note 3 0 0 0 1 System reserved use inhibited Note 1 Note 1 Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command is handl...

Page 699: ...can only be specified on 32 bit word boundaries The two low order address bits specified by a command are ignored Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device Figure 14 3 1 RDR Command Data Format Figure 14 3 2 Operation of the RDR Command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be ...

Page 700: ...0 10 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD Figure 14 3 3 Read Data Transfer Format Note The read data is transferred LSB first 31 D31 1 D0 0 D30 30 D1 Read data Note RTDTXD MSB side LSB side ...

Page 701: ... bits specified by a command are ignored Note also that data are written to the internal RAM in units of 32 bits The external host should transmit the command and address in the first frame and then the write data in the second frame The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data Figure 14 3 4 WRR Command Data Format Note 1 X Don t C...

Page 702: ...ame address immediately after writing to the internal RAM this helps to verify the data written to the internal RAM The read data is output at the timing shown below Note An Specified address D An Data at specified address An D A1 Verify value after write WRR A1 A1 Write data RTDCLK RTDRXD RTDTXD RTDACK WRR A2 A2 Write data D A1 Read value before write 32 clock periods 32 clock periods 32 clock pe...

Page 703: ...s Monitor Command Data Format Figure 14 3 7 Operation of the VER Continuous Monitor Command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Note 1 WRR command can also be used Note 2 An Specified address D An Data at specified address An 31 X 0 0 0 0 19 18 17 16 X 15 0 X 20 RTDRXD MSB side LSB side X Command VER RDR A1 VER RTDCLK RTDRXD RTDTXD ...

Page 704: ... 14 3 9 Operation of the VEI Interrupt Request Command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Note 1 WRR command can also be used Note 2 An Specified address D An Data at specified address An 31 X 0 1 1 0 19 18 17 16 X 15 0 X 20 RTDRXD MSB side LSB side X VEI interrupt request generation command Note Note RTD interrupt RDR A1 VEI RTDCL...

Page 705: ... 14 3 10 RCV Command Data Format Note All of 32 data bits are 1 s The RCV command must always be issued twice in succession Note The next command following the RCV command must have its bits 20 31 all set to 1 Figure 14 3 11 Operation of the RCV Command 31 1 1 1 1 1 19 18 17 16 1 15 0 1 20 RTDRXD MSB side LSB side 1 Command RCV Note Note RCV RCV command stored here RTDCLK RTDRXD RTDTXD RTDACK RCV ...

Page 706: ...use the internal RAM area is located in a 48 KB area ranging from H 0080 4000 to H 0080 FFFF you can set low order 16 bit addresses of that area However access to any locations other than the area where the RAM resides is inhibited Note also that two least significant address bits A31 and A30 are always 0 s because data are read and written to the internal RAM in a fixed length of 32 bits SFR 16KB...

Page 707: ...tatus of the RTD related output pins after a system reset are shown below Table 14 3 2 RTD Pin State after System Reset Pin Name State RTDACK High level output RTDTXD High level output The first command transfer to the RTD after it was reset is initiated by transferring data to the RTDRXD pin synchronously with falling edges of RTDCLK Don t Care RDR A1 RTDCLK RTDRXD RTDTXD RTDACK RESET System rese...

Page 708: ...le the RTDACK level is checked between transfer frames 14 4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data The clock for synchronous is generated by the host An example for connecting the RTD and host is shown below RTDRXD RTDTXD RTDCLK RTDACK M32R E Host microprocessor RXD TXD SCLK PORT Note ...

Page 709: ...When issuing the VER command the RTDACK signal goes low for only one clock period Therefore after sending 32 bits in one frame turn off RTDCLK output and check whether RTDACK is low If RTDACK is low you know that the RTD is communicating normally If you want to identify the type of transmitted command by the width of RTDACK use the 32170 s internal measurement timer to count RTDCLK pulses while RT...

Page 710: ...14 14 16 Ver 0 10 REAL TIME DEBUGGER RTD 14 4 Typical Connection with the Host This is a blank page ...

Page 711: ...CHAPTER 15 CHAPTER 15 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals 15 2 Read Write Operations 15 3 Bus Arbitration 15 4 Typical Connection of External Extension Memory ...

Page 712: ...the timing at which to read data from the bus This signal is driven high when writing to the bus or accessing the internal function ___ ___ 4 Byte High Write Byte High Enable BHW BHE The pin function changes depending on the Bus Mode Control Register BUSMODC ___ When BUSMOD 0 and this signal is Byte High Write BHW during external write access it indicates that the upper byte DB0 DB7 of the data bu...

Page 713: ...ode Register P71MOD bit to 0 Note that the 32170 always inserts one or more wait cycles for external access Therefore the shortest time in which an external device can be accessed is one wait cycle 2 BCLK periods ____ ____ 9 Hold control HREQ HACK The hold state refers to a state in which the 32170 has stopped bus access and bus interface related pins are tristated high impedance While the 32170 i...

Page 714: ...de Register Address H 0080 0747 D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD When reset H 00 D Bit Name Function R W 8 P70MOD 0 P70 Port P70 operation mode __ 1 BCLK WR 9 P71MOD 0 P71 Port P71 operation mode ____ 1 WAIT 10 P72MOD 0 P72 Port P72 operation mode ____ 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode ____ 1 HACK 12 P74MOD 0 P74 Port P74 operation mode 1...

Page 715: ...e Control Register BUSMOD 0 the WR signal is output separately for each byte __ ___ ___ ____ ____ area Signals RD BHW BLW BCLK and WAIT can be used For memory connection in boot mode the Bus Mode Control Register has no effect and the interface operates under conditions where Bus Mode Control Register BUSMOD 0 When Bus Mode Control Register BUSMOD 1 the byte enable signal is output separately for ...

Page 716: ...us In external write cycle BHW or BLW output for the byte position to which to write is pulled low as data is written to the bus ____ When an external bus cycle starts wait cycles are inserted as long as the WAIT signal is low ____ Unless the WAIT signal is needed leave it held high During external bus cycles at least one wait cycle is inserted even for the shortest case access The shortest bus cy...

Page 717: ... Write Timing for Shortest case External Access Note Circles above indicate points at which signals are sampled Read 2 cycles H A A A H H H One wait cycle BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 2 cycles One wait cycle BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write ...

Page 718: ...Cycles Note Circles above indicate points at which signals are sampled H Don t Care AA H A L H AA Don t Care A A A L H AA 1 external wait cycle 2 internal wait cycles A A Read 4 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 4 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 1 external wait cycle 2 internal wait cycles ...

Page 719: ...rom only the byte __ ___ ___ position of the bus In external write cycle the WR signal goes low and BHE or BLE output for the byte position to which to write is pulled low writing data to the necessary byte position ____ When an external bus cycle starts wait cycles are inserted as long as the WAIT signal is low ____ Unless the WAIT signal is needed leave it held high During external bus cycle at ...

Page 720: ... Shortest case External Access Note 1 Circles above indicate points at which signals are sampled Note 2 BCLK is not output H A A A H H H Read 2 cycles One wait cycle BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 2 cycles One wait cycle BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write WR WR ...

Page 721: ...les above indicate points at which signals are sampled Note 2 BCLK is not output H AA AA H A L H AA A A A L H AA A A Don t Care 1 external wait cycle 2 internal wait cycles Read 4 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 4 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write 1 external wait cycle 2 internal wait cycles WR WR Don t Care ...

Page 722: ...ins are placed in the high impedance state allowing data to be transferred on the system bus To exit the hold state and ____ return to normal operating state release the HREQ signal back high Note 1 Circles above indicate points at which signals are sampled Note 2 Hi z indicate the high impedance state Note 3 Idle cycles are inserted only when the hold state is assumed after external lead access D...

Page 723: ... Register 1 ____ When HREQ pin input is pulled low and the hold request is accepted the 32170 goes to a hold state ____ and outputs a low from the HACK pin During hold state all bus related pins are placed in the high impedance state allowing data to be transferred on the system bus To exit the hold state and ____ return to normal operating state release the HREQ signal back high DB0 DB15 BCLK Hi ...

Page 724: ...tion when using external extension memory is shown in Figure 15 4 1 External extension memory can only be used in external extension mode and processor mode Memory mapping Internal flash memory 768KB External memory area 1MB A A A A A A Number of bus wait cycles can be set to 1 4 Normally used as port WAIT is used only when four or more wait cycles are needed H 0000 0000 H 0040 0000 H 0020 0000 H ...

Page 725: ...nsion memory is shown in Figure 15 4 2 External extension memory can only be used in external extension mode and processor mode M32170F6 A11 A30 A A A A D0 D15 A A A A RD CS0 A CS1 BLE BHE A WAIT H 0000 0000 H 0040 0000 H 0020 0000 H 000C 0000 H 0010 0000 A18 A0 A A D15 D0 A A RD CS max1MB A19 A0 A A D15 D0 A A RD D0 D15 CS BHE D0 D7 BLE D8 D15 max2MB WR WR D0 D15 Memory mapping Internal flash mem...

Page 726: ... bus memory located in the CS1 area External extension memory can only be used in external extension mode and processor mode Note The QS32X2245 is a product made by IDT Company A A A A A When CL 50 pF memory can be connected with only 2 ns data delay H 0000 0000 H 0040 0000 H 0020 0000 H 000C 0000 H 0010 0000 8 bit memory A18 A0 AD7 D0 A A RD CS max1MB A19 A0 AA AA D15 D0 AA AA BHE CS WR D0 D15 RD...

Page 727: ...CHAPTER 16 CHAPTER 16 WAIT CONTROLLER 16 1 Outline of the Wait Controller 16 2 Wait Controller Related Registers 16 3 Typical Operation of the Wait Controller ...

Page 728: ...a 2 Mbytes Number of wait cycles 1 to 4 wait cycles inserted by software any number of wait cycles inserted from that can be inserted ____ WAIT pin Bus cycles with 1 wait cycle are the shortest bus cycle for external access ___ ___ In external extension mode and processor mode two chip select signals CS0 CS1 are output to ___ ___ an extended external area Two areas in it corresponding to CS0 and C...

Page 729: ...is extended as long as the WAIT signal is held low Then when the WAIT signal is released back high the wait cycle is terminated and the next new bus cycle is entered into Table 16 1 2 Number of Wait Cycles that Can be Set by the Wait Controller Extended External Area Address Number of Wait Cycles Inserted CS0 area H 0010 0000 H 001F FFFF One to 4 wait cycles set by software any number of External ...

Page 730: ...T CONTROLLER 16 2 Wait Controller Related Registers 16 2 Wait Controller Related Registers The following shows a wait controller related register map H 0080 0180 Address D0 D7 0 Address 1 Address D8 D15 Wait Cycles Control Register WTCCR Blank addresses are a reserved area ...

Page 731: ... Bit Name Function R W 0 1 No functions assigned 0 2 3 CS0WTC 00 4 wait cycles when reset CS0 wait cycles control 01 3 wait cycles 10 2 wait cycles 11 1 wait cycle 4 5 No functions assigned 0 6 7 CS1WTC 00 4 wait cycles when reset CS1 wait cycles control 01 3 wait cycles 10 2 wait cycles 11 1 wait cycle WAIT CONTROLLER 16 2 Wait Controller Related Registers ...

Page 732: ...combination with the wait controller 1 When Bus Mode Control Register 0 ___ External read write operations are performed using the address bus data bus and signals CS0 ___ __ ___ ___ ____ CS1 RD BHW BLW WAIT and BCLK Figure 16 3 1 Internal Bus Access during Bus Free State Note THi Z denotes a high impedance state Bus free state internal bus access H BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD H ...

Page 733: ...ircles above indicate points at which signals are sampled Read 2 cycles H A A A H H H One wait cycle BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 2 cycles One wait cycle BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller ...

Page 734: ...oints at which signals are sampled H Don t Care AA H H A Don t Care H A 2 internal wait cycles Read 3 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 3 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 2 internal wait cycles A A A A WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller ...

Page 735: ...with 3 Internal Wait Cycles Note Circles above indicate points at which signals are sampled H Don t Care AA H H AA Don t Care H AA 3 internal wait cycles Read 4 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 4 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 3 internal wait cycles A A A A A A A A ...

Page 736: ...4 Internal Wait Cycles Note Circles above indicate points at which signals are sampled H Don t Care A H H AA Don t Care H AA 4 internal wait cycles Read 5 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 5 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 4 internal wait cycles A A A A A A A A AA AA AA AA ...

Page 737: ...cles Note Circles above indicate points at which signals are sampled H Don t Care AA H H Don t Care H 4 internal wait cycles Read 6 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 6 cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 4 internal wait cycles AA AA AA AA A A A A A A A A A A L L A A 1 external wait cycle 1 external wait cycle ...

Page 738: ...s Note Circles above indicate points at which signals are sampled H Don t Care AA H H Don t Care H 2 internal wait cycles Read 3 n cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Read Write 3 n cycles BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD Write 2 internal wait cycles AA AA AA AA A A L L A n external wait cycles n external wait cycles L A L A L A L A A ...

Page 739: ... 1 Hi Z denotes a high impedance state Note 2 BCLK is not output 2 When Bus Mode Control Register 1 ___ External read write operations are performed using the address bus data bus and signals CS0 ___ __ ___ ___ ____ __ CS1 RD BHE BLE WAIT and WR H H Hi z H H Bus free state internal bus access BCLK A11 A30 CS0 CS1 BHW BLW DB0 DB15 WAIT RD WR ...

Page 740: ...points at which signals are sampled Note 2 BCLK is not output H A A A H H H Read 2 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 2 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write WR WR 1 internal wait cycle 1 internal wait cycle WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller ...

Page 741: ...ignals are sampled Note 2 BCLK is not output H AA AA H H A A A H A A A Don t Care 2 internal wait cycles Read 3 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 3 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write 2 internal wait cycles WR WR Don t Care WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller ...

Page 742: ...s are sampled Note 2 BCLK is not output WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller H AA AA H H AA A A H AA A A Don t Care 3 internal wait cycles Read 4 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 4 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write 3 internal wait cycles WR WR Don t Care A A A A ...

Page 743: ...e sampled Note 2 BCLK is not output WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller H A A H H AA A A H AA A A Don t Care 4 internal wait cycles Read 5 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 5 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write 4 internal wait cycles WR WR Don t Care A A A AAA AA AA AA ...

Page 744: ...LK is not output WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller H AA AA H H A AA AA H A AA AA Don t Care 4 internal wait cycles Read 6 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 6 cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write 4 internal wait cycles WR WR Don t Care A A A A A A A A L A L A 1 external wait cycle 1 external wait cycle ...

Page 745: ...is not output WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller H AA AA H H A AA AA H A AA AA Don t Care 2 internal wait cycles Read 3 n cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Read Write 3 n cycles BCLK A11 A30 CS0 CS1 BHE BLE DB0 DB15 WAIT RD Write 2 internal wait cycles WR WR Don t Care L A L A n external wait cycles n external wait cycles L A L A L A L A ...

Page 746: ...16 16 20 Ver 0 10 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller This is a blank page ...

Page 747: ...CHAPTER 17 CHAPTER 17 RAM BACKUP MODE 17 1 Outline 17 2 Example of RAM Backup when Power is Down 17 3 Example of RAM Backup for Saving Power Consumption 17 4 Exiting RAM Backup Mode Wakeup ...

Page 748: ...ion in the system can effectively reduced 17 2 Example of RAM Backup when Power is Down A typical circuit for RAM backup at power outage is shown in Figure 17 2 1 The following explains how the RAM can be backed up by using this circuit as an example RAM BACKUP MODE 17 1 Outline Figure 17 2 1 Typical Circuit for RAM Backup at Power Outage Note 1 Power outage is detected by the DC IN regulator inpu...

Page 749: ...e DC IN regulator input voltage Note 2 These pins are used to detect a RAM backup signal Note 3 This pin outputs a high when the power is on and outputs a low when the power is down Note 4 Backup power supply 2 0 to 3 3 V VREFn SBI ADnINi M32R E C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power su...

Page 750: ...nal in Figure 17 2 3 Whether the power is down or not must be determined with respect to the DC IN regulator input voltage in order to allow for a software processing time at power outage To enable RAM backup mode make the following settings 1 Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally in Figure 17 2 3 When the power s...

Page 751: ...t as an example Figure 17 3 1 Typical Circuit for RAM Backup to Save on Power Consumption Note 1 This signal outputs a low for RAM backup Note 2 This pin outputs a high when the power is on and is set for input mode when in RAM backup mode Note 3 These pins are used to detect a RAM backup signal RAM backup signal Note 1 External circuit Port X IB RAM backup power supply DC IN Input Output Regulato...

Page 752: ...ation the RAM ___ backup signal output by the external signal is high Also input on the SBI pin or ADnINi i 0 15 pin used for RAM backup signal detection remains high Port X which is the transistor s base connecting pin should output a high This causes the transistor s base voltage IB to go high so that current is fed from the power supply to the VCC pin via the transistor RAM backup signal Note 1...

Page 753: ...er the RAM data has been retained normally in Figure 17 3 3 2 To materialize low power operation set all programmable input output pins except port X for input mode or for output mode with pins outputting a low in Figure 17 3 3 3 Set port X for input mode B and in Figure 17 3 3 This causes the transistor s base voltage IB to go low so that no current flows from the power supply to the VCC pin via ...

Page 754: ... is indeterminate Therefore be sure to set the output high level in the Port X Data Register before you set port X for output mode Unless this method is followed port output may go low at the same time port output is set after the clock oscillation has stabilized causing the device to enter RAM backup mode RESET SBI ADnINi VCCI OSC VCC VDD Oscillation stabilization time External input signal goes ...

Page 755: ...created before entering RAM backup mode in Figure 17 4 1 4 If the RAM contents and check data did not match when checked in 3 initialize the RAM in Figure 17 4 1 If the RAM contents and check data matched use the retained data in the program 5 After initializing each internal circuit in Figure 17 4 1 return the main routine in Figure 17 4 1 Note For wakeup from power outage RAM backup mode setting...

Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...

Page 757: ...CHAPTER 18 CHAPTER 18 OSCILLATION CIRCUIT 18 1 Oscillator Circuit 18 2 Clock Generator Circuit ...

Page 758: ...1 1 Example of an Oscillator Circuit A clock generating circuit can be configured by connecting a ceramic or crystal resonator between the XIN and XOUT pins external to the chip Figure 18 1 1 below shows an example of a system clock generating circuit using a resonator connected external to the chip and an RC network connected to the PLL circuit control pin VCNT For constants Rf CIN COUT and Rd co...

Page 759: ...wn below P7 Operation Mode Register P7MOD Address H 0080 0747 D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD When reset H 00 D Bit Name Function R W 8 P70MOD 0 P70 Port P70 operation mode 1 BCLK 9 P71MOD 0 P71 Port P71 operation mode ____ 1 WAIT 10 P72MOD 0 P72 Port P72 operation mode ____ 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode ____ 1 HACK 12 P74MOD 0 P74 P...

Page 760: ...er on The oscillator circuit comprised of a ceramic or crystal resonator has a finite time after power on at which its oscillation is instable Therefore create a certain amount of oscillation stabilization time that suits the oscillator circuit used Figure 18 1 2 shows an oscillation stabilization time at power on RESET XIN Oscillation stabilization time OSC VCC ...

Page 761: ... OSCILLATION CIRCUIT 18 2 Clock Generator Circuit 18 2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits XIN 8MHz 10MHz BCLK 16MHz 20MHz CPU clock 32MHz 40MHz X4 1 2 1 2 internal peripheral clock 8MHz 10MHz 1 4 ...

Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...

Page 763: ...TER 19 JTAG 19 1 Outline of JTAG 19 2 Configuration of the JTAG Circuit 19 3 JTAG Registers 19 4 Basic Operation of JTAG 19 5 Boundary Scan Description Language 19 6 Precautions about Board Design when Connecting JTAG ...

Page 764: ...Synchronous serial data input pin used to enter test instruction code and test data This input is sampled on rising edges of JTCK JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data This signal changes state on falling edges of JTCK and is output only in Shift IR or Shift DR state JTMS Test mode select Input Test mode select input to c...

Page 765: ...scan path A set of data registers which are accessed through the boundary scan path Test access port abbreviated TAP controller to control the JTAG unit s state transitions Control logic to select input output etc A configuration of the JTAG circuit is shown below JTCK JTMS JTRST TAP controller Instruction register 6 bits JTAGIR Decoder JTDO ID code register JTAGIDR Bypass register JTAGBPR Boundar...

Page 766: ...s Note that if this operation is performed the device may inadvertently handle b 110001 as instruction code which makes it unable to operate normally Capture IR Exit1 IR Update IR The 32170 s JTAG interface supports the following instructions Three instructions stipulated as essential in IEEE 1149 1 EXTEST SAMPLE PRELOAD BYPASS Device ID register access instruction IDCODE Table 19 3 1 JTAG Instruc...

Page 767: ...est Connected between the JTDI and JTDO pins this register is selected when issuing BYPASS instruction This register when in Capture DR state has b 0 fixed value loaded into it 3 ID Code Register JTAGIDR The ID Code Register is a 32 bit register used to identify the device and manufacturer It holds the following information Version information 4 bits b 0000 Part number 16 bits b 0011 0010 0010 000...

Page 768: ... outside through the boundary scan path The sampled value is output to an external device at the same time data is set from outside As register operation bits are shifted right between each shift register stage Update operation The data set from outside during shift is driven As register operation the value set in the shift register stage is transferred to the parallel output stage The JTAG interf...

Page 769: ...4 1 TAP Controller State Transition Note Values 0 and 1 in this diagram denote the state of JTMS input signal Select DR Scan Test Logic Reset Run Test Idle 0 1 0 Capture DR 0 Shift DR 0 Exit1 DR 1 Pause DR 0 Exit2 DR 1 Update DR 1 0 0 1 0 1 1 0 Select IR Scan Capture IR 0 Shift IR 0 Exit1 IR 1 Pause IR 0 Exit2 IR 1 Update IR 1 0 0 1 0 1 1 0 1 1 1 Data input G 0 1 D T Q D T R Q Shift DR or Shift IR...

Page 770: ...the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit Because instruction code is set in the instruction register which is comprised of 6 bits the Shift IR state continues for a period of 6 JTCK cycles To stop the shift operation in the middle go to Pause IR state via temporarily Exit1 IR state by setting JTMS input from high to low Also to return fr...

Page 771: ...s 1 0 0 0 1 1 LSB value JTMS TAP state JTDI JTDO High impedance Shift output from the instruction register is fixed to b 110001 Finished storing instruction code in the instruction register s shift register stage Instruction code is set in the parallel output stage at fall of JTCK in Update IR state JTDI input is sampled at rise of JTCK in Shift IR state JTDO is output at fall of JTCK in Shift IR ...

Page 772: ... data that was set in 2 is serially output from the JTDO in At the same time the setup data serially entered from the JTDI pin is set in the data register s shift register stage bit by bit By continuing the Shift DR state as long as the number of bits of the selected data register by entering JTMS low all bits of data can be set in and read out from the shift register stage To stop the shift opera...

Page 773: ...e JTCK Select DR Scan Capture DR Shift DR Exit1 DR Update DR Run Test Idle Run Test Idle Don t Care Don t Care JTMS JTDI JTDO Finished storing setup data in the shift register stage of the selected data register Setup data is set in the parallel output stage at fall of JTCK in Update DR state JTDI input is sampled at rise of JTCK in Shift DR state A A A A A A A A A A A A A TAP state LSB value High...

Page 774: ...idle state hold JTMS input low 3 Set JTMS high to exit Run Test Idle state and perform IR path sequence In IR path sequence specify the data register you want to inspect or set 4 Subsequently perform DR path sequence For the data register specified in IR path sequence enter setup data from the JTDI pin and read out reference data from the JTDO pin 5 If after DR path sequence is completed you want ...

Page 775: ...g Capture DR state Specify the data register you want to inspect or set Test Logic Reset state Run Test Idle state IR path sequence TAP states Instruction code 0 Setup data 0 JTDI Note 1 Fixed value b 110001 Note 3 JTDO Note 2 Setup data is entered serially from JTDI Reference data is serially output from JTDO 1 Basic access Same data register can be operated on to inspect or set data continuously...

Page 776: ...output input output buffer or link of each pin that defines the logical direction of signal flow Physical pin map The physical pin map correlates the chip s logical ports to the physical pins on each package Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description Instruction set statement The instruction set statement writes bit patterns to...

Page 777: ...bit P44 inout bit P45 inout bit P46 inout bit P47 inout bit P220 inout bit P221 in bit P222 inout bit P223 inout bit P224 inout bit P225 inout bit VSS_17 linkage bit OSCVSS_18 linkage bit XIN in bit XOUT buffer bit OSCVCC_21 linkage bit VSS_22 linkage bit VCNT_23 linkage bit VSS_24 linkage bit P30 inout bit P31 inout bit P32 inout bit P33 inout bit P34 inout bit P35 inout bit P36 inout bit P37 ino...

Page 778: ...t AD0IN2 linkage bit AD0IN3 linkage bit AD0IN4 linkage bit AD0IN5 linkage bit AD0IN6 linkage bit AD0IN7 linkage bit AD0IN8 linkage bit AD0IN9 linkage bit AD0IN10 linkage bit AD0IN11 linkage bit AD0IN12 linkage bit AD0IN13 linkage bit AD0IN14 linkage bit AD0IN15 linkage bit AVSS_79 linkage bit VCCE_80 linkage bit VSS_81 linkage bit P180 inout bit P181 inout bit P182 inout bit P183 inout bit P184 in...

Page 779: ...4 inout bit P85 inout bit P86 inout bit P87 inout bit P200 inout bit P201 inout bit P202 inout bit P203 inout bit VCCI_126 linkage bit VSS_127 linkage bit FVCC_128 linkage bit VSS_129 linkage bit P61 inout bit P62 inout bit P63 inout bit P64 in bit P65 inout bit P66 inout bit P67 inout bit VCCI_137 linkage bit VSS_138 linkage bit VCCE_139 linkage bit P70 inout bit P71 inout bit P72 inout bit P73 i...

Page 780: ...bit P211 inout bit P212 inout bit P213 inout bit P214 inout bit P215 inout bit P216 inout bit P217 inout bit TMS in bit TCK in bit TRST in bit TDO out bit TDI in bit P103 inout bit P104 inout bit P105 inout bit P106 inout bit P107 inout bit P124 inout bit P125 inout bit P126 inout bit P127 inout bit VCCI_195 linkage bit VSS_196 linkage bit P130 inout bit P131 inout bit P132 inout bit P133 inout bi...

Page 781: ...0 linkage bit AD1IN1 linkage bit AD1IN2 linkage bit AD1IN3 linkage bit AD1IN4 linkage bit AD1IN5 linkage bit AD1IN6 linkage bit AD1IN7 linkage bit AD1IN8 linkage bit AD1IN9 linkage bit AD1IN10 linkage bit AD1IN11 linkage bit use STD_1149_1_1994 all attribute COMPONENT_CONFORMANCE of M32170F6VFP entity is STD_1149_1_1993 attribute PIN_MAP of M32170F6VFP entity is PHYSICAL_PIN_MAP constant P6Y240_A ...

Page 782: ...35 30 P36 31 P37 32 P20 33 P21 34 P22 35 P23 36 VCCE_37 37 VSS_38 38 P24 39 P25 40 P26 41 P27 42 P00 43 P01 44 P02 45 P03 46 P04 47 P05 48 P06 49 P07 50 VCCE_51 51 VSS_52 52 P10 53 P11 54 P12 55 P13 56 P14 57 P15 58 P16 59 P17 60 VREF_61 61 AVCC_62 62 AD0IN0 63 AD0IN1 64 AD0IN2 65 AD0IN3 66 AD0IN4 67 AD0IN5 68 AD0IN6 69 AD0IN7 70 AD0IN8 71 AD0IN9 72 AD0IN10 73 AD0IN11 74 AD0IN12 75 AD0IN13 76 ...

Page 783: ... 87 P186 88 P187 89 P190 90 P191 91 P192 92 P193 93 P194 94 P195 95 P196 96 P197 97 VCCI_98 98 VSS_99 99 P160 100 P161 101 P162 102 P163 103 P164 104 P165 105 P166 106 P167 107 P172 108 P173 109 P174 110 P175 111 P176 112 P177 113 VCCE_114 114 VSS_115 115 P82 116 P83 117 P84 118 P85 119 P86 120 P87 121 P200 122 P201 123 P202 124 P203 125 VCCI_126 126 VSS_127 127 FVCC_128 128 VSS_129 129 P61 130 P6...

Page 784: ... 143 P74 144 P75 145 P76 146 P77 147 P93 148 P94 149 P95 150 P96 151 P97 152 RESET 153 MOD0 154 MOD1 155 FP 156 VCCE_157 157 VSS_158 158 P110 159 P111 160 P112 161 P113 162 P114 163 P115 164 P116 165 P117 166 P100 167 P101 168 P102 169 VDD_170 170 VCCI_171 171 VSS_172 172 P210 173 P211 174 P212 175 P213 176 P214 177 P215 178 P216 179 P217 180 TMS 181 TCK 182 TRST 183 TDO 184 TDI 185 P103 186 P104 ...

Page 785: ...6 206 P140 207 P141 208 P142 209 P143 210 P144 211 P145 212 P146 213 P147 214 P150 215 P151 216 P152 217 P153 218 P154 219 P155 220 P156 221 P157 222 P41 223 P42 224 VCCI_225 225 VSS_226 226 VREF_227 227 AVCC_228 228 AD1IN0 229 AD1IN1 230 AD1IN2 231 AD1IN3 232 AD1IN4 233 AD1IN5 234 AD1IN6 235 AD1IN7 236 AD1IN8 237 AD1IN9 238 AD1IN10 239 AD1IN11 240 attribute TAP_SCAN_IN of TDI signal is true attri...

Page 786: ...CCESS 010011 DMA_RADDR 011000 DMA_RDATA 011001 DMA_RTYPE 011010 DMA_ACCESS 011011 RTDENB 100000 attribute INSTRUCTION_CAPTURE of M32170F6VFP entity is 110001 attribute INSTRUCTION_PRIVATE of M32170F6VFP entity is MDM_SYSTEM MDM_CONTROL MDM_SETUP MTM_CONTROL MON_CODE MON_DATA MON_PARAM MON_ACCESS DMA_RADDR DMA_RDATA DMA_RTYPE DMA_ACCESS RTDENB attribute IDCODE_REGISTER of M32170F6VFP entity is 0000...

Page 787: ... Z 468 BC_1 control 0 467 BC_4 P104 observe_only X 466 BC_1 P104 output3 X 465 0 Z 465 BC_1 control 0 464 BC_4 P105 observe_only X 463 BC_1 P105 output3 X 462 0 Z 462 BC_1 control 0 461 BC_4 P106 observe_only X 460 BC_1 P106 output3 X 459 0 Z 459 BC_1 control 0 458 BC_4 P107 observe_only X 457 BC_1 P107 output3 X 456 0 Z 456 BC_1 control 0 455 BC_4 P124 observe_only X 454 BC_1 P124 output3 X 453 0...

Page 788: ... BC_1 P142 output3 X 411 0 Z 411 BC_1 control 0 410 BC_4 P143 observe_only X 409 BC_1 P143 output3 X 408 0 Z 408 BC_1 control 0 407 BC_4 P144 observe_only X 406 BC_1 P144 output3 X 405 0 Z 405 BC_1 control 0 404 BC_4 P145 observe_only X 403 BC_1 P145 output3 X 402 0 Z 402 BC_1 control 0 401 BC_4 P146 observe_only X 400 BC_1 P146 output3 X 399 0 Z 399 BC_1 control 0 398 BC_4 P147 observe_only X 397...

Page 789: ...l 0 356 BC_4 P46 observe_only X 355 BC_1 P46 output3 X 354 0 Z 354 BC_1 control 0 353 BC_4 P47 observe_only X 352 BC_1 P47 output3 X 351 0 Z 351 BC_1 control 0 350 BC_4 P220 observe_only X 349 BC_1 P220 output3 X 348 0 Z 348 BC_1 control 0 347 BC_4 P221 observe_only X 346 BC_4 P222 observe_only X 345 BC_1 P222 output3 X 344 0 Z 344 BC_1 control 0 343 BC_4 P223 observe_only X 342 BC_1 P223 output3 ...

Page 790: ... 300 BC_1 P23 output3 X 299 0 Z 299 BC_1 control 0 298 BC_4 P24 observe_only X 297 BC_1 P24 output3 X 296 0 Z 296 BC_1 control 0 295 BC_4 P25 observe_only X 294 BC_1 P25 output3 X 293 0 Z 293 BC_1 control 0 292 BC_4 P26 observe_only X 291 BC_1 P26 output3 X 290 0 Z 290 BC_1 control 0 289 BC_4 P27 observe_only X 288 BC_1 P27 output3 X 287 0 Z 287 BC_1 control 0 286 BC_4 P00 observe_only X 285 BC_1 ...

Page 791: ...6 observe_only X 243 BC_1 P16 output3 X 242 0 Z 242 BC_1 control 0 241 BC_4 P17 observe_only X 240 BC_1 P17 output3 X 239 0 Z 239 BC_1 control 0 238 BC_4 P180 observe_only X 237 BC_1 P180 output3 X 236 0 Z 236 BC_1 control 0 235 BC_4 P181 observe_only X 234 BC_1 P181 output3 X 233 0 Z 233 BC_1 control 0 232 BC_4 P182 observe_only X 231 BC_1 P182 output3 X 230 0 Z 230 BC_1 control 0 229 BC_4 P183 o...

Page 792: ... 0 Z 188 BC_1 control 0 187 BC_4 P161 observe_only X 186 BC_1 P161 output3 X 185 0 Z 185 BC_1 control 0 184 BC_4 P162 observe_only X 183 BC_1 P162 output3 X 182 0 Z 182 BC_1 control 0 181 BC_4 P163 observe_only X 180 BC_1 P163 output3 X 179 0 Z 179 BC_1 control 0 178 BC_4 P164 observe_only X 177 BC_1 P164 output3 X 176 0 Z 176 BC_1 control 0 175 BC_4 P165 observe_only X 174 BC_1 P165 output3 X 173...

Page 793: ... 132 BC_1 P87 output3 X 131 0 Z 131 BC_1 control 0 130 BC_4 P200 observe_only X 129 BC_1 P200 output3 X 128 0 Z 128 BC_1 control 0 127 BC_4 P201 observe_only X 126 BC_1 P201 output3 X 125 0 Z 125 BC_1 control 0 124 BC_4 P202 observe_only X 123 BC_1 P202 output3 X 122 0 Z 122 BC_1 control 0 121 BC_4 P203 observe_only X 120 BC_1 P203 output3 X 119 0 Z 119 BC_1 control 0 118 BC_4 P61 observe_only X 1...

Page 794: ...Z 76 BC_1 control 0 75 BC_4 P93 observe_only X 74 BC_1 P93 output3 X 73 0 Z 73 BC_1 control 0 72 BC_4 P94 observe_only X 71 BC_1 P94 output3 X 70 0 Z 70 BC_1 control 0 69 BC_4 P95 observe_only X 68 BC_1 P95 output3 X 67 0 Z 67 BC_1 control 0 66 BC_4 P96 observe_only X 65 BC_1 P96 output3 X 64 0 Z 64 BC_1 control 0 63 BC_4 P97 observe_only X 62 BC_1 P97 output3 X 61 0 Z 61 BC_1 control 0 60 BC_4 RE...

Page 795: ...BC_1 control 0 26 BC_4 P102 observe_only X 25 BC_1 P102 output3 X 24 0 Z 24 BC_1 control 0 23 BC_4 P210 observe_only X 22 BC_1 P210 output3 X 21 0 Z 21 BC_1 control 0 20 BC_4 P211 observe_only X 19 BC_1 P211 output3 X 18 0 Z 18 BC_1 control 0 17 BC_4 P212 observe_only X 16 BC_1 P212 output3 X 15 0 Z 15 BC_1 control 0 14 BC_4 P213 observe_only X 13 BC_1 P213 output3 X 12 0 Z 12 BC_1 control 0 11 BC...

Page 796: ...t wiring lengths be matched during board design Figure 19 6 1 Precautions to Be Observed when Connecting JTAG Tool when Using the 240QFP M32R E JTDI JTMS JTCK JTRST User board JTAG tool Make sure wiring lengths are the same and avoid bending wires as much as possible Also do not use through holes within wiring JTDO 33Ω VCCE 5V 2KΩ 10KΩ 0 1µF SDI connector JTAG connector Power TDI TMS TCK TRST TDO ...

Page 797: ...AAA DBI TRCLK TRSYNC TRDATA 0 7 EVENT 0 1 DBI TRCLK TRSYNC When connecting emulator TRDATA 0 7 EVENT 0 1 8 2 M32R E JTDI JTMS JTCK JTRST When connecting JTAG tool JTDO 33Ω VCCE 5V 2KΩ 10KΩ 0 1µF SDI connector JTAG connector Power TDI TMS TCK TRST TDO GND 33Ω 10KΩ 33Ω 10KΩ 33Ω 10KΩ 33Ω User board 33Ω 33Ω 33Ω 33Ω 33Ω 10KΩ Make sure wiring lengths are the same and avoid bending wires as much as possi...

Page 798: ...19 19 36 Ver 0 10 JTAG 19 6 Precautions about Board Design when Connecting JTAG This is a blank page ...

Page 799: ...CHAPTER 20 CHAPTER 20 POWER UP POWER SHUTDOWN SEQUENCE 20 1 Configuration of the Power Supply Circuit 20 2 Power Up Sequence 20 3 Power Shutdown Sequence ...

Page 800: ...igure 20 1 1 Configuration of the Power Supply Circuit Table 20 1 1 List of Power Supply Functions Type of Power Supply Pin Name Function 5 0 V system VCCE Supplies power to external I O ports AVCC0 AVCC1 Power supply for A D converter VREF0 VREF1 Reference voltage for A D converter 3 3 V system VCCI Supplies power to internal logic FVCC Power supply for internal flash memory VDD Power supply for ...

Page 801: ...r supply after turning on the 5 V power supply ____________ After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time release the RESET pin input back high to deactivate reset Note Power on limitations VDD OSC VCC VCCI FVCC VCCE VCCI FVCC OSC VCC Figure 20 2 1 Power On Sequence When Not Using RAM Backup VCCE AVCC0 AVCC1 VREF0 VREF1 RESET V...

Page 802: ...3 3 V power supply after turning on the 5 V power supply ____________ After turning on all power supplies and holding the RESET pin low for an oscillation ____________ stabilization time release the RESET pin input back high to deactivate reset Note Power on limitations VDD OSC VCC VCCI FVCC VCCE VCCI FVCC OSC VCC VCCE AVCC0 AVCC1 VREF0 VREF1 RESET VDD VCCI FVCC OSC VCC 5V 5V 5V 5V 3 3V 3 3V 3 3V ...

Page 803: ...________ Pull the RESET pin input low ____________ Turn off the 5 V and the 3 V power supply after the RESET pin goes low Note Power shutdown requirements VDD VCCI FVCC OSC VCC VCCI Figure 20 3 1 Power Shutdown Sequence When Not Using RAM Backup POWER UP POWER SHUTDOWN SEQUENCE 20 3 Power Shutdown Sequence VCCE AVCC0 AVCC1 VREF0 VREF1 RESET VDD VCCI FVCC OSC VCC 5V 5V 5V 5V 3 3V 3 3V 3 3V 3 3V 0V ...

Page 804: ...0V 0V 0V 0V 0V 2 0V 2 1 3 3 4 __________ Pull the HREQ pin input low to halt the CPU at end of bus cycle Or disable RAM access in software The M32R E allows P72 to be used as HREQ irrespective of its operation mode ____________ With the CPU halted pull the RESET pin input low Or while RAM access is disabled pull ____________ the RESET pin input low ____________ Turn off the 5 V and the 3 3 V power...

Page 805: ...own Sequence OSC VCC FVCC VDD VCCI AVCC VCCE M32R E 5V power supply 3 3V power supply I O control circuit A D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V 3 3V OSC VCC FVCC VDD VCCI AVCC VCCE M32R E I O control circuit A D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 0V 3 3V 5V power supply 3 3V power supply ...

Page 806: ...DD VCCI AVCC VCCE M32R E 0V 5V I O control circuit A D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V power supply 3 3V power supply OSC VCC FVCC VDD VCCI AVCC VCCE M32R E 0V 0V 3 3V 2 0V I O control circuit A D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V power supply 3 3V power supply ...

Page 807: ...CHAPTER 21 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21 1 Absolute Maximum Ratings 21 2 Recommended Operating Conditions 21 3 DC Characteristics 21 4 A D Conversion Characteristics 21 5 AC Characteristics ...

Page 808: ...xternal I O Buffer Voltage VCCE AVCC VREF Xout 0 3 to 6 5 40 to 125 65 to 150 0 3 to OSC VCC 0 3 0 3 to VCCE 0 3 0 3 to OSC VCC 0 3 600 0 3 to VCCE 0 3 V V Other Other 0 3 to 4 2 0 3 to 4 2 0 3 to 4 2 0 3 to 6 5 0 3 to 6 5 Rated Value mW 500 VDD VCCI FVCC OSC VCC VDD VCCI FVCC OSC VCC VDD VCCI FVCC OSC VCC VCCE AVCC VREF VCCE AVCC VREF ELECTRICAL CHARACTERISTICS 21 1 Absolute Maximum Ratings 21 1 ...

Page 809: ...er Supply Voltage Note2 AVCC Analog Power Supply Voltage Note1 VREF Analog Reference Voltage Note1 VIH Input High Voltage MIN TYP MAX VIL Input Low Voltage IOH peak IOH avg IOL peak IOL avg mA mA mA mA MHz f XIN FVCC Flash Power Supply Voltage Note2 PLL Power Supply Voltage Note2 OSC VCC VCCI Internal Logic Power Supply Voltage Note2 4 5 5 0 5 5 3 0 3 3 3 6 3 3 5 0 3 3 5 0 Ports P0 P1 external ext...

Page 810: ...e 2 AVCC Analog Power Supply Voltage Note 1 VREF Analog Reference Voltage Note 1 VIH Input High Voltage MIN TYP MAX VIL Input Low Voltage IOH peak IOH avg IOL peak IOL avg mA mA mA mA MHz f XIN FVCC Flash Power Supply Voltage Note 2 PLL Power Supply Voltage Note 2 OSC VCC VCCI Internal Logic Power Supply Voltage Note 2 4 5 5 0 5 5 3 0 3 3 3 6 3 3 5 0 3 3 5 0 Ports P0 P1 external extension processo...

Page 811: ...CAL CHARACTERISTICS 21 3 DC Characteristics ICC 5V 5 V power supply Note 1 100 2000 f XIN 10 0MHz When reset Ta 25 C Ta 85 C 1 IDDhold See RAM retention power supply current characteristic graph 1 10 ICCI 3V 3 3 V power supply Note 2 75 125 75 VOH Output High Voltage V VDD RAM Retention Power Supply Voltage V IIH µA IIL VOL Output Low Voltage V VCCE 1 0 45 VCCI IOH 2mA IOL 2mA VI VCCE VI 0V 3 0 2 ...

Page 812: ...when operating OSCVCC power supply current when operating FVCC power supply current when operating Note 1 VDD power supply current when operating Note 2 AVCC power supply current when operating VREF power supply current Symbol Rated Value Unit MIN TYP MAX Condition f XIN 10 0MHZ f XIN 10 0MHZ f XIN 10 0MHZ f XIN 10 0MHZ f XIN 10 0MHZ f XIN 10 0MHZ Parameter Note 1 Maximum value including currents ...

Page 813: ...dual functions ICC 5V 5 V power supply Note 1 100 7500 f XIN 8 0MHz When reset Ta 25 C Ta 125 C 1 IDDhold See RAM retention power supply current characteristic graph 1 10 ICCI 3V 3 3 V power supply Note 2 60 110 70 VOH Output High Voltage V VDD RAM Retention Power Supply Voltage V IIH µA IIL VOL Output Low Voltage V VCCE 1 0 45 VCCI IOH 2mA IOL 2mA VI VCCE VI 0V 3 0 2 0 5 5 High State Input Curren...

Page 814: ... CHARACTERISTICS 21 3 DC Characteristics IVREF mA mA ICCE VCCE power supply current when operating f XIN 8 0MHZ ICCI IOSCVCC IDD 30 IAVCC mA mA mA 10 105 16 3 1 50 FICC mA VCCI power supply current when operating OSCVCC power supply current when operating FVCC power supply current when operating Note 1 VDD power supply current when operating Note 2 AVCC power supply current when operating VREF pow...

Page 815: ...0 PRELIMINARY PRELIMINARY ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics RAM retention power supply current in a standard sample reference value 1 10 100 1000 1 2 3 4 1 5 3 6 Ta 25 C Ta 85 C Ta 125 C IDD µA VDD V ...

Page 816: ...CE 5 V 0 5 V VCCI 3 3 V 0 3 V Unless Otherwise Noted Ifvcc1 FVCC Power Supply Current when Programming mA lfvcc2 FVCC Power Supply Current when Erasing mA 50 40 Flash Rewrite Ambient Temperature Topr 0 70 C cycle Rewrite Durability 100 times Symbol Parameter Rated Value Unit MIN TYP MAX Condition ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics ...

Page 817: ...ote 1 LSB Offset Error LSB 10 2 2 Full scale Error LSB TCONV Conversion Time Number of internal peripheral clock 2 299 IIAN Analog Input Leakage Current nA 200 200 Note 2 During normal mode During double speed mode 173 VREF VCC Symbol Parameter Rated Value Unit MIN TYP MAX Condition Note 1 The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset full scal...

Page 818: ...ing characteristics 1 Input output ports 2 Serial I O a CSIO mode with internal clock selected b CSIO mode with external clock selected tsu D CLK RxD Input Setup Time ns 150 4 th CLK D ns 50 5 RxD Input Hold Time tc CLK CLK Input Cycle Time ns 640 7 tw CLKH ns 300 8 CLK Input High Pulse Width tw CLKL ns 300 9 CLK Input Low Pulse Width tsu D CLK ns 60 10 RxD Input Setup Tim th CLK D ns 11 RxD Input...

Page 819: ...KH WAITL 26 0 ns 34 tsu WAITH BCLKH WAIT Input Setup Time before BCLK ns 78 WAIT Input Hold Time after BCLK th BCLKH WAITH 26 0 ns 79 tw BLWL Write Low Pulse Width Byte write mode ns 51 tc BCLK 25 tw BHWL tw RDL Read Low Pulse Width ns 43 Data Input Setup Time before Read tsu D RDH 30 ns 44 Data Input Hold Time after Read th RDH D 45 ns 0 tc BCLK 2 23 3 td RDH BLWL Write Delay Time after Read ns 5...

Page 820: ...0 15 20 40 40 60 tc JTCK ns See Figure 21 5 11 Symbol Rated Value Unit MIN MAX Condition tr ns 58 ns Input Rising Transition Time tf ns ns 59 Input Falling Transition Time Other than JTRST pin JTRST pin Other than JTRST pin JTRST pin JTCK JTDI JTMS JTDO When using TAP When not using TAP JTCK JTDI JTMS JTDO 10 10 2 10 10 2 ms ms See Figure 21 5 10 Symbol Rated Value Unit MIN MAX Condition When usin...

Page 821: ...ics td E P Port Data Output Delay Time ns 100 3 See Figure 21 5 1 Symbol Parameter Rated Value Unit MIN MAX Condition td CLK D TxD Output Delay Time 12 td CLK D TxD Output Delay Time ns 160 6 ns 160 See Figure 21 5 2 Symbol Parameter Rated Value Unit MIN MAX Condition See Figure 21 5 2 Symbol Parameter Rated Value Unit MIN MAX Condition td BCLK TOi TOi Output Delay Time 100 ns 15 See Figure 21 5 4...

Page 822: ...pzx BCLKL DZ ns 29 BCLK Output Low Pulse Width Data Output Disable Time after BCLK tpxz BCLKH DZ ns 30 11 11 12 12 16 19 24 24 10 11 td BCLKL BLWL td BCLKL BHWL tv BCLKL BHWL tv BCLKL BLWL 18 tc BCLK 2 5 5 See Figure 21 5 6 21 5 7 21 5 8 Symbol Parameter Rated Value Unit MIN MAX Condition td A RDL ns 39 Chip Select Delay Time before Read td CS RDL ns 40 Valid Address Time after Read tv RDH A 41 ns...

Page 823: ...te Byte write mode tpxz BLWH DZ tpxz BHWH DZ 54 ns tc BCLK 2 15 Address Delay Time before Write Byte enable mode td A WRL 69 ns Chip Select Delay Time before Write Byte enable mode td CS WRL 70 ns Valid Address Time after Write Byte enable mode tv WRH A 71 ns Valid Chip Select Time after Write Byte enable mode tv WRH CS 72 ns Byte enable delay time before write Byte enable mode td BLE WRL td BHE W...

Page 824: ... 2VCCE Port input 0 2VCCE 0 8VCCE tsu P E th E P 1 2 3 a CSIO mode with internal clock selected b CSIO mode with external clock selected CLKOUT TxD RxD td CLK D tsu D CLK th CLK D 0 8VCCE 0 2VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE CLKIN TxD RxD td CLK D tsu D CLK th CLK D 0 8VCCE 0 2VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE tc CLK tw CLKH tw CLKL 4 5 6 7 8 12 10 11 9 0 8VCCE 0 2VCCE Figure...

Page 825: ...w SBIL 0 2VCCE 0 2VCCE 13 BCLK TOi td BCLK TOi 0 8VCCE 0 2VCCE 0 2VCCE 15 TINi 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE tw TINi 14 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics Figure 21 5 3 SBI Timing Figure 21 5 4 TOi Timing Figure 21 5 5 TINi Timing ...

Page 826: ...17 16 21 22 24 0 16VCCE Address A11 A30 CS0 CS1 0 43VCCE 0 16VCCE 0 43VCCE 0 16VCCE WAIT tsu WAITL BCLKH 0 16VCCE 0 16VCCE tpzx BCLKL DZ 0 16VCCE td BCLKL RDL tsu D RDH th RDH D tv RDH A tv RDH CS tpzx RDH DZ td CS RDL td A RDL 44 45 46 tw RDL th BCLKH D tw RDH 0 43VCCE tsu D BCLKH td BHWH RDL td BLWH RDL td RDH BHWL td RDH BLWL 56 0 16VCCE td BCLKH A td BCLKH CS 42 43 23 19 20 40 39 55 57 31 32 2...

Page 827: ...8 17 16 21 22 0 43VCCE 0 16VCCE 0 16VCCE 0 16VCCE 0 43VCCE 0 16VCCE WAIT 0 16VCCE 0 16VCCE td BCLKL D tpzx BCLKL DZ tv BCLKH D tpxz BLWH DZ tv BLWH D td CS BLWL tw BHWL tv BHWH D tpxz BHWH DZ td CS BHWL td A BLWL td A BHWL tw BLWL tv BLWH A tv BHWH A tv BLWH CS tv BHWH CS 54 53 td BCLKH A td BCLKH CS 19 20 57 47 48 51 49 50 25 26 28 29 27 30 33 34 td BCLKL BLWL 0 16VCCE td BCLKL RDL 23 0 16VCCE 0 ...

Page 828: ...to TTL level 0 43VCCE 0 16VCCE 0 43VCCE 0 16VCCE RD Address A11 A30 CS0 CS1 0 43VCCE 0 16VCCE 0 16VCCE 0 43VCCE 0 43VCCE 0 16VCCE td WRL D tpxz WRH DZ tv WRH D 71 72 77 75 76 0 16VCCE 0 16VCCE BLE BHE WR tw WRL 68 73 74 69 70 td BHEL WRL td BLEL WRL 0 16VCCE 0 43VCCE td RDH BHEL td RDH BLEL td BHEH RDL td BLEH RDL tv WRH A tv WRH CS tv WRH BLEL tv WRH BHEL td CS WRL td A WRL 80 81 Data output D0 D...

Page 829: ...TRST tw JTCKL 61 65 66 67 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE 0 8VCCE 0 2VCCE 62 0 2VCCE 0 2VCCE 0 8VCCE 0 2VCCE JTCK JTDI JTMS JRST tr tf 0 8VCCE 0 2VCCE 58 59 0 8VCCE 0 2VCCE Figure 21 5 10 Input Transition Time on JTAG pins Figure 21 5 11 JTAG Interface Timing Note Stipulated values are guaranteed values when the test pin load capacitance CL 80 pF Note Stipulated values are guaranteed values when t...

Page 830: ...21 21 24 Ver 0 10 PRELIMINARY PRELIMINARY This is a blank page ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics ...

Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...

Page 832: ...ristics 22 1 A D Conversion Characteristics 1 Test conditions Ta 40 C 27 C 125 C Test voltage VCC 5 12 V Double speed mode 2 Measured value Reference value Vertical axis Conversion error Horizontal axis Analog input voltage 5 12 N 1024 V Ta 40 C Ta 27 C Ta 125 C ...

Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...

Page 834: ...d Material Cu Alloy 240P6Y A Plastic 240pin 32 32mm body QFP 0 35 0 45 Symbol Min Nom Max A A2 b c D E HE L L1 y b2 Dimension in Millimeters HD A1 0 225 I2 1 2 MD 32 6 ME 32 6 10 0 0 1 1 3 0 7 0 5 0 3 34 8 34 6 34 4 34 8 34 6 34 4 0 5 32 1 32 0 31 9 32 1 32 0 31 9 0 2 0 15 0 13 0 3 0 2 0 15 3 6 0 25 4 1 e e e E c H E 1 60 61 HD D MD M E A F b A 1 A 2 L1 L y b 2 I2 Recommended Mount Pad Detail F 24...

Page 835: ...55F7F 255pin 17 17mm body FBGA 0 8 19 15 2 A 0 8TYP 17TYP 0 8 19 15 2 0 8TYP B 1 2MAX C 0 1 C 0 35 0 05 16 6 17TYP 16 6 0 20 C B 0 2 4 255 φ0 45 0 05 φ0 08 C M AB Under Development 0 20 C A Y W V U T R P N M L K J H G F E D C B A Recommended Mount Pad 255FBGA Note 255FBGA is currently under development 0 32mm 0 3mm Metal wiring Cu pattern Ni Au plating via Solder resist Cu pattern P C B side Packa...

Page 836: ...Appendix 1 Appendix 1 4 Ver 0 10 MECHANICAL SPECIFICATIONS Appendix 1 1 Dimensional Outline Drawing This is a blank page ...

Page 837: ...Appendix 2 1 32170 Instruction Processing Time APPENDIX 2 APPENDIX 2 INSTRUCTION PROCESSING TIME ...

Page 838: ...nstruction fetch and D decode stages not just E execution stage must also be taken into account The table below shows the instruction processing time in each pipelined stage of the M32R Table 2 1 1 Instruction Processing Time of Each Pipeline Stage Number of execution cycles in each stage Note 1 Instruction IF D E MEM WB Load instructions LD LDB LDUB LDH LDUH LOCK R 1 1 R 1 Store instructions ST S...

Page 839: ...struction processing may take more time than the calculated value R read cycle Cycles When existing in instruction queue 1 When reading internal resource ROM RAM 1 When reading internal resource SFR byte halfword 2 When reading internal resource SFR word 4 When reading external memory byte halfword 5 Note When reading external memory word 9 Note When successively fetching instructions from externa...

Page 840: ...Appendix 2 Appendix 2 4 Ver 0 10 INSTRUCTION PROCESSING TIME Appendix 2 1 32170 Instruction Processing Time This is a blank page ...

Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...

Page 842: ... the microcomputer ____________ 1 Wiring of the RESET pin _____________ Reduce the length of wiring connecting to the RESET pin Especially when connecting a _____________ capacitor between the RESET and VSS pins make sure it is connected to each pin with the shortest possible wiring within 20 mm Reasons Reset is a function to initialize the internal logic of the microcomputer The pulse width appli...

Page 843: ... if a noise induced potential difference exists between the microcomputer s VSS level and the oscillator s VSS level the clock fed into the microcomputer may not be an exact clock Figure 3 1 2 Wiring of Clock Input Output Pins 3 Wiring of operation mode setup pins When connecting operation mode setup pins and the VCC or VSS pin make sure they are connected with the shortest possible wiring Reasons...

Page 844: ...w The wiring length between VSS pin and bypass capacitor and that between VCC pin and bypass capacitor are equal The wiring length between VSS pin and bypass capacitor and that between VCC pin and bypass capacitor are the shortest possible The VSS and VCC lines are comprised of wiring in greater width than that of other signal lines Figure 3 1 4 Bypass Capacitor between VSS and VCC Lines AA AA AAA...

Page 845: ...rter input pin normally is an output signal from a sensor In many cases a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted so that wiring to the analog input pin inevitably is long Because a long wiring serves as an antenna which draws noise into the microcomputer the signal fed into the analog input pin tends to be noise ridden Furthermore if...

Page 846: ...t signal lines Signal lines in which a large current flows exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer especially the oscillator as possible Reasons Systems using the microcomputer contain signal lines to control for example a motor LED and thermal head When a large current flows in these signal lines it generates noise ...

Page 847: ...l lines and other noise sensitive signal lines Reasons Rapidly level changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls Especially if they intersect clock related signal lines they will cause the clock waveform to become distorted which may result in the microcomputer operating erratically or getting out of control Figure 3 1 7 Wiring of Rapid...

Page 848: ... _ Insert resistors of 100 Ω or more in series to input output ports Software measures For input ports read out data in a program two or more times to verify that levels match For output ports rewrite the data register at certain intervals because there is a possibility of the output data being inverted by noise Rewrite the direction register at certain intervals Noise Direction register Data regi...

Page 849: ... Manual Ver 0 10 March 17 2000 Copyright 2000 MITSUBISHI ELECTRIC CORPORATION Copyright 2000 MITSUBISHI ELECTRIC SEMICONDUCTOR SYSTEMS CORPORATION All Rights Reversed No part of this manual may be reproduced or distributed in any form or by any means without the written permission of Mitsubishi ...

Page 850: ...MSD M32170 U 0003 Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor Systems Corporation M32R Family M32R E Series 32170 Group User s Manual Preliminary Ver 0 10 ...

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