Mitsubishi Electric M32170F3VFP, User Manual

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9
9-38 Ver.0.10
DMAC
9.4 Precautions about the DMAC
9.4 Precautions about the DMAC
• About writing to DMAC related registers
Because DMA transfer involves exchanging data via the internal bus, basically you only can write to
the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit
= 0). When transfer is enabled, do not write to the DMAC related registers because write operation
to those registers, except the DMA transfer enable bit, transfer request flag, and the DMA Transfer
Count Register which is protected in hardware, is instable.
The table below shows the registers that can or cannot be accessed for write.
Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write
Status Transfer enable bit Transfer request flag Other DMAC related registers
When transfer is enabled
✕
When transfer is disabled
: Can be accessed ;
✕
: Cannot be accessed
For even registers that can exceptionally be written to while transfer is enabled, the following
requirements must be met.
➀
DMA Channel Control Register's transfer enable bit and transfer request flag
For all other bits of the channel control register, be sure to write the same data that those
bits had before you wrote to the transfer enable bit or transfer request flag. Note that you
only can write a 0 to the transfer request flag as valid data.
➁
DMA Transfer Count Register
When transfer is enabled, this register is protected in hardware, so that any data you write
to this register is ignored.
➂
Rewriting the DMA source and DMA destination addresses on different channels by DMA
transfer
In this case, you are writing to the DMAC related registers while DMA is enabled, but this
practically does not present any problem. However, you cannot DMA-transfer to the DMAC
related registers on the local channel itself in which you are currently operating.