Mitsubishi Electric M32170F3VFP, User Manual

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9
9-37 Ver.0.10
DMAC
9.3 Functional Description of the DMAC
9.3.10 End of DMA and Interrupt
In normal mode, DMA transfer is terminated when the transfer count register underflows. When
transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. Also, an
interrupt request is generated at completion of transfer. However, this interrupt is not generated for
channels where interrupt requests have been masked by the DMA Interrupt Mask Register.
During ring buffer mode, the transfer count register operates in free-run mode, and transfer
continues until the transfer enable bit is cleared to 0 (to disable transfer). In this case, therefore, the
DMA transfer-completed interrupt request is not generated. Nor is this interrupt request generated
even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.
9.3.11 Status of Each Register after Completion of DMA Transfer
When DMA transfer is completed, the status of the source address and destination address
registers becomes as follows:
(1) Address fixed
• The value set in the address register before DMA transfer started remains intact (fixed).
(2) Address incremental
• For 8-bit transfer, the value of the address register is the last transfer a 1.
• For 16-bit transfer, the value of the address register is the last transfer a 2.
The transfer count register when DMA transfer completed is in an underflow state (H'FF).
Therefore, to perform another DMA transfer, set the transfer count register newly again, except
when you are performing transfers 256 times (H'FF).