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Ver.0.10
SERIAL I/O
12.7 Receive Operation in UART Mode
12.7.2 Starting UART Reception
When all of the following receive conditions are met after you finished initialization, the serial I/O
starts receive operation.
• The SIO Receive Control Register's receive enable bit is set to 1
• Start bit (falling edge signal) is applied to the RXD pin
When the above conditions are met, the serial I/O enters UART receive operation. However, if the
start bit when checked again at the first rise of the internal receive shift clock is detected high for
reason of noise, etc., the serial I/O stops receive operation and waits for the start bit again.
12.7.3 Processing at End of UART Reception
When data reception is completed, the following operation is automatically performed in hardware.
(1) When reception is completed normally
The receive-finished (receive buffer full) bit is set to 1.
Note 1 : If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request
is generated.
Note 2 : A DMA transfer request is generated.
(2) When error occurs during reception
When an error occurs during reception, the corresponding error bit (OE, FE, or PE) and the
receive sum bit are set to 1.
Note 1 : If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt
Select Register), a receive-finished interrupt request is generated when interrupt
requests are enabled. However, if an overrun error has occurred, this interrupt is not
generated.
Note 2 : If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select
Register), a receive error interrupt request is generated when interrupt requests are
enabled.
Note 3 : No DMA transfer requests are generated.
Summary of Contents for M32170F3VFP
Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...
Page 56: ...2 2 14 Ver 0 10 This is a blank page ...
Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...
Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...
Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...
Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...
Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...
Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...