10
10-201
Ver.0.10
MULTIJUNCTION TIMERS
10.8 TOD (Output-related 16-bit Timer)
10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function)
(1) Outline of TOD continuous output mode
In continuous output mode, the timer counts down clock pulses starting from the set value of the
counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this
operation is repeated each time the counter underflows, thus generating consecutive pulses
whose waveform is inverted in width of (reload 0 register set value + 1).
When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable
bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's
set value synchronously with the count clock and when the minimum count is reached, generates
an underflow. This underflow causes the counter to be reloaded with the content of reload 0
register and start counting over again. Thereafter, this operation is repeated each time an
underflow occurs. To stop the counter, disable count by writing to the enable bit in software.
The F/F output waveform in continuous output mode is inverted (F/F output levels change from
low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the
timer stops counting. Also, an interrupt can be generated each time the counter underflows.
The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For
details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output
Mode (Without Correction Function)."
(2) Precautions to be observed when using TOD continuous output mode
The following describes precautions to be observed when using TOD continuous output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing
to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you
get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at
the next clock edge.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a
finite time equal to a prescaler delay is included before F/F starts operating after the timer is
enabled.
Summary of Contents for M32170F3VFP
Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...
Page 56: ...2 2 14 Ver 0 10 This is a blank page ...
Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...
Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...
Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...
Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...
Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...
Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...