11
11-25
Ver.0.10
(1) ADnSMSL (A-Dn conversion mode selection) bit (D8)
This bit selects A-D conversion mode for the A-Dn converter during single mode. Setting this bit
to 0 selects A-D conversion mode, and setting this bit to 1 selects comparator mode.
(2) ADnSSPD (A-Dn conversion rate selection) bit (D9)
This bit selects an A-D conversion rate for the A-Dn converter during single mode. Setting this bit
to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed (two times normal speed).
(3) ANsSEL (analog input pin selection) bits (D12-D15)
These bits select analog input pins for the A-Dn converter during single mode. It is the channels
selected by these bits that are operated on for A-D conversion or comparate operation. When
you read these bits, they show the values written to them.
A-D CONVERTERS
11.2 A-D Converter Related Registers
Summary of Contents for M32170F3VFP
Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...
Page 56: ...2 2 14 Ver 0 10 This is a blank page ...
Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...
Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...
Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...
Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...
Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...
Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...