Appendix 2
Appendix 2-3
Ver.0.10
INSTRUCTION PROCESSING TIME
Appendix 2.1 32170 Instruction Processing Time
The following shows the number of memory access cycles in IF and MEM stages. Shown here are
the minimum number of cycles required for memory access. Therefore, these values do not always
reflect the number of cycles required for actual memory or bus access.
In write access, for example, although the CPU finishes the MEM stage by only writing to the write
buffer, this operation actually is followed by a write to memory. Depending on the memory or bus
state before or after the CPU requested a memory access, the instruction processing may take
more time than the calculated value.
■
R (read cycle)
Cycles
When existing in instruction queue ............................................................................. 1
When reading internal resource (ROM, RAM) ........................................................... 1
When reading internal resource (SFR)(byte, halfword) .............................................. 2
When reading internal resource (SFR)(word) ............................................................ 4
When reading external memory (byte, halfword) ....................................................... 5 (Note)
When reading external memory (word) ...................................................................... 9 (Note)
When successively fetching instructions from external memory ................................ 8 (Note)
■
W (write cycle)
Cycles
When writing to internal resource (RAM) ................................................................... 1
When writing to internal resource (SFR)(byte, halfword) ........................................... 2
When writing to internal resource (SFR)(word) .......................................................... 4
When writing to external memory (byte, halfword) ..................................................... 4 (Note)
When writing to external memory (word) .................................................................... 8 (Note)
Note: This applies for external access with one wait cycle. (When the 32170 accesses external
circuits, it requires at least one wait cycle inserted.)
Summary of Contents for M32170F3VFP
Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...
Page 56: ...2 2 14 Ver 0 10 This is a blank page ...
Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...
Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...
Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...
Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...
Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...
Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...