Mitsubishi Electric M32170F3VFP, User Manual

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15
15-6 Ver.0.10
EXTERNAL BUS INTERFACE
15.2 Read/Write Operations
15.2 Read/Write Operations
(1) When Bus Mode Control Register = 0
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External read/write operations are performed using the address bus, data bus, and signals CS0,
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CS1, RD, BHW, BLW, WAIT, and BCLK. In external read cycle, the RD signal is low while BHW and
BLW both are high, reading data from only the valid byte position of the bus. In external write cycle,
BHW or BLW output for the byte position to which to write is pulled low as data is written to the bus.
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When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low.
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Unless the WAIT signal is needed, leave it held high. During external bus cycles, at least one wait
cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.)
Figure 15.2.1 Internal Bus Access during Bus Free State
Note : THi-Z denotes a high-impedance state.
Bus-free state
internal bus access
"H"
BCLK
A11 - A30
CS0, CS1
BHW, BLW
DB0 - DB15
WAIT
RD
"H"
Hi-z
"H"