9
9-36
Ver.0.10
DMAC
9.3 Functional Description of the DMAC
Figure 9.3.4 Example of Address Increment Operation in 32-Channel Ring Buffer Mode
(7) Ring buffer mode
When ring buffer mode is selected, transfer begins from the transfer start address and after
performing transfers 32 times, control is recycled back to the transfer start address, from which
transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start
address must always be B'00000. The address increment operation in ring buffer mode is
described below.
➀
When the transfer unit = 8 bits
The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are
incremented by one at a time. When as transfer proceeds the five low-order bits reach
B'11111, they are recycled to B'00000 by the next increment operation, thus returning to
the start address again.
➁
When the transfer unit = 16 bits
The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are
incremented by two at a time. When as transfer proceeds the six low-order bits reach
B'111110, they are recycled to B'000000 by the next increment operation, thus returning to
the start address again.
When the source address has been set to be incremented, it is the source address that recycles
to the start address; when the destination address has been set to be incremented, it is the
destination address that recycles to the start address. If both source and destination addresses
have been set to be incremented, both addresses recycle to the start address. However, the start
address on either side must have their five low-order bits initially being B'00000.
During ring buffer mode, the transfer count register is ignored. Also, once DMA operation starts,
the counter operates in free-run mode, and the transfer continues until the transfer enable bit is
cleared to (to disable transfer).
<When transfer unit = 8 bits>
Transfer count
Transfer address
1
H'0080 1000
2
H'0080 1001
3
H'0080 1002
|
|
31
H'0080 101E
32
H'0080 101F
↓
↓
1
H'0080 1000
2
H'0080 1001
|
|
<When transfer unit = 16 bits>
Transfer count
Transfer address
1
H'0080 1000
2
H'0080 1002
3
H'0080 1004
|
|
31
H'0080 103C
32
H'0080 103E
↓
↓
1
H'0080 1000
2
H'0080 1002
|
|
Summary of Contents for M32170F3VFP
Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...
Page 56: ...2 2 14 Ver 0 10 This is a blank page ...
Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...
Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...
Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...
Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...
Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...
Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...