9
9-32
Ver.0.10
DMAC
9.3 Functional Description of the DMAC
Figure 9.3.2 Gaining and Releasing Control of the Internal Bus
9.3.3 Starting DMA
Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable
DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause
of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1.
9.3.4 Channel Priority
Channel 0 has the highest priority. The priority of this and other channels is shown below.
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 >
channel 8 > channel 9
This order of priority is fixed and cannot be changed. Among channels for which DMA transfers are
requested, the channel that has the highest priority is selected. Channel selection is made every
transfer cycle (one DMA bus cycle consisting of three machine cycles).
9.3.5 Gaining and Releasing Control of the Internal Bus
For any channel, control of the internal bus is gained and released in "single transfer DMA" mode.
In single transfer DMA, the DMA gains control of the internal bus when DMA transfer request is
accepted and after executing one DMA transfer (consisting of one read cycle + one write cycle of
internal peripheral clock), returns bus control to the CPU. The diagram below shows DMA
operation in single transfer DMA.
One DMA transfer
DMAC
CPU
Internal bus
arbitration (control
requested by DMAC)
Internal
bus
R: Read
W: Write
R
W
R
W
R
W
Requested
Gained
Released
Requested
Gained
Requested
Gained
Released
Released
One DMA transfer
One DMA transfer
Summary of Contents for M32170F3VFP
Page 42: ...1 1 24 Ver 0 10 OVERVIEW 1 4 Pin Layout This is a blank page ...
Page 56: ...2 2 14 Ver 0 10 This is a blank page ...
Page 88: ...3 3 32 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page ...
Page 270: ...9 9 40 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page ...
Page 614: ...12 12 64 Ver 0 10 This is a blank page SERIAL I O 12 9 Precautions on Using UART Mode ...
Page 756: ...17 17 10 Ver 0 10 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page ...
Page 762: ...18 18 6 Ver 0 10 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit This is a blank page ...
Page 831: ...CHAPTER 22 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics ...
Page 833: ...Appendix 1 1 Dimensional Outline Drawing APPENDIX 1 APPENDIX 1 MECHANICAL SPECIFICATIONS ...
Page 841: ...Appendix 3 1 Precautions about Noise APPENDIX 3 APPENDIX 3 PRECAUTIONS ABOUT NOISE ...